mcpat/cacti/uca.cc

249     power_routing_to_bank.readOp.gate_leakage +=
250         htree_in_add->power.readOp.gate_leakage +
251         htree_in_data->power.readOp.gate_leakage +
252         htree_out_data->power.readOp.gate_leakage;
255         power_routing_to_bank.readOp.gate_leakage += htree_in_search->power.readOp.gate_leakage + htree_out_search->power.readOp.gate_leakage;
261     power.readOp.gate_leakage += power_routing_to_bank.readOp.gate_leakage;
333         (bank.mat.r_predec->power.readOp.gate_leakage +
334          bank.mat.b_mux_predec->power.readOp.gate_leakage +
335          bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage +
336          bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage +
337          bank.mat.power_row_decoders.readOp.gate_leakage +
338          bank.mat.power_bit_mux_decoders.readOp.gate_leakage +
339          bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage +
340          bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * dp.num_act_mats_hor_dir; //+
355         (bank.mat.r_predec->power.readOp.gate_leakage +
356          bank.mat.b_mux_predec->power.readOp.gate_leakage +
357          bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage +
358          bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage +
359          bank.mat.power_row_decoders.readOp.gate_leakage +
360          bank.mat.power_bit_mux_decoders.readOp.gate_leakage +
361          bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage +
362          bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage ) * dp.num_act_mats_hor_dir;
372         power_routing_to_bank.readOp.gate_leakage +
373         bank.htree_in_add->power.readOp.gate_leakage +
374         bank.htree_in_data->power.readOp.gate_leakage +
375         bank.htree_out_data->power.readOp.gate_leakage;
379         leak_power_request_and_reply_networks += htree_in_search->power.readOp.gate_leakage + htree_out_search->power.readOp.gate_leakage;