Lines Matching refs:delay
121 // delay calculation
140 double delay_array_to_mat = htree_in_add->delay + bank.htree_in_add->delay;
141 double max_delay_before_row_decoder = delay_array_to_mat + bank.mat.r_predec->delay;
143 bank.mat.sa_mux_lev_1_predec->delay +
144 bank.mat.sa_mux_lev_1_dec->delay;
146 bank.mat.sa_mux_lev_2_predec->delay +
147 bank.mat.sa_mux_lev_2_dec->delay;
148 double delay_inside_mat = bank.mat.row_dec->delay + bank.mat.delay_bitline + bank.mat.delay_sa;
152 delay_array_to_mat + bank.mat.b_mux_predec->delay + bank.mat.bit_mux_dec->delay + bank.mat.delay_sa), // col_path
156 bank.htree_out_data->delay + htree_out_data->delay;
161 //delay of FA contains both CAM tag and RAM data
162 { //delay of CAM
164 access_time = htree_in_add->delay + bank.htree_in_add->delay;
165 //delay of fully-associative data array
188 temp = MAX(temp, bank.mat.r_predec->delay);
189 temp = MAX(temp, bank.mat.b_mux_predec->delay);
190 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
191 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
197 temp = MAX(temp, bank.mat.b_mux_predec->delay);//TODO: Sheng revisit whether distinguish cam and ram bitline etc.
198 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
199 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
213 multisubbank_interleave_cycle_time = htree_in_add->delay;
214 precharge_delay = htree_in_add->delay +
215 bank.htree_in_add->delay + bank.mat.delay_writeback +