Lines Matching refs:MAX
151 MAX(MAX(max_delay_before_row_decoder + delay_inside_mat, // row_path
153 MAX(delay_array_to_sa_mux_lev_1_decoder, // sa_mux_lev_1_path
174 double cas_latency = MAX(delay_array_to_sa_mux_lev_1_decoder, delay_array_to_sa_mux_lev_2_decoder) +
188 temp = MAX(temp, bank.mat.r_predec->delay);
189 temp = MAX(temp, bank.mat.b_mux_predec->delay);
190 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
191 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
197 temp = MAX(temp, bank.mat.b_mux_predec->delay);//TODO: Sheng revisit whether distinguish cam and ram bitline etc.
198 temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay);
199 temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay);
204 temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay);
210 multisubbank_interleave_cycle_time = MAX(delay_req_network, delay_rep_network);
285 (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1) *
405 (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1); //FIXME