mcpat/cacti/router.cc

142     DynamicParameter dyn_p;
143     dyn_p.is_tag      = false;
144     dyn_p.pure_cam    = false;
145     dyn_p.fully_assoc = false;
146     dyn_p.pure_ram    = true;
147     dyn_p.is_dram     = false;
148     dyn_p.is_main_mem = false;
149     dyn_p.num_subarrays = 1;
150     dyn_p.num_mats = 1;
151     dyn_p.Ndbl = 1;
152     dyn_p.Ndwl = 1;
153     dyn_p.Nspd = 1;
154     dyn_p.deg_bl_muxing = 1;
155     dyn_p.deg_senseamp_muxing_non_associativity = 1;
156     dyn_p.Ndsam_lev_1 = 1;
157     dyn_p.Ndsam_lev_2 = 1;
158     dyn_p.Ndcm = 1;
159     dyn_p.number_addr_bits_mat = 8;
160     dyn_p.number_way_select_signals_mat = 1;
161     dyn_p.number_subbanks_decode = 0;
162     dyn_p.num_act_mats_hor_dir = 1;
163     dyn_p.V_b_sense = Vdd; // FIXME check power calc.
164     dyn_p.ram_cell_tech_type = 0;
165     dyn_p.num_r_subarray = (int) vc_buffer_size;
166     dyn_p.num_c_subarray = (int) flit_size * (int) vc_count;
167     dyn_p.num_mats_h_dir = 1;
168     dyn_p.num_mats_v_dir = 1;
169     dyn_p.num_do_b_subbank = (int)flit_size;
170     dyn_p.num_di_b_subbank = (int)flit_size;
171     dyn_p.num_do_b_mat = (int) flit_size;
172     dyn_p.num_di_b_mat = (int) flit_size;
173     dyn_p.num_do_b_mat = (int) flit_size;
174     dyn_p.num_di_b_mat = (int) flit_size;
175     dyn_p.num_do_b_bank_per_port = (int) flit_size;
176     dyn_p.num_di_b_bank_per_port = (int) flit_size;
177     dyn_p.out_w = (int) flit_size;
179     dyn_p.use_inp_params = 1;
180     dyn_p.num_wr_ports = (unsigned int) vc_count;
181     dyn_p.num_rd_ports = 1;//(unsigned int) vc_count;//based on Bill Dally's book
182     dyn_p.num_rw_ports = 0;
183     dyn_p.num_se_rd_ports = 0;
184     dyn_p.num_search_ports = 0;
188     dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_wr_ports +
189                    dyn_p.num_rw_ports - 1 + dyn_p.num_rd_ports);
190     dyn_p.cell.w = g_tp.sram.b_w + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_rw_ports - 1 +
191                    (dyn_p.num_rd_ports - dyn_p.num_se_rd_ports) +
192                    dyn_p.num_wr_ports) + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports;
194     Mat buff(dyn_p);