Lines Matching defs:wire_local
163 wire_local.display(indent + 2);
209 const TechnologyParameter::InterconnectType & wire_local = g_tp.wire_local;
321 cam_cell.h = g_tp.cam.b_h + 2 * wire_local.pitch *
323 + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) +
324 wire_local.pitch * g_ip->num_se_rd_ports;
325 cam_cell.w = g_tp.cam.b_w + 2 * wire_local.pitch *
327 + 2 * wire_local.pitch * (g_ip->num_search_ports - 1) +
328 wire_local.pitch * g_ip->num_se_rd_ports;
330 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch *
332 + 2 * wire_local.pitch * (g_ip->num_search_ports - 1);
333 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch *
336 + g_ip->num_wr_ports) + g_tp.wire_local.pitch *
337 g_ip->num_se_rd_ports + 2 * wire_local.pitch *
341 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 + g_ip->num_rd_ports +
343 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 + g_ip->num_wr_ports +
345 wire_local.pitch * g_ip->num_se_rd_ports;
351 cell.h = g_tp.sram.b_h + 2 * wire_local.pitch * (g_ip->num_wr_ports +
353 cell.w = g_tp.sram.b_w + 2 * wire_local.pitch * (g_ip->num_rw_ports - 1 +
355 g_ip->num_wr_ports) + g_tp.wire_local.pitch * g_ip->num_se_rd_ports;
360 double c_b_metal = cell.h * wire_local.C_per_um;
399 c_b_metal = cam_cell.h * wire_local.C_per_um;//IBM and SUN design, SRAM array uses dummy cells to fill the blank space due to mismatch on CAM-RAM