Lines Matching refs:tr_R_on

488             rd = tr_R_on(ml_to_ram_wl_drv->width_n[k], NCH, 1, is_dram, false, true);
498 R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
539 double rd = tr_R_on(row_dec->w_dec_n[k], NCH, 1, is_dram, false, true);
549 double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);
789 double R_bl_precharge = tr_R_on(g_tp.w_pmos_bl_precharge, PCH, 1, is_dram, false, false);//Assuming CAM and SRAM have same Pre_eq_dr
819 rd = tr_R_on(Wdummyn, NCH, 2, is_dram);
830 double R_ml_precharge = tr_R_on(Wfaprechp, PCH, 1, is_dram);
850 rd = tr_R_on(Waddrnandn, NCH, 2, is_dram);
864 rd = tr_R_on(Wdummyinvn, NCH, 1, is_dram);
894 rd = tr_R_on(Wfanorn, NCH, 1, is_dram);
918 rd = tr_R_on(W_hit_miss_p, PCH, 1, is_dram, false, false);
934 rd = tr_R_on(W_hit_miss_n, PCH, 1, is_dram, false, false);
1022 double R_sram_cell_pull_up_tr = tr_R_on(g_tp.sram.cell_pmos_w, NCH, 1, is_dram, true);
1023 double R_access_tr = tr_R_on(g_tp.sram.cell_a_w, NCH, 1, is_dram, true);
1068 R_cell_acc = tr_R_on(g_tp.dram.cell_a_w, NCH, 1, true, true);
1074 R_cell_pull_down = tr_R_on(g_tp.sram.cell_nmos_w, NCH, 1, false, true);
1075 R_cell_acc = tr_R_on(g_tp.sram.cell_a_w, NCH, 1, false, true);
1107 double R_bit_mux = tr_R_on(g_tp.w_nmos_b_mux, NCH, 1, is_dram);
1112 double R_sense_amp_iso = tr_R_on(g_tp.w_iso, PCH, 1, is_dram);
1272 rd = tr_R_on(g_tp.w_nmos_sa_mux, NCH, 1, is_dram);
1288 rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1, is_dram);
1305 rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1, is_dram);
1326 rd = tr_R_on(g_tp.w_nmos_sa_mux, NCH, 1, is_dram);
1361 double Req = tr_R_on(g_tp.w_comp_inv_p1, PCH, 1, is_dram);
1379 Req = tr_R_on(g_tp.w_comp_inv_n2, NCH, 1, is_dram);
1393 Req = tr_R_on(g_tp.w_comp_inv_p3, PCH, 1, is_dram);
1404 double r1 = tr_R_on(g_tp.w_comp_n, NCH, 2, is_dram);
1405 double r2 = tr_R_on(g_tp.w_eval_inv_n, NCH, 1, is_dram); /* was switch */