Lines Matching refs:width_nand3_path_p
997 width_nand3_path_p[i] = 0;
1109 width_nand3_path_p[0] = p_to_n_sz_ratio * width_nand3_path_n[0];
1110 F = c_load_nand3_path_out / gate_C(width_nand3_path_n[0] + width_nand3_path_p[0], 0, is_dram_);
1116 width_nand3_path_p,
1159 compute_gate_area(INV, 1, width_nand3_path_p[i],
1162 cmos_Isub_leakage(width_nand3_path_n[i], width_nand3_path_p[i],
1165 cmos_Ig_leakage(width_nand3_path_n[i], width_nand3_path_p[i],
1222 c_gate_load = gate_C(width_nand3_path_p[i+1] + width_nand3_path_n[i+1], 0.0, is_dram_);
1223 c_intrinsic = drain_C_(width_nand3_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1236 c_intrinsic = drain_C_(width_nand3_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1309 leak_nand3_path += cmos_Isub_leakage(width_nand3_path_n[i], width_nand3_path_p[i], 1, inv,is_dram_);
1310 gate_leak_nand3_path += cmos_Ig_leakage(width_nand3_path_n[i], width_nand3_path_p[i], 1, inv,is_dram_);