Lines Matching refs:width_nand2_path_n
994 width_nand2_path_n[i] = 0;
1090 width_nand2_path_n[0] = g_tp.min_w_nmos_;
1091 width_nand2_path_p[0] = p_to_n_sz_ratio * width_nand2_path_n[0];
1092 F = c_load_nand2_path_out / gate_C(width_nand2_path_n[0] + width_nand2_path_p[0], 0, is_dram_);
1097 width_nand2_path_n,
1139 width_nand2_path_n[i], g_tp.cell_h_def);
1141 cmos_Isub_leakage(width_nand2_path_n[i], width_nand2_path_p[i],
1144 cmos_Ig_leakage(width_nand2_path_n[i], width_nand2_path_p[i],
1194 rd = tr_R_on(width_nand2_path_n[i], NCH, 1, is_dram_);
1195 c_gate_load = gate_C(width_nand2_path_p[i+1] + width_nand2_path_n[i+1], 0.0, is_dram_);
1197 drain_C_(width_nand2_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1208 rd = tr_R_on(width_nand2_path_n[i], NCH, 1, is_dram_);
1210 drain_C_(width_nand2_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1297 leak_nand2_path += cmos_Isub_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);
1298 gate_leak_nand2_path += cmos_Ig_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);