Lines Matching refs:w_L2_n

410             w_L2_n[0] = 2 * g_tp.min_w_nmos_;
413 w_L2_n[0] = 3 * g_tp.min_w_nmos_;
417 F *= C_ld_predec_blk_out / (gate_C(w_L2_n[0], 0, is_dram_) + gate_C(w_L2_p[0], 0, is_dram_));
422 w_L2_n,
437 (gate_C(w_L2_n[0], 0, is_dram_) +
461 (gate_C(w_L2_n[0], 0, is_dram_) +
626 cumulative_area_L2 = compute_gate_area(NAND, 2, w_L2_p[0], w_L2_n[0], g_tp.cell_h_def);
627 leakage_L2 = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
628 gate_leakage_L2 = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
630 cumulative_area_L2 = compute_gate_area(NAND, 3, w_L2_p[0], w_L2_n[0], g_tp.cell_h_def);
631 leakage_L2 = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
632 gate_leakage_L2 = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
636 cumulative_area_L2 += compute_gate_area(INV, 1, w_L2_p[i], w_L2_n[i], g_tp.cell_h_def);
637 leakage_L2 += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
638 gate_leakage_L2 += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
703 (gate_C(w_L2_n[0], 0, is_dram_) +
755 (gate_C(w_L2_n[0], 0, is_dram_) + gate_C(w_L2_p[0], 0,
779 rd = tr_R_on(w_L2_n[0], NCH, 2, is_dram_);
780 c_load = gate_C(w_L2_n[1] + w_L2_p[1], 0.0, is_dram_);
782 drain_C_(w_L2_n[0], NCH, 2, 1, g_tp.cell_h_def, is_dram_);
789 rd = tr_R_on(w_L2_n[0], NCH, 3, is_dram_);
790 c_load = gate_C(w_L2_n[1] + w_L2_p[1], 0.0, is_dram_);
792 drain_C_(w_L2_n[0], NCH, 3, 1, g_tp.cell_h_def, is_dram_);
801 rd = tr_R_on(w_L2_n[i], NCH, 1, is_dram_);
802 c_load = gate_C(w_L2_n[i+1] + w_L2_p[i+1], 0.0, is_dram_);
804 drain_C_(w_L2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
818 rd = tr_R_on(w_L2_n[i], NCH, 1, is_dram_);
820 drain_C_(w_L2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
941 leakage_L2 = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
942 gate_leakage_L2 = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
946 leakage_L2 = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
947 gate_leakage_L2 = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
952 leakage_L2 += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
953 gate_leakage_L2 += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);