mcpat/cacti/decoder.cc

52     bool   is_dram_,
61         fully_assoc(fully_assoc_), is_dram(is_dram_),
294         is_dram_(is_dram) {
320             C_ld_dec_gate = num_dec_per_predec * gate_C(dec->w_dec_n[0] + dec->w_dec_p[0], 0, is_dram_, false, false);
329             C_ld_dec_gate = num_dec_per_predec * gate_C(dec->w_dec_n[0] + dec->w_dec_p[0], 0, is_dram_, false, false);
343     double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram_);
417         F *= C_ld_predec_blk_out / (gate_C(w_L2_n[0], 0, is_dram_) + gate_C(w_L2_p[0], 0, is_dram_));
426                               is_dram_, false,
437                                 (gate_C(w_L2_n[0], 0, is_dram_) +
438                                  gate_C(w_L2_p[0], 0, is_dram_));
442                 (gate_C(w_L1_nand2_n[0], 0, is_dram_) +
443                  gate_C(w_L1_nand2_p[0], 0, is_dram_));
452                                              is_dram_, false,
461                                 (gate_C(w_L2_n[0], 0, is_dram_) +
462                                  gate_C(w_L2_p[0], 0, is_dram_));
466                 (gate_C(w_L1_nand3_n[0], 0, is_dram_) +
467                  gate_C(w_L1_nand3_p[0], 0, is_dram_));
476                                              is_dram_, false,
484                 (gate_C(w_L1_nand2_n[0], 0, is_dram_) +
485                  gate_C(w_L1_nand2_p[0], 0, is_dram_));
494                                              is_dram_, false,
500                 (gate_C(w_L1_nand3_n[0], 0, is_dram_) +
501                  gate_C(w_L1_nand3_p[0], 0, is_dram_));
510                                              is_dram_, false,
528         double leak_L1_nand2      = cmos_Isub_leakage(w_L1_nand2_n[0], w_L1_nand2_p[0], 2, nand, is_dram_);
529         double gate_leak_L1_nand2 = cmos_Ig_leakage(w_L1_nand2_n[0], w_L1_nand2_p[0], 2, nand, is_dram_);
604             leak_L1_nand2      += cmos_Isub_leakage(w_L1_nand2_n[i], w_L1_nand2_p[i], 2, nand, is_dram_);
605             gate_leak_L1_nand2 += cmos_Ig_leakage(w_L1_nand2_n[i], w_L1_nand2_p[i], 2, nand, is_dram_);
613             leak_L1_nand3      += cmos_Isub_leakage(w_L1_nand3_n[i], w_L1_nand3_p[i], 3, nand, is_dram_);
614             gate_leak_L1_nand3 += cmos_Ig_leakage(w_L1_nand3_n[i], w_L1_nand3_p[i], 3, nand, is_dram_);
627             leakage_L2         = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
628             gate_leakage_L2    = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
631             leakage_L2         = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
632             gate_leakage_L2    = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
637             leakage_L2         += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
638             gate_leakage_L2    += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
675             rd = tr_R_on(w_L1_nand2_n[0], NCH, 2, is_dram_);
676             c_load = gate_C(w_L1_nand2_n[1] + w_L1_nand2_p[1], 0.0, is_dram_);
677             c_intrinsic = 2 * drain_C_(w_L1_nand2_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
678                           drain_C_(w_L1_nand2_n[0], NCH, 2, 1, g_tp.cell_h_def, is_dram_);
687                 rd = tr_R_on(w_L1_nand2_n[i], NCH, 1, is_dram_);
688                 c_load = gate_C(w_L1_nand2_n[i+1] + w_L1_nand2_p[i+1], 0.0, is_dram_);
689                 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
690                               drain_C_(w_L1_nand2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
700             rd = tr_R_on(w_L1_nand2_n[i], NCH, 1, is_dram_);
703                     (gate_C(w_L2_n[0], 0, is_dram_) +
704                      gate_C(w_L2_p[0], 0, is_dram_));
705                 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
706                               drain_C_(w_L1_nand2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
714                 c_intrinsic = drain_C_(w_L1_nand2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
715                               drain_C_(w_L1_nand2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
727             rd = tr_R_on(w_L1_nand3_n[0], NCH, 3, is_dram_);
728             c_load = gate_C(w_L1_nand3_n[1] + w_L1_nand3_p[1], 0.0, is_dram_);
729             c_intrinsic = 3 * drain_C_(w_L1_nand3_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
730                           drain_C_(w_L1_nand3_n[0], NCH, 3, 1, g_tp.cell_h_def, is_dram_);
739                 rd = tr_R_on(w_L1_nand3_n[i], NCH, 1, is_dram_);
740                 c_load = gate_C(w_L1_nand3_n[i+1] + w_L1_nand3_p[i+1], 0.0, is_dram_);
741                 c_intrinsic = drain_C_(w_L1_nand3_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
742                               drain_C_(w_L1_nand3_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
752             rd = tr_R_on(w_L1_nand3_n[i], NCH, 1, is_dram_);
755                     (gate_C(w_L2_n[0], 0, is_dram_) + gate_C(w_L2_p[0], 0,
756                                                              is_dram_));
757                 c_intrinsic = drain_C_(w_L1_nand3_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
758                               drain_C_(w_L1_nand3_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
766                 c_intrinsic = drain_C_(w_L1_nand3_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
767                               drain_C_(w_L1_nand3_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
779                 rd = tr_R_on(w_L2_n[0], NCH, 2, is_dram_);
780                 c_load = gate_C(w_L2_n[1] + w_L2_p[1], 0.0, is_dram_);
781                 c_intrinsic = 2 * drain_C_(w_L2_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
782                               drain_C_(w_L2_n[0], NCH, 2, 1, g_tp.cell_h_def, is_dram_);
789                 rd = tr_R_on(w_L2_n[0], NCH, 3, is_dram_);
790                 c_load = gate_C(w_L2_n[1] + w_L2_p[1], 0.0, is_dram_);
791                 c_intrinsic = 3 * drain_C_(w_L2_p[0], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
792                               drain_C_(w_L2_n[0], NCH, 3, 1, g_tp.cell_h_def, is_dram_);
801                 rd = tr_R_on(w_L2_n[i], NCH, 1, is_dram_);
802                 c_load = gate_C(w_L2_n[i+1] + w_L2_p[i+1], 0.0, is_dram_);
803                 c_intrinsic = drain_C_(w_L2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
804                               drain_C_(w_L2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
818             rd = tr_R_on(w_L2_n[i], NCH, 1, is_dram_);
819             c_intrinsic = drain_C_(w_L2_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
820                           drain_C_(w_L2_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
846     double leak_L1_nand2      = cmos_Isub_leakage(w_L1_nand2_n[0], w_L1_nand2_p[0], 2, nand, is_dram_);
847     double gate_leak_L1_nand2 = cmos_Ig_leakage(w_L1_nand2_n[0], w_L1_nand2_p[0], 2, nand, is_dram_);
922       leak_L1_nand2      += cmos_Isub_leakage(w_L1_nand2_n[i], w_L1_nand2_p[i], 2, nand, is_dram_);
923       gate_leak_L1_nand2 += cmos_Ig_leakage(w_L1_nand2_n[i], w_L1_nand2_p[i], 2, nand, is_dram_);
930       leak_L1_nand3      += cmos_Isub_leakage(w_L1_nand3_n[i], w_L1_nand3_p[i], 3, nand, is_dram_);
931       gate_leak_L1_nand3 += cmos_Ig_leakage(w_L1_nand3_n[i], w_L1_nand3_p[i], 3, nand, is_dram_);
941       leakage_L2         = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
942       gate_leakage_L2    = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 2, nand, is_dram_);
946       leakage_L2         = cmos_Isub_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
947       gate_leakage_L2    = cmos_Ig_leakage(w_L2_n[0], w_L2_p[0], 3, nand, is_dram_);
952       leakage_L2         += cmos_Isub_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
953       gate_leakage_L2    += cmos_Ig_leakage(w_L2_n[i], w_L2_p[i], 2, inv, is_dram_);
991         is_dram_(is_dram),
1006             c_load_nand2_path_out = gate_C(dec->w_dec_n[0] + dec->w_dec_p[0], 0, is_dram_);
1009             c_load_nand3_path_out = gate_C(dec->w_dec_n[0] + dec->w_dec_p[0], 0, is_dram_);
1030     double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram_);
1033         double C_nand2_gate_blk = gate_C(blk->w_L1_nand2_n[0] + blk->w_L1_nand2_p[0], 0, is_dram_);
1034         double C_nand3_gate_blk = gate_C(blk->w_L1_nand3_n[0] + blk->w_L1_nand3_p[0], 0, is_dram_);
1092             F = c_load_nand2_path_out / gate_C(width_nand2_path_n[0] + width_nand2_path_p[0], 0, is_dram_);
1101                                           is_dram_, false, g_tp.max_w_nmos_);
1110             F = c_load_nand3_path_out / gate_C(width_nand3_path_n[0] + width_nand3_path_p[0], 0, is_dram_);
1119                                           is_dram_, false, g_tp.max_w_nmos_);
1142                                   1, inv, is_dram_);
1145                                 1, inv, is_dram_);
1163                                   1, inv, is_dram_);
1166                                 1, inv, is_dram_);
1194             rd = tr_R_on(width_nand2_path_n[i], NCH, 1, is_dram_);
1195             c_gate_load = gate_C(width_nand2_path_p[i+1] + width_nand2_path_n[i+1], 0.0, is_dram_);
1196             c_intrinsic = drain_C_(width_nand2_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1197                           drain_C_(width_nand2_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1208             rd = tr_R_on(width_nand2_path_n[i], NCH, 1, is_dram_);
1209             c_intrinsic = drain_C_(width_nand2_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1210                           drain_C_(width_nand2_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1221             rd = tr_R_on(width_nand3_path_n[i], NCH, 1, is_dram_);
1222             c_gate_load = gate_C(width_nand3_path_p[i+1] + width_nand3_path_n[i+1], 0.0, is_dram_);
1223             c_intrinsic = drain_C_(width_nand3_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1224                           drain_C_(width_nand3_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1235             rd = tr_R_on(width_nand3_path_n[i], NCH, 1, is_dram_);
1236             c_intrinsic = drain_C_(width_nand3_path_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1237                           drain_C_(width_nand3_path_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1297       leak_nand2_path += cmos_Isub_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);
1298       gate_leak_nand2_path += cmos_Ig_leakage(width_nand2_path_n[i], width_nand2_path_p[i], 1, inv,is_dram_);
1309       leak_nand3_path += cmos_Isub_leakage(width_nand3_path_n[i], width_nand3_path_p[i], 1, inv,is_dram_);
1310       gate_leak_nand3_path += cmos_Ig_leakage(width_nand3_path_n[i], width_nand3_path_p[i], 1, inv,is_dram_);
1423       is_dram_(is_dram) {
1434     double p_to_n_sz_ratio = pmos_to_nmos_sz_ratio(is_dram_);
1439     double F = c_load / gate_C(width_n[0] + width_p[0], 0, is_dram_);
1448                        is_dram_, false,
1460         rd = tr_R_on(width_n[i], NCH, 1, is_dram_);
1461         c_load = gate_C(width_n[i+1] + width_p[i+1], 0.0, is_dram_);
1462         c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1463                       drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1471             cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *
1474             cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *
1480     rd = tr_R_on(width_n[i], NCH, 1, is_dram_);
1481     c_intrinsic = drain_C_(width_p[i], PCH, 1, 1, g_tp.cell_h_def, is_dram_) +
1482         drain_C_(width_n[i], NCH, 1, 1, g_tp.cell_h_def, is_dram_);
1490         cmos_Isub_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *
1493         cmos_Ig_leakage(width_n[i], width_p[i], 1, inv, is_dram_) *