Lines Matching refs:min_w_pmos
44 min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_;
67 double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) +
68 gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0);
70 // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 +
72 // drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 +
73 // drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
74 // gate_C(TriS2*min_w_pmos, 0);
76 drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 +
78 drain_C_(TriS1 * min_w_pmos, NCH, 1, 1, g_tp.cell_h_def) * 2 +
79 drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) +
80 gate_C(TriS2 * min_w_pmos, 0);
83 drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def);
84 double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0);
99 TriS2 * min_w_pmos, g_tp.cell_h_def);
102 TriS1 * min_w_pmos, g_tp.cell_h_def);
104 TriS1 * 2 * min_w_pmos, g_tp.cell_h_def);
136 cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2,
138 cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3,
140 cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3,
144 cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2,
146 cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3,
148 cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3,