Lines Matching refs:cache_params
72 size = cache_params.capacity;
73 line = cache_params.blockW;
74 assoc = cache_params.assoc;
75 banks = cache_params.nbanks;
76 if ((cache_params.dir_ty == ST &&
77 cache_params.cache_level == L1Directory) ||
78 (cache_params.dir_ty == ST &&
79 cache_params.cache_level == L2Directory)) {
85 if (cache_params.dir_ty == SBT) {
86 dir_overhead = ceil(cache_params.num_cores / BITS_PER_BYTE) *
100 if (cache_params.cache_level == L1) {
106 interface_ip.access_mode = cache_params.cache_access_mode;
107 interface_ip.throughput= cache_params.throughput;
108 interface_ip.latency = cache_params.latency;
114 interface_ip.pure_ram = cache_params.pure_ram;
116 interface_ip.num_rw_ports = cache_params.cache_rw_ports;
117 interface_ip.num_rd_ports = cache_params.cache_rd_ports;
118 interface_ip.num_wr_ports = cache_params.cache_wr_ports;
119 interface_ip.num_se_rd_ports = cache_params.cache_se_rd_ports;
120 interface_ip.num_search_ports = cache_params.cache_search_ports;
123 cache_params.device_ty, clockRate, opt_local,
124 cache_params.core_ty);
216 if (!((cache_params.dir_ty == ST &&
217 cache_params.cache_level == L1Directory) ||
218 (cache_params.dir_ty == ST &&
219 cache_params.cache_level== L2Directory))) {
223 int(ceil(log2(size / cache_params.blockW))) +
224 (cache_params.blockW * BITS_PER_BYTE);
226 size = cache_params.missb_size * line;
230 interface_ip.assoc = cache_params.missb_assoc;
231 interface_ip.nbanks = cache_params.missb_banks;
235 if (cache_params.cache_level == L1) {
241 interface_ip.access_mode = cache_params.miss_buff_access_mode;
247 interface_ip.pure_ram = cache_params.pure_ram;
249 interface_ip.throughput = cache_params.throughput;
250 interface_ip.latency = cache_params.latency;
251 interface_ip.num_rw_ports = cache_params.miss_buff_rw_ports;
252 interface_ip.num_rd_ports = cache_params.miss_buff_rd_ports;
253 interface_ip.num_wr_ports = cache_params.miss_buff_wr_ports;
254 interface_ip.num_se_rd_ports = cache_params.miss_buff_se_rd_ports;
255 interface_ip.num_search_ports = cache_params.miss_buff_search_ports;
258 cache_params.device_ty, clockRate, opt_local,
259 cache_params.core_ty);
274 if (cache_params.dir_ty == SBT) {
283 data = cache_params.blockW;
285 interface_ip.cache_sz = data * cache_params.fu_size;
287 interface_ip.assoc = cache_params.fu_assoc;
288 interface_ip.nbanks = cache_params.fu_banks;
292 if (cache_params.cache_level == L1) {
298 interface_ip.access_mode = cache_params.fetch_buff_access_mode;
305 interface_ip.throughput = cache_params.throughput;
306 interface_ip.latency = cache_params.latency;
307 interface_ip.num_rw_ports = cache_params.fetch_buff_rw_ports;
308 interface_ip.num_rd_ports = cache_params.fetch_buff_rd_ports;
309 interface_ip.num_wr_ports = cache_params.fetch_buff_wr_ports;
310 interface_ip.num_se_rd_ports = cache_params.fetch_buff_se_rd_ports;
311 interface_ip.num_search_ports = cache_params.fetch_buff_search_ports;
313 cache_params.device_ty, clockRate, opt_local,
314 cache_params.core_ty);
329 if (cache_params.dir_ty == SBT) {
338 line = cache_params.blockW;
340 interface_ip.cache_sz = cache_params.prefetchb_size * line;
342 interface_ip.assoc = cache_params.prefetchb_assoc;
343 interface_ip.nbanks = cache_params.prefetchb_banks;
347 if (cache_params.cache_level == L1) {
353 interface_ip.access_mode = cache_params.prefetch_buff_access_mode;
359 interface_ip.pure_ram = cache_params.pure_ram;
361 interface_ip.throughput = cache_params.throughput;
362 interface_ip.latency = cache_params.latency;
363 interface_ip.num_rw_ports = cache_params.pf_buff_rw_ports;
364 interface_ip.num_rd_ports = cache_params.pf_buff_rd_ports;
365 interface_ip.num_wr_ports = cache_params.pf_buff_wr_ports;
366 interface_ip.num_se_rd_ports = cache_params.pf_buff_se_rd_ports;
367 interface_ip.num_search_ports = cache_params.pf_buff_search_ports;
369 cache_params.device_ty, clockRate, opt_local,
370 cache_params.core_ty);
383 if (cache_params.dir_ty == SBT) {
391 if (cache_params.wbb_size > 0) {
393 line = cache_params.blockW;
395 interface_ip.cache_sz = cache_params.wbb_size * line;
397 interface_ip.assoc = cache_params.wbb_assoc;
398 interface_ip.nbanks = cache_params.wbb_banks;
402 if (cache_params.cache_level == L1) {
408 interface_ip.access_mode = cache_params.writeback_buff_access_mode;
414 interface_ip.pure_ram = cache_params.pure_ram;
416 interface_ip.throughput = cache_params.throughput;
417 interface_ip.latency = cache_params.latency;
418 interface_ip.num_rw_ports = cache_params.wb_buff_rw_ports;
419 interface_ip.num_rd_ports = cache_params.wb_buff_rd_ports;
420 interface_ip.num_wr_ports = cache_params.wb_buff_wr_ports;
421 interface_ip.num_se_rd_ports = cache_params.wb_buff_se_rd_ports;
422 interface_ip.num_search_ports = cache_params.wb_buff_search_ports;
425 cache_params.device_ty, clockRate,
426 opt_local, cache_params.core_ty);
441 if (cache_params.dir_ty == SBT) {
459 memset(&cache_params, 0, sizeof(CacheParameters));
483 ASSIGN_FP_IF("size", cache_params.capacity);
484 ASSIGN_FP_IF("block_size", cache_params.blockW);
485 ASSIGN_FP_IF("assoc", cache_params.assoc);
486 ASSIGN_FP_IF("num_banks", cache_params.nbanks);
487 ASSIGN_FP_IF("latency", cache_params.latency);
488 ASSIGN_FP_IF("throughput", cache_params.throughput);
489 ASSIGN_INT_IF("miss_buffer_size", cache_params.missb_size);
490 ASSIGN_INT_IF("fetch_buffer_size", cache_params.fu_size);
491 ASSIGN_INT_IF("prefetch_buffer_size", cache_params.prefetchb_size);
492 ASSIGN_INT_IF("writeback_buffer_size", cache_params.wbb_size);
493 ASSIGN_INT_IF("miss_buffer_assoc", cache_params.missb_assoc);
494 ASSIGN_INT_IF("fetch_buffer_assoc", cache_params.fu_assoc);
495 ASSIGN_INT_IF("prefetch_buffer_assoc", cache_params.prefetchb_assoc);
496 ASSIGN_INT_IF("writeback_buffer_assoc", cache_params.wbb_assoc);
497 ASSIGN_INT_IF("miss_buffer_banks", cache_params.missb_banks);
498 ASSIGN_INT_IF("fetch_buffer_banks", cache_params.fu_banks);
499 ASSIGN_INT_IF("prefetch_buffer_banks", cache_params.prefetchb_banks);
500 ASSIGN_INT_IF("writeback_buffer_banks", cache_params.wbb_banks);
502 cache_params.cache_access_mode, Access_mode);
504 cache_params.miss_buff_access_mode, Access_mode);
506 cache_params.fetch_buff_access_mode, Access_mode);
508 cache_params.prefetch_buff_access_mode, Access_mode);
510 cache_params.writeback_buff_access_mode, Access_mode);
511 ASSIGN_INT_IF("cache_rw_ports", cache_params.cache_rw_ports);
512 ASSIGN_INT_IF("cache_rd_ports", cache_params.cache_rd_ports);
513 ASSIGN_INT_IF("cache_wr_ports", cache_params.cache_wr_ports);
514 ASSIGN_INT_IF("cache_se_rd_ports", cache_params.cache_se_rd_ports);
515 ASSIGN_INT_IF("cache_search_ports", cache_params.cache_search_ports);
516 ASSIGN_INT_IF("miss_buff_rw_ports", cache_params.miss_buff_rw_ports);
517 ASSIGN_INT_IF("miss_buff_rd_ports", cache_params.miss_buff_rd_ports);
518 ASSIGN_INT_IF("miss_buff_wr_ports", cache_params.miss_buff_wr_ports);
520 cache_params.miss_buff_se_rd_ports);
522 cache_params.miss_buff_search_ports);
523 ASSIGN_INT_IF("fetch_buff_rw_ports", cache_params.fetch_buff_rw_ports);
524 ASSIGN_INT_IF("fetch_buff_rd_ports", cache_params.fetch_buff_rd_ports);
525 ASSIGN_INT_IF("fetch_buff_wr_ports", cache_params.fetch_buff_wr_ports);
527 cache_params.fetch_buff_se_rd_ports);
529 cache_params.fetch_buff_search_ports);
530 ASSIGN_INT_IF("pf_buff_rw_ports", cache_params.pf_buff_rw_ports);
531 ASSIGN_INT_IF("pf_buff_rd_ports", cache_params.pf_buff_rd_ports);
532 ASSIGN_INT_IF("pf_buff_wr_ports", cache_params.pf_buff_wr_ports);
533 ASSIGN_INT_IF("pf_buff_se_rd_ports", cache_params.pf_buff_se_rd_ports);
535 cache_params.pf_buff_search_ports);
536 ASSIGN_INT_IF("wb_buff_rw_ports", cache_params.wb_buff_rw_ports);
537 ASSIGN_INT_IF("wb_buff_rd_ports", cache_params.wb_buff_rd_ports);
538 ASSIGN_INT_IF("wb_buff_wr_ports", cache_params.wb_buff_wr_ports);
539 ASSIGN_INT_IF("wb_buff_se_rd_ports", cache_params.wb_buff_se_rd_ports);
541 cache_params.wb_buff_search_ports);
542 ASSIGN_FP_IF("clockrate", cache_params.clockRate);
543 ASSIGN_INT_IF("pure_ram", cache_params.pure_ram);
545 ASSIGN_ENUM_IF("Directory_type", cache_params.dir_ty, Dir_type);
546 ASSIGN_ENUM_IF("device_type", cache_params.device_ty, Device_ty);
547 ASSIGN_ENUM_IF("core_type", cache_params.core_ty, Core_type);
548 ASSIGN_INT_IF("num_cores", cache_params.num_cores);
558 cache_params.clockRate *= 1e6;
559 if (cache_params.clockRate > 0) {
560 clockRate = cache_params.clockRate;
573 cache_params.cache_level = L1;
576 cache_params.cache_level = L2;
579 cache_params.cache_level = L3;
582 cache_params.cache_level = L1Directory;
585 cache_params.cache_level = L2Directory;