ext/mcpat/cacheunit.cc

482         ASSIGN_INT_IF("level", level);
489         ASSIGN_INT_IF("miss_buffer_size", cache_params.missb_size);
490         ASSIGN_INT_IF("fetch_buffer_size", cache_params.fu_size);
491         ASSIGN_INT_IF("prefetch_buffer_size", cache_params.prefetchb_size);
492         ASSIGN_INT_IF("writeback_buffer_size", cache_params.wbb_size);
493         ASSIGN_INT_IF("miss_buffer_assoc", cache_params.missb_assoc);
494         ASSIGN_INT_IF("fetch_buffer_assoc", cache_params.fu_assoc);
495         ASSIGN_INT_IF("prefetch_buffer_assoc", cache_params.prefetchb_assoc);
496         ASSIGN_INT_IF("writeback_buffer_assoc", cache_params.wbb_assoc);
497         ASSIGN_INT_IF("miss_buffer_banks", cache_params.missb_banks);
498         ASSIGN_INT_IF("fetch_buffer_banks", cache_params.fu_banks);
499         ASSIGN_INT_IF("prefetch_buffer_banks", cache_params.prefetchb_banks);
500         ASSIGN_INT_IF("writeback_buffer_banks", cache_params.wbb_banks);
511         ASSIGN_INT_IF("cache_rw_ports", cache_params.cache_rw_ports);
512         ASSIGN_INT_IF("cache_rd_ports", cache_params.cache_rd_ports);
513         ASSIGN_INT_IF("cache_wr_ports", cache_params.cache_wr_ports);
514         ASSIGN_INT_IF("cache_se_rd_ports", cache_params.cache_se_rd_ports);
515         ASSIGN_INT_IF("cache_search_ports", cache_params.cache_search_ports);
516         ASSIGN_INT_IF("miss_buff_rw_ports", cache_params.miss_buff_rw_ports);
517         ASSIGN_INT_IF("miss_buff_rd_ports", cache_params.miss_buff_rd_ports);
518         ASSIGN_INT_IF("miss_buff_wr_ports", cache_params.miss_buff_wr_ports);
519         ASSIGN_INT_IF("miss_buff_se_rd_ports" ,
521         ASSIGN_INT_IF("miss_buff_search_ports",
523         ASSIGN_INT_IF("fetch_buff_rw_ports", cache_params.fetch_buff_rw_ports);
524         ASSIGN_INT_IF("fetch_buff_rd_ports", cache_params.fetch_buff_rd_ports);
525         ASSIGN_INT_IF("fetch_buff_wr_ports", cache_params.fetch_buff_wr_ports);
526         ASSIGN_INT_IF("fetch_buff_se_rd_ports",
528         ASSIGN_INT_IF("fetch_buff_search_ports",
530         ASSIGN_INT_IF("pf_buff_rw_ports", cache_params.pf_buff_rw_ports);
531         ASSIGN_INT_IF("pf_buff_rd_ports", cache_params.pf_buff_rd_ports);
532         ASSIGN_INT_IF("pf_buff_wr_ports", cache_params.pf_buff_wr_ports);
533         ASSIGN_INT_IF("pf_buff_se_rd_ports", cache_params.pf_buff_se_rd_ports);
534         ASSIGN_INT_IF("pf_buff_search_ports",
536         ASSIGN_INT_IF("wb_buff_rw_ports", cache_params.wb_buff_rw_ports);
537         ASSIGN_INT_IF("wb_buff_rd_ports", cache_params.wb_buff_rd_ports);
538         ASSIGN_INT_IF("wb_buff_wr_ports", cache_params.wb_buff_wr_ports);
539         ASSIGN_INT_IF("wb_buff_se_rd_ports", cache_params.wb_buff_se_rd_ports);
540         ASSIGN_INT_IF("wb_buff_search_ports",
543         ASSIGN_INT_IF("pure_ram", cache_params.pure_ram);
544         ASSIGN_INT_IF("tech_type", tech_type);
548         ASSIGN_INT_IF("num_cores", cache_params.num_cores);
549         ASSIGN_INT_IF("wire_mat_type", mat_type);
616         ASSIGN_INT_IF("homenode_read_accesses",
618         ASSIGN_INT_IF("homenode_write_accesses",
620         ASSIGN_INT_IF("homenode_read_misses",
622         ASSIGN_INT_IF("homenode_write_misses",