Lines Matching refs:String
40 RouterInputPort::RouterInputPort(const String& instance_name_, const TechModel* tech_model_)
78 const String& buffer_model = getParameter("BufferModel");
83 " -> Expecting " + (String)number_vns + " number of vcs, got " +
91 " -> Expecting " + (String)number_vns + " number of bufs per vc, got " +
129 const String& ram_name = "RAM";
136 vector<String> rd_addr_dff_names(number_addr_bits, "");
140 rd_addr_dff_names[i] = "RDAddr_DFF" + (String)i;
148 createNet("RDAddr_DFF_Out" + (String)i);
151 portConnect(rd_addr_dffs[i], "Q", "RDAddr_DFF_Out" + (String)i);
158 portConnect(ram, "WRAddr" + (String)i, "FlitIn", makeNetIndex(i));
159 portConnect(ram, "RDAddr" + (String)i, "RDAddr_DFF_Out" + (String)i);
195 rd_addr_dffs[i] = (ElectricalModel*)getSubInstance("RDAddr_DFF" + (String)i);
204 const String& current_event = getGenProperties()->get("UseModelEvent");
212 assignPortTransitionInfo(ram, "WRAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));
213 assignPortTransitionInfo(ram, "RDAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));