Lines Matching refs:String

45     Router::Router(const String& instance_name_, const TechModel* tech_model_)
107 createInputPort("FlitIn" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
111 createOutputPort("FlitOut" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
125 createElectricalEventResult("TraverseCrossbar->Multicast" + (String)i);
126 getEventInfo("TraverseCrossbar->Multicast" + (String)i)->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
140 createNet("PipelineReg2_In" + (String)i);
141 createNet("PipelineReg2_Out" + (String)i);
169 Result* traverse_crossbar_event = getEventResult("TraverseCrossbar->Multicast" + (String)i);
173 traverse_crossbar_event->addSubResult(getSubInstance("Crossbar")->getEventResult("Multicast" + (String)i), "Crossbar", 1.0);
176 traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("DFFD"), "PipelineReg2_" + (String)j, number_bits_per_flit);
177 traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("DFFQ"), "PipelineReg2_" + (String)j, number_bits_per_flit);
178 traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("CK"), "PipelineReg2_" + (String)j, number_bits_per_flit);
208 getSubInstance("PipelineReg2_" + (String)i)->update();
229 const String& current_event = getGenProperties()->get("UseModelEvent");
256 if(current_event == ("TraverseCrossbar->Multicast" + (String)i))
261 crossbar->applyTransitionInfo("Multicast" + (String)i);
277 pipeline_reg2s[i] = (ElectricalModel*)getSubInstance("PipelineReg2_" + (String)i);
309 const String& number_vcs_per_vn = getParameter("NumberVirtualChannelsPerVirtualNetwork");
310 const String& number_bufs_per_vc = getParameter("NumberBuffersPerVirtualChannel");
312 const String& buffer_model = getParameter("InputPort->BufferModel");
315 const String& input_port_name = "InputPort";
358 const String& arb_model = getParameter("SwitchAllocator->ArbiterModel");
361 const String& sw_allocator_name = "SwitchAllocator";
381 const String& crossbar_model = getParameter("CrossbarModel");
393 const String& crossbar_name = "Crossbar";
405 const String& crossbar_sel_dff_name = "Crossbar_Sel_DFF";
422 createNet(String::format("Crossbar_Sel%d_%d", i, j));
424 createNet("Crossbar_Out" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
428 createNet("Crossbar_In" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
438 assignVirtualFanout("Crossbar_In" + (String)i, "PipelineReg1_Out");
439 portConnect(crossbar, "In" + (String)i, "Crossbar_In" + (String)i);
445 assignVirtualFanout(String::format("Crossbar_Sel%d_%d", i, j), "Crossbar_Sel_DFF_Out");
446 portConnect(crossbar, String::format("Sel%d_%d", i, j), String::format("Crossbar_Sel%d_%d", i, j));
448 portConnect(crossbar, "Out" + (String)i, "Crossbar_Out" + (String)i);
449 assignVirtualFanin("PipelineReg2_In" + (String)i, "Crossbar_Out" + (String)i);
465 const String& pipeline_reg0_name = "PipelineReg0";
469 const String& pipeline_reg1_name = "PipelineReg1";
475 vector<String> pipeline_reg2_names(number_output_ports, "");
478 pipeline_reg2_names[i] = "PipelineReg2_" + (String)i;
499 assignVirtualFanin("PipelineReg0_In", "FlitIn" + (String)i);
507 portConnect(pipeline_reg2s[i], "D", "PipelineReg2_In" + (String)i);
508 portConnect(pipeline_reg2s[i], "Q", "PipelineReg2_Out" + (String)i);
509 assignVirtualFanout("FlitOut" + (String)i, "PipelineReg2_Out" + (String)i);
534 const String& clock_tree_model = getParameter("ClockTreeModel");
535 const String& clock_tree_number_levels = getParameter("ClockTree->NumberLevels");
536 const String& clock_tree_wire_layer = getParameter("ClockTree->WireLayer");
537 const String& clock_tree_wire_width_multiplier = getParameter("ClockTree->WireWidthMultiplier");
538 const String& clock_tree_wire_spacing_multiplier = getParameter("ClockTree->WireSpacingMultiplier");
541 const String& clock_tree_name = "ClockTree";