model/electrical/TestModel.cc

67         createNet("A", makeNetIndex(0, num_bits - 1));
68         createNet("B", makeNetIndex(0, num_bits - 1));
69         createNet("S", makeNetIndex(0, num_bits - 1));
97             portConnect(a_reg, "Q", "A", makeNetIndex(i));
107             portConnect(b_reg, "Q", "B", makeNetIndex(i));
117             portConnect(s_reg, "D", "S", makeNetIndex(i));
155         createNet("In0", makeNetIndex(0, mux_bits-1));
156         createNet("In1", makeNetIndex(0, mux_bits-1));
157         createNet("In2", makeNetIndex(0, mux_bits-1));
158         createNet("In3", makeNetIndex(0, mux_bits-1));
159         createNet("In4", makeNetIndex(0, mux_bits-1));
160         createNet("Out", makeNetIndex(0, mux_bits-1));
176             getNet("Out", makeNetIndex(i))->addDownstreamNode(getLoad("OutLoad[" + n + "]"));
178         createNet("Sel", makeNetIndex(0, 2));
179         assign("Sel", makeNetIndex(0), "CK");
180         assign("Sel", makeNetIndex(1), "CK");
181         assign("Sel", makeNetIndex(2), "CK");
203         t2->performTimingOpt(getNet("In1", makeNetIndex(0)), 500e-12);