Lines Matching refs:String
38 OR::OR(const String& instance_name_, const TechModel* tech_model_)
83 createInputPort("In" + (String)i, makeNetIndex(0, number_bits-1));
112 const String& or0_name = "OR_way0";
113 const String& or1_name = "OR_way1";
114 const String& orf_name = "OR2_i" + (String)number_inputs;
142 createNet("way0_In" + (String)i);
143 portConnect(or0, "In" + (String)i, "way0_In" + (String)i);
144 assignVirtualFanin("way0_In" + (String)i, "In" + (String)i);
148 createNet("way1_In" + (String)i);
149 portConnect(or1, "In" + (String)i, "way1_In" + (String)i);
150 assignVirtualFanin("way1_In" + (String)i, "In" + (String)(i + or0_number_inputs));
178 const String& or_name = "OR_bit" + (String)n;
188 portConnect(ors, "In" + (String)i, "In" + (String)i, makeNetIndex(n));
222 propagatePortTransitionInfo(or0, "In" + (String)i, "In" + (String)i);
229 propagatePortTransitionInfo(or1, "In" + (String)i, "In" + (String)i);
233 ElectricalModel* orf = (ElectricalModel*)getSubInstance("OR2_i" + (String)number_inputs);
246 ElectricalModel* or_bit = (ElectricalModel*)getSubInstance("OR_bit" + (String)n);
249 propagatePortTransitionInfo(or_bit, "In" + (String)i, "In" + (String)i);