drampower/src/CmdScheduler.cc

104     cmd.Type = PRECHARGE;
105     cmd.bank = static_cast<unsigned>(i);
106     cmd.name = "PRE";
108       cmd.time = 1 - memSpec.memTimingSpec.TAW;
110       cmd.time = 1 - memSpec.memTimingSpec.FAW;
113     PRE.push_back(cmd);
115     cmd.Type = ACTIVATE;
116     cmd.name = "ACT";
117     ACT.push_back(cmd);
119     cmd.Type = WRITE;
120     cmd.name = "WRITE";
121     cmd.time = -1;
122     RDWR[static_cast<size_t>(i)].push_back(cmd);
256         cmd.bank = 0;
257         cmd.name = "REF";
258         cmd.time = max(max(max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime);
260           cmdScheduling.push_back(cmd);
261           startTime = cmd.time + memTimingSpec.RFC;
301             cmd.bank                  = bankAddr;
302             cmd.PhysicalAddr.bankAddr = cmd.bank;
303             cmd.PhysicalAddr.rowAddr  = PhysicalAddress.rowAddr;
304             cmd.Type                  = ACTIVATE;
305             cmd.name                  = "ACT";
307             cmd.time                  = max(max(ACT[bankaccess - 1].time + tRRD_init,
308                                                 PRE[cmd.bank].time + static_cast<int>(memTimingSpec.RP)),
313               cmd.time = max(max(ACT[bankaccess - 1].time + tRRD_init,
314                                  PRE[cmd.bank].time + static_cast<int>(memTimingSpec.RP)),
320               cmd.time = max(cmd.time, PreRDWR.time + 1);
321               cmd.time = max(cmd.time, timer);
322               cmd.time = max(startTime, cmd.time);
329                 if (RDWR[bankaccess - n][m].time == cmd.time) {
330                   cmd.time      += 1; // ACT is shifted
340             ACT.push_back(cmd);
341             cmdScheduling.push_back(cmd);
349           cmd.bank = bankAddr;
350           cmd.PhysicalAddr.bankAddr = cmd.bank;
351           cmd.PhysicalAddr.rowAddr  = PhysicalAddress.rowAddr;
352           cmd.PhysicalAddr.colAddr  = PhysicalAddress.colAddr + k * burstLength;
353           cmd.Type = transType;
356             cmd.name = "RD";
360             cmd.name = "WR";
366               cmd.time = max(PreRDWR.time + tSwitch_init, ACT.back().time
373             transFinish.time = cmd.time + 1;
379               cmd.name = "RDA";
383               cmd.name = "WRA";
387           PreRDWR = cmd;
389           RDWR[bankAccessNum[bankAddr]].push_back(cmd);
390           cmdScheduling.push_back(cmd);
460     cmd.bank = 0;
461     cmd.name = "PDN_S_PRE";
462     cmd.time = endTime;
463     cmdScheduling.push_back(cmd);
464     cmd.name = "PUP_PRE";
467       cmd.time = cmd.time + memTimingSpec.REFI;
469       cmd.time = cmd.time + pdTime;
472       startTime = cmd.time + memTimingSpec.XP;
474       startTime = cmd.time + memTimingSpec.XPDLL - memTimingSpec.RCD;
476     cmdScheduling.push_back(cmd);
478     cmd.bank      = 0;
479     cmd.name      = "SREN";
480     cmd.time      = endTime;
481     cmdScheduling.push_back(cmd);
483     cmd.name      = "SREX";
484     cmd.time      = cmd.time + pdTime;
487       startTime = cmd.time + memTimingSpec.XS;
489       startTime = cmd.time + memTimingSpec.XSDLL - memTimingSpec.RCD;
491     cmdScheduling.push_back(cmd);