drampower/src/CmdScheduler.cc

58   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
59   nBanks          = memArchSpec.nbrOfBanks;
60   nColumns        = memArchSpec.nbrOfColumns;
61   burstLength     = memArchSpec.burstLength;
62   nbrOfBankGroups = memArchSpec.nbrOfBankGroups;
87   const size_t numBanks = static_cast<size_t>(memSpec.memArchSpec.nbrOfBanks);
91   bankaccess = memSpec.memArchSpec.nbrOfBanks;
103   for (int64_t i = 0; i < memSpec.memArchSpec.nbrOfBanks; i++) {
426     if (ACT.size() >= static_cast<size_t>(memSpec.memArchSpec.nbrOfBanks)) {
501   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
507       tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate;
512       tRWTP_init = memArchSpec.burstLength / memArchSpec.dataRate +
517       tRWTP_init = memTimingSpec.AL + memArchSpec.burstLength /
518                    memArchSpec.dataRate +
531       tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength /
532                    memArchSpec.dataRate - 1 + memTimingSpec.WR;
534       tRWTP_init = memTimingSpec.WL + memArchSpec.burstLength /
535                    memArchSpec.dataRate + memTimingSpec.WR;
554   const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec;
565         tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
566                        memArchSpec.dataRate - 1 + memTimingSpec.WTR;
568         tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
569                        memArchSpec.dataRate + memTimingSpec.WTR;
594       tSwitch_init = memTimingSpec.WL + memArchSpec.burstLength /
595                      memArchSpec.dataRate + tWTR_init;
600     tSwitch_init = memTimingSpec.RL + memArchSpec.burstLength /
601                    memArchSpec.dataRate + 2 - memTimingSpec.WL;
649   uint64_t rowMask  = (memSpec.memArchSpec.nbrOfRows - 1) << rowShift;