Lines Matching refs:True

110         self.sequencer.is_cpu_sequencer = True
118 self.sequencer1.is_cpu_sequencer = True
165 self.sequencer.is_cpu_sequencer = True
364 resourceStalls = True
381 self.noTCCdir = True
398 default=True)
400 default=True)
480 rb_cntrl.isOnCPU = True
508 cp_cntrl.triggerQueue = MessageBuffer(ordered = True)
511 rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
532 rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
555 tcp_cntrl.requestFromTCP = MessageBuffer(ordered = True)
558 tcp_cntrl.responseFromTCP = MessageBuffer(ordered = True)
564 tcp_cntrl.probeToTCP = MessageBuffer(ordered = True)
567 tcp_cntrl.responseToTCP = MessageBuffer(ordered = True)
586 sqc_cntrl.requestFromSQC = MessageBuffer(ordered = True)
589 sqc_cntrl.probeToSQC = MessageBuffer(ordered = True)
592 sqc_cntrl.responseToSQC = MessageBuffer(ordered = True)
612 tcc_cntrl.requestFromTCP = MessageBuffer(ordered = True)
615 tcc_cntrl.responseToCore = MessageBuffer(ordered = True)
624 tcc_cntrl.requestToNB = MessageBuffer(ordered = True)
633 tcc_cntrl.triggerQueue = MessageBuffer(ordered = True)
641 rb_cntrl.requestFromCore = MessageBuffer(ordered = True)
662 rb_cntrl.triggerQueue = MessageBuffer(ordered = True)
705 dir_cntrl.reqToRegDir = MessageBuffer(ordered = True)
708 dir_cntrl.reqFromRegDir = MessageBuffer(ordered = True)
714 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
715 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
723 reg_cntrl = RegionCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits)
730 reg_cntrl.requestToDir = MessageBuffer(ordered = True)
745 reg_cntrl.triggerQueue = MessageBuffer(ordered = True)