configs/example/se.py

176 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
182     system.multi_thread = True
185 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
187 # Create a source clock for the system and set the clock period
188 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
189                                    voltage_domain = system.voltage_domain)
192 system.cpu_voltage_domain = VoltageDomain()
195 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
197                                        system.cpu_voltage_domain)
202     CpuConfig.config_etrace(CPUClass, system.cpu, options)
206 for cpu in system.cpu:
207     cpu.clk_domain = system.cpu_clk_domain
211         system.kvm_vm = KvmVM()
227         system.cpu[i].workload = multiprocesses
229         system.cpu[i].workload = multiprocesses[0]
231         system.cpu[i].workload = multiprocesses[i]
234         system.cpu[i].addSimPointProbe(options.simpoint_interval)
237         system.cpu[i].addCheckerCpu()
241         system.cpu[i].branchPred = bpClass()
245         system.cpu[i].branchPred.indirectBranchPred = indirectBPClass()
247     system.cpu[i].createThreads()
250     Ruby.create_system(options, False, system)
251     assert(options.num_cpus == len(system.ruby._cpu_ports))
253     system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
254                                         voltage_domain = system.voltage_domain)
256         ruby_port = system.ruby._cpu_ports[i]
261         system.cpu[i].createInterruptController()
264         system.cpu[i].icache_port = ruby_port.slave
265         system.cpu[i].dcache_port = ruby_port.slave
267             system.cpu[i].interrupts[0].pio = ruby_port.master
268             system.cpu[i].interrupts[0].int_master = ruby_port.slave
269             system.cpu[i].interrupts[0].int_slave = ruby_port.master
270             system.cpu[i].itb.walker.port = ruby_port.slave
271             system.cpu[i].dtb.walker.port = ruby_port.slave
274     system.membus = SystemXBar()
275     system.system_port = system.membus.slave
276     CacheConfig.config_cache(options, system)
277     MemConfig.config_mem(options, system)
278     config_filesystem(system, options)
280 root = Root(full_system = False, system = system)
281 Simulation.run(options, root, system, FutureClass)