Lines Matching defs:system

201 ########################## Creating the GPU system ########################
278 ########################## Creating the CPU system ########################
408 ########################## Create the overall system ########################
414 # Full list of processing cores in the system. Note that
419 # creating the overall system
421 system = System(cpu = cpu_list,
426 system.future_cpu = future_cpu_list
427 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
428 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
429 voltage_domain = system.voltage_domain)
434 system.vm = KvmVM()
442 GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
444 # create Ruby system
445 system.piobus = IOXBar(width=32, response_latency=0,
447 Ruby.create_system(options, None, system)
448 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
449 voltage_domain = system.voltage_domain)
453 ruby_port = system.ruby._cpu_ports[i]
456 system.cpu[i].createInterruptController()
459 system.cpu[i].icache_port = ruby_port.slave
460 system.cpu[i].dcache_port = ruby_port.slave
462 ruby_port.mem_master_port = system.piobus.slave
464 system.cpu[i].interrupts[0].pio = system.piobus.master
465 system.cpu[i].interrupts[0].int_master = system.piobus.slave
466 system.cpu[i].interrupts[0].int_slave = system.piobus.master
468 system.cpu[i].itb.walker.port = ruby_port.slave
469 system.cpu[i].dtb.walker.port = ruby_port.slave
478 gpu_port_idx = len(system.ruby._cpu_ports) \
487 system.cpu[shader_idx].CUs[i].memory_port[j] = \
488 system.ruby._cpu_ports[gpu_port_idx].slave[j]
495 system.cpu[shader_idx].CUs[i].sqc_port = \
496 system.ruby._cpu_ports[gpu_port_idx].slave
501 system.cpu[cp_idx].createInterruptController()
502 system.cpu[cp_idx].dcache_port = \
503 system.ruby._cpu_ports[gpu_port_idx + i * 2].slave
504 system.cpu[cp_idx].icache_port = \
505 system.ruby._cpu_ports[gpu_port_idx + i * 2 + 1].slave
506 system.cpu[cp_idx].interrupts[0].pio = system.piobus.master
507 system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave
508 system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master
511 # connect dispatcher to the system.piobus
512 dispatcher.pio = system.piobus.master
513 dispatcher.dma = system.piobus.slave
534 root = Root(system=system, full_system=False)
542 Simulation.setWorkCountOptions(system, options)
562 m5.switchCpus(system, switch_cpu_list)
573 m5.switchCpus(system, switch_cpu_list)