Lines Matching defs:system
93 # start with the system itself, using a multi-layer 2.0 GHz
96 system = System(membus = IOXBar(width = 32))
97 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
103 system.mem_ranges = [mem_range]
106 system.mmap_using_noreserve = True
114 MemConfig.config_mem(options, system)
118 if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
122 system.mem_ctrls[0].null = True
127 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
129 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
142 nbr_banks = system.mem_ctrls[0].banks_per_rank.value
145 burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
146 system.mem_ctrls[0].device_bus_width.value *
147 system.mem_ctrls[0].burst_length.value) / 8)
150 page_size = system.mem_ctrls[0].devices_per_rank.value * \
151 system.mem_ctrls[0].device_rowbuffer_size.value
155 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
165 system.tgen = PyTrafficGen()
168 system.monitor = CommMonitor()
171 system.tgen.port = system.monitor.slave
172 system.monitor.master = system.membus.slave
174 # connect the system port even if it is not used in this example
175 system.system_port = system.membus.slave
181 root = Root(full_system = False, system = system)
182 root.system.mem_mode = 'timing'
187 generator = dram_generators[options.mode](system.tgen)
196 yield system.tgen.createExit(0)
198 system.tgen.start(trace())