util: Build m5 with -no-pie flag


Added -no-pie flag to link /util/m5 to support newer versions of GCC
that enable PIE by default. Tested for backwards compatibility with GCC
4.3, which, only warns for the unrecognized flag.

Change-Id: I4b6df593936346b9d3e2fe29a5d85dde78b7cc5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17429
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: changed shebang on gem5img.py to python2.7

Change-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util, tlm: Fix a memory error in the SCMasterPort class.

In the b_transport method of the SCMasterPort class, there is a check
which determines whether the packet being sent to gem5 should be
deleted once the call to sendAtomic returns. This was deleting the
packet if extension was *not* nullptr.

This check should delete the packet if the extension *is* nullptr. The
reasoning is that the extension will equal nullptr if there was no
gem5 packet in an extension and a new one needed to be allocated. If
there was an extension, ie if extension is not nullptr, then that's
where the packet came from which therefore doesn't belong to us. In
that case, we need to leave it alone and let its owner clean it up.

With the check reversed, this method will either leak allocated packets
it should delete, or delete packets it shouldn't that someone else will
likely try to use later.

Change-Id: I61578d910be6e5085b9fc0ddaa82468b1ac68578
Reviewed-on: https://gem5-review.googlesource.com/c/16949
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Update the systemc example to use m5.systemc for sc_main.

Change-Id: I431d3f2c18964bac1a3f19eacfffd49cd6e50fa2
Reviewed-on: https://gem5-review.googlesource.com/c/16569
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

python: Replace orderdict with collections.OrderedDict

Python 2.7 and newer has support for ordered dictionaries in the
standard library. Remove this custom class.

Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16362
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

systemc: Allow specific functions to shadow the base class method

sc_in::bind and sc_core::sc_object::print shadow their respective base
class method. This change adds the necessary declarations to inform
the compiler that this is intentional.

Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15135
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Add the scons configuration cache to .gitignore for util/tlm.

Change-Id: Ife31e1bbf862d10bbe8e2c0fa36c8c168cfafa84
Reviewed-on: https://gem5-review.googlesource.com/c/14656
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Update the gem5-within-systemc README to mention USE_SYSTEMC.

When linking with an external systemc host, the native gem5 systemc API
should be disabled to avoid linking conflicts.

Change-Id: If7f9b3718fcdbdab5ebc9ef52e746f6bf9f2fb9c
Reviewed-on: https://gem5-review.googlesource.com/c/14520
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

systemc: Fix some paths in the tlm SCons(script|struct).

The code in util/systemc was moved into a subdirectory recently. The
scons support here referred to it, and needed to be updated.

Change-Id: Ib457d9bdafb2bba5058e6ecf99b9d33b3072c5b3
Reviewed-on: https://gem5-review.googlesource.com/c/13955
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: Add some examples for using systemc code within gem5.

These examples have comments inside them that explain what they do.
There's also a README file which explains how to use the examples
generally, and at a high level what each one does.

Change-Id: I223963dc1c190289986b2ee5705910dbcad4a4c9
Reviewed-on: https://gem5-review.googlesource.com/c/13376
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Move the existing systemc example into a subdirectory.

This example is for how to embed gem5 within systemc and make it use
the systemc event queue. This used to be the only method of using
gem5 and systemc together, but now that there are other options, it's
ambiguous to have it as the only thing in the util/systemc directory.

This change moves it into a gem5_within_systemc subdirectory which
clearly shows what type of integration that example corresponds with.

Change-Id: I426d68ccb618397d820bef492cbb1ff8ef4a979b
Reviewed-on: https://gem5-review.googlesource.com/c/13375
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Do not use $(PWD) in Makefiles

644e8cdf5ee7 ("util: Move the m5ops.h file to a shared directory")
added include/ to the include path for m5 Makefiles, based on
$(PWD): $(PWD)/../../include.

Unfortunately, this breaks when using `make -C <path>`, as -C does
not move PWD accordingly. The fix is simply to remove $(PWD), as a
relative path is just fine here.

Change-Id: Ia046c29761363b6670e52c52a604c7e70a6a305a
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Signed-off-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12844
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: add util/maint/show_changes_by_file.py tool

The script diffs an upstream branch and a feature branch to find
all files which have been changed between the branches. It then
searches for all the corresponding changesets and binds them to
the files in the output.

The tool's output resembles the following:

/path/to/file/
filename
git-hash
git-hash
filename
git-hash

/path/to/file/
filename
git-hash

Change-Id: Icd67953748f38dad984488c5445313eaa56fa202
Reviewed-on: https://gem5-review.googlesource.com/7861
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

tests,style: add RISC-V assembly tests

This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.

The tests have been slightly modified to work in gem5 SE mode:

(1) Removed a trap handler used in riscv-tests for bare-metal systems

(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
- '0' if SUCCESS
- Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.

In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.

(1) rv64uamt: multi-threaded tests for A-extension instructions

(2) rv64samt: multi-threaded tests for clone and futex system calls

This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.

Please find more details in the README file included in this patch.

Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

util,arch-arm: Update gen_arm_fs_files.py to use new kernel repos

Now it is using the kernels on https://gem5.googlesource.com/arm

Change-Id: I765f2b8ee48cfd7175e5b17a65db3bf612570c68
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/9481
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Implement Lua module for m5ops.

This module allows m5ops to be executed in Lua programs.
To compile it (in util/m5):
The following command generates Lua moduel, gem5OpLua.so.

make -f Makefile.<arch> gem5OpLua.so

To use it:
First, put gem5OpLua.so in Lua library search path.
Then, import the module and execute the m5op function.

Example usage, creating a checkpoint.

m5 = require("gem5OpLua")
m5.do_checkpoint(0, 0)

Change-Id: Icc18a1fb6c050afeb1cf4558fbdc724fb26a90e2
Reviewed-on: https://gem5-review.googlesource.com/6541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Implement PIC version of m5ops for X86.

Using m5ops for X86 in shared objects requires PIC for the m5ops.
Typically, the PIC version is used to make m5op interfaces to other
languages like python and lua.

Change-Id: I2463904c13ea8b839d0386d3c743d8dad1e1e6bc
Reviewed-on: https://gem5-review.googlesource.com/7261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: Add an option to specify paths in list_changes.py

Add an option to restrict change lists to changes that touch one or
more subdirectories in the source tree.

Change-Id: Id4e34fe300fdc3657505e2e188c727e583bcf611
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7461
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

util/m5: add Android.mk

Add Android.mk so we can build m5 tool in Android tree.

Change-Id: I7023130bd3ce5e015b8f7c41941eafb4611da8cb
Reviewed-on: https://gem5-review.googlesource.com/7363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Add the missing wakecpu m5op in X86.

Change-Id: I74876a4638ad37308ecdb0ef68513a968fac8787
Reviewed-on: https://gem5-review.googlesource.com/6501
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Add script to plot DRAM low power sweep

This change adds a script to generate graphs from the stats file
output by the configuration script low_power_sweep.py.

The graphs show stacked bars for time spent and energy consumed
wherein each component of the stacked bar represents a DRAM power
state (Idle, Refresh, Active, Active Power-down, Precharge Power-down
and Self-refresh). The script generates one plot per delay value. It
also generates a pdf (--pdf option) in which the graphs are laid out
such that you can easily compare how the increasing delay and other
swept params affect the resulting energy.

Change-Id: Id80b0947bfde27e11e5505b23a3adb30f793a43f
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5727
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Remove support for hg patches in patch creation script

Simplify the patch creation helper script by removing support for
automatic conversion to Mercurial's patch format. We no longer use
Mercurial as a primary repository, so this support is not likely to be
needed again.

Change-Id: I83f6efb9ccaee9c548b33257a4d6128153750c76
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5162
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Optionally search entire history when listing changes

The helper script to list changes currently only looks at the changes
between a branch point and two heads. This helps performance, but
sometimes misclassifies changes that exist both in the upstream
branch before the branch point and in a feature branch. Such changes
should normally not exist, but can be the product of an incorrect
rebase.

This change adds an option to the helper script to search the entire
upstream repo history when determining the set of upstream
changes. When this option is provided, the script lists the changes
that exist upstream before the branch point and in the feature branch
as "Incorrectly rebased changes".

Change-Id: I4cb72cea2152c49d0317dc43613be94a0a2de1e5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5161

util: Filter out the For-Upstream commit message tag

Some internal review flows, e.g. the flow used by ARM Research, uses
the For-Upstream tag to indicate that a change has been approved for
upstream. This tag isn't meaningful outside of the internal review
system. Remove it automatically when running the maintainer script to
prepare patches to be posted upstream.

Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5141
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Use a Makefile to ensure util/packet_pb2.py is up to date.

Rather than just ensuring that packet_pb2.py is available in general, use a
Makefile to ensure that it's also up to date in case packet.proto has
changed.

Also, remove a check that ensures that the protobuf module is available,
since python will complain if it needs it and can't find it.

Finally, remove a comment which talks about manually regenerating the
packet_pb2.py module, something that hasn't been necessary for a while, even
with the old version of this code.

Change-Id: I40c5c1f577e6d7ad1af9a209309a1eb92f073317
Reviewed-on: https://gem5-review.googlesource.com/5005
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: When building packet_pb2.py, don't assume a particular CWD.

Allow the script to be run from anywhere, and compute the paths relative to
where the script is. The script is assumed to be in util.

Change-Id: I8500ef959f2ff8119540c956f2b27789c96de60e
Reviewed-on: https://gem5-review.googlesource.com/5004
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Make decode_packet_trace.py print the new master ID fields.

Those fields are "repeated" which means they can appear zero times, which
they will in older style traces.

Change-Id: Ib6ff4aab521332cf1405549d0d6e922c51c12f32
Reviewed-on: https://gem5-review.googlesource.com/5003
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Small style fix in _EncodeVarint32.

Added spaces around the '|' operator.

Change-Id: I5cb82b98e7d2769605cde141f76a62a6e3c6570d
Reviewed-on: https://gem5-review.googlesource.com/5002
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Rename the (De|En)codeVarint function _(De|En)codeVarint32.

DecodeVarint implicitly truncates its inputs to 32 bits, and that should be
obvious from its name, and so not a surprise to the caller. EncodeVarint also
has the suffix added for consistency. Both functions are only used in
protolib.py, so add a _ to make it private (in the python sense) to the
module.

Change-Id: I835295717bb51672351b963fe1227ed619836f22
Reviewed-on: https://gem5-review.googlesource.com/5001
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Fix the indentation in DecodeVarint in util/protolib.py.

The DecodeVarint was, as a comment describes, lifted from
google.protobuf.internal.decoder. Unfortunately, the relative indentation of
some lines was changed, changing what scope they fell under. This changed the
behavior of the function, breaking it for multibyte and negative values.

This change restores the correct indentation and fixes the function's
behavior.

Change-Id: If645649506b0fe5a617b37a8202c9ca1c57aaf15
Reviewed-on: https://gem5-review.googlesource.com/5000
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tlm: Elastic Trace Example with L2 Cache Added

The SystemC TLM examples already include an example setup for elastic
traces. However, in the provided examples the L2 cache is omitted. This
patch provides an additionall example, which also includes an L2 cache
on the gem5 side.

Change-Id: I49e9fa074b60007694abff37663f0400caf72099
Reviewed-on: https://gem5-review.googlesource.com/4900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

misc: Make the m5 utilities writefile command accept a host path.

When the writefile command is given one command line argument, it's treated
as the name of the file in the simulation and on the host. When there are two
arguments, the first is the filename in the simulation, and the second is the
name on the host.

Change-Id: I402925a9ff89665bee9910fb18b7f8b06b8f7d35
Reviewed-on: https://gem5-review.googlesource.com/4850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

tlm: Don't set SystemC time resolution

Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.

Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Reviewed-on: https://gem5-review.googlesource.com/4520
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

style: Add shared gem5 headers to the style checker

Teach the style checker about common headers living in gem5/. These
should be included after any global library headers (e.g., C headers
or STL headers), but before the normal gem5 headers.

Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4300
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util: Move m5op.h to the shared include directory

The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory and factor out flags to a generic asm header. Note
that applications that need to call m5ops still need to link with
libm5.a or implement their own trampolines.

Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4265
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util, m5: Use consistent naming for m5op C symbols

Rename m5op C symbols to be prefixed all lower case, separated by
underscore, and prefixed by m5. This avoids potential name clashes for
short names such as arm.

Change-Id: Ic42f94d8a722661ef96c151d627e31eeb2e51490
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4264
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util: Move the m5ops.h file to a shared directory

The header file m5ops.h contains a list of constants that should be
shared between the simulator and utilities. Move this header file to a
new top-level directory for shared files and rename constants to make
them suitable for inclusion in the main simulator.

The structure of the shared include directory is as follows:

include/gem5: Files that can be included from C code.
include/gem5/asm: Files that can be included from assembly code.
asm/generic/: Files that aren't guest ISA specific
asm/${isa}/: Files that are guest ISA specific

Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

util,arch-arm: Added python script to generate ARM FS binaries

This python script builds the bootloaders, kernels and DTBs for the
VExpress_GEM5_V1 (aarch32/aarch64), VExpress_EMM and VExpress_EMM64
platforms (it checkouts some linux kernel repositories when needed).

This is the result of this e-mail thread in gem5-dev mailing list:
http://www.mail-archive.com/gem5-dev@gem5.org/msg22406.html

Change-Id: Ida8f9b974f7188f48be8f84f14828a1973d6d256
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/3945
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Fix building the m5tap utility.

Use printf instead of cprintf to avoid having to have .o files from gem5.
Stop disabling optimization. Placate the style checker by rearranging the
header include order. Include some missing standard headers. Switch from
the deprecated -I- gcc option to using -iquote. Make the "program"
variable a const char *. When checking the return value of getopt, don't
check against the char c which may mask the -1 return value. Instead,
store the return value in an int, and then later cast it to a char when
it's actually consumed.

Change-Id: Ibec51927d0cdbd98db8e53081be2c4931e20333c
Reviewed-on: https://gem5-review.googlesource.com/3600
Reviewed-by: Nathan Binkert <nate@binkert.org>
Maintainer: Nathan Binkert <nate@binkert.org>

misc: check address range in the SystemC example

Using a wrong offset or memory size may lead to segmentation faults.
This patch adds an address range check and produces an error message.

Change-Id: I79a72c05879266daf61a83367fe4ae386d1958a4
Reviewed-on: https://gem5-review.googlesource.com/3482
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>

misc: Reorder sources in util/tlm and rewrite build scripts

* Use one SConstruct to build everything instead of one SConstruct for
each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
ensures that SystemC does not need to be installed on the host and
avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes

Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: generate fully qualified paths for cscope

Change-Id: I318c185b117b9608110544526fbaaa3fdcdeb8bc
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

style: fix line lengths and include ordering

The style checker complains about line length and ordering for these
files. This fix should make these two files kosher.

Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d
Reviewed-on: https://gem5-review.googlesource.com/3380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

style: Treat PyBind headers as Python headers

Some PyBind11 headers need to include Python.h. This means that we need
to include PyBind11 headers before any standard library headers. Enforce
this by applying the Python.hh rules for anything in pybind11/.

Change-Id: Id175a4f613960a17f84f98b81bfd02806e905d5a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3120
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

util, arm: Support mmapped m5ops on aarch64

Add support for memory-mapped m5ops in the aarch64 version of the m5
utility. To enable support for memory-mapped m5ops, compile the tool
with the define M5OP_ADDR set to the base of the m5op PA range.

Change-Id: I13e21e48536b9849bf4081411b66b2f350f7a8ac
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2966

util: Correctly handle short writes in m5 (read|exec)file

The m5 tool has subcommands that writes a file to the simulated file
system. The implementation of this command currently doesn't check the
return value from write, which leads to compiler warnings and
potentially incorrect behavior. Add the necessary checks.

Change-Id: If558534d3245aa24cf15edf06bd0af4c6ba3908c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2962
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Add the m5_loadsymbol pseudo op to the m5 tool

Change-Id: Ib8bf4eac77170db8b2bf44796fd9d46b02217d03
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Fix incorrect use of m5_loadsymbol

It seems like the m5 utility incorrectly called m5_loadsymbol instead
of m5_addsymbol. Judging by the signature of the loadsymbol command,
the expected behavior is to add a new symbol to gem5's symbol
table. This is behavior is implemented by m5_addsymbol.

Change-Id: I83b61c48d6f8d7b1e8b57d884dfca00481c83c3a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2961
Reviewed-by: Gabe Black <gabeblack@google.com>

misc: fix build failure in cxx_config example

Fix a missing header in the cxx_config example which is used as a
simple example of using libgem5.so without python.

Change-Id: I758bfe42ba735ce0c7eaedd49b94a130e3bd21e3
Reviewed-on: https://gem5-review.googlesource.com/3000
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

util: Fix incorrect return type in m5 writefile

Change-Id: Ic24a1c3c1488e970ed27bb6b99262d201f535384
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2960
Reviewed-by: Gabe Black <gabeblack@google.com>

misc: minor fix for the gem5-SystemC/TLM coupling.

This patch has a minor fix for the coupling between gem5 and SystemC-TLM.

It also fixes some typos in the related documentation.

Change-Id: I894568729b8ebdacc5b81c9f46e8f9d137da210f
Reviewed-on: https://gem5-review.googlesource.com/2480
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handling

The aforementioned registers (Interrupt Processor Targets Registers) are
banked per-CPU, but are read-only. This patch eliminates the per-CPU
storage of these values that are simply computed.

Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2442
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>

util: Add a tool to list outgoing/incoming changes

Add a small Python script that uses Gerrit's Change-Id: tags to list
incoming and outgoing changes.

Change-Id: Iea1757b2d64a57a4c7b4e47718cfcaa725a99615
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2329
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim: allow forward dependencies in checkpoint upgraders

The notion of forward dependencies is just expressing the same
dependency but at the other end of the dependency edge, i.e. at
the dependee rather than the depender. As there is no more
'power' here, it's strictly a convenience feature for handling
dependencies with tags that are not in the upstream repository.

Change-Id: Ic7c68de6aff4094aaa12de62cdf690a5dc65ccb5
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

sim: add support for checkpoint downgrading

This commit supports the use case of transitioning tags and their
associated checkpoint rewrites out of use for whatever reason. Just
replace the upgrader() method with a downgrader() method that performs
the appropriate inverse operation.

The tag name is still used, but only in this negative, 'zombie' state,
as it will be removed from the tags in the checkpoint and gem5 binary.

Change-Id: If9d26cccfe8449e026762b1a72f0c2ae5a9cf2d7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Update the README

misc: Update #!env calls for python to explicit version

In some newer Linux distributions, env python default to Python 3.0. This
patch explicitly uses "python2" instead of just "python" for all scripts
that use #!

Reported-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Add callbacks for the Gem5SimControl that are called at before and
* after simulate()

Reviewed at http://reviews.gem5.org/r/3799/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Pay for the header delay that the gem5 XBar annotates to packets.

Reviewed at http://reviews.gem5.org/r/3798/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* bugfix: The BEGIN_RESP also needs to be handled when END_REQ was
* skipped
and '&trans == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.

Reviewed at http://reviews.gem5.org/r/3797/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Implement 'pipe through' for gem5 Packets (see explanation below)

Basically, this patch ensures that all transactions that originated in the
gem5 world are converted back to the original packet when entering the gem5
world. So far, this only worked for packets that are responded to by a
SyctemC component (e.g. when a gem5 CPU sends a request to a SystemC
memory). By implementing the 'pipe through' this patch ensures, that
packets that are responded to by a gem5 component (e.g. when a gem5 CPU
sends a request to a gem5 memory via a SystemC interconnect) are handled
properly.

Reviewed at http://reviews.gem5.org/r/3796/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.

Reviewed at http://reviews.gem5.org/r/3775/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Move common code of the example to a common directory. Move the cli
* parsing from the SimControl module to a separate example object. Add
* comments describing the Gem5SimControl module.

Testing Done: Examples compile and run.

Reviewed at http://reviews.gem5.org/r/3695/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Simplify the Slave Port by using a simple_initiator_socket.

Testing Done: Example applications are still running.

Reviewed at http://reviews.gem5.org/r/3686/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Add the Master Port. Add an example application that isslustrates its
* use.

Testing Done: A simple example application consisting of a TLM traffic
generator and a gem5 memory is part of the patch.

Reviewed at http://reviews.gem5.org/r/3528/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: fix includes in util/systemc

This fixes compilation errors with clang on OS X.

Reviewed at http://reviews.gem5.org/r/3807/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Implement the Base SystemC Module as an sc_channel.

Implementing the Module as an sc_channel allows derived classes to provide
SystemC interfaces. Other SystemC modules can connect to these interfaces.
This meachanism can be used to control gem5 and acces gem5 components from
within arbitrary SystemC moduels. Since sc_channel is derived from
sc_module, this patch does not break compatibility with existing code.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

style: Force Python.h to be included before main header

Python's header files set various compiler macros (e.g.,
_XOPEN_SOURCE) unconditionally. This triggers preprocessor warnings
that end up being treated as errors. The Python integration manual [1]
strongly recommends that Python.h is included before any system
header. The style guide used to mandate that Python.h is included
first in any file that needs it. This requirement was changed to
always include a source file's main header first, which ended up
triggering these errors.

This change updates the style checker to always include Python.h
before the main header file.

[1] https://docs.python.org/2/extending/extending.html

Change-Id: Id6a4f7fc64a336a8fd26691a0ca682abeb1d1579
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

misc: Add support for switching multiple cores in SystemC

This patch adds a '-n' flag to the gem5 SystemC driver which allows
multiple CPUs to be switched out to a new CPU. Primarily this involves
appending CPU numbers to the objects searched for in the config
manager if there are multiple CPUs in the system.

Note that an equivalent change should be made to the util/cxx_config driver,
but I wanted to get input on this first before making the same change over
there

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: fixes deprecated sc_time function for SystemC 2.3.1

The non-standard sc_time constructors

- sc_time( uint64, bool scale )
- sc_time( double, bool scale )

have been deprecated in SystemC 2.3.1 and a warning is issued when being
used. Insted the new 'sc_time::from_value' function is used to omit the
warning message.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

misc: Documentation Update

Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm.
Some minor corrections, mostly with respect to MAC/OSX

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

util: Add maintainer tools to create upstream patches

This changeset adds a maintainer script, create_patches.sh, that can
be used to prepare for upstream from a git repository. The script can
be used to generate patches in Mercurial or git format. The commit
messages in the exported patches are all filtered, see
upstream_msg_filter.sed, to ensure that irrelevant meta data isn't
included in the upstream commit.

Kudos to Curtis Dunham and Nikos Nikoleris for reviews and usability
enhancements for earlier versions of this patch.

Change-Id: Ia4cd089a32834b5e046ef58c0a173ca285b77bca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

dist, dev: fix etherswitch upgrade script

The aforementioned upgrader in [1] assumes every option in [system]
has a delimiting '.', and also seems to do its rewriting work a bit too
unconditionally. Most checkpoints in the wild don't have this device,
in which case this script should be a safe no-op.

[1] 2aa4d7b dist, dev: Fixed the packet ordering in etherswitch

Change-Id: Icfd0350985109df1628eb9ab864cda42c54060a8
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>

arm: update AArch{64,32} register mappings

Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

style: Add options to select checkers and apply fixes

Add an option, --checker/-c, to style.py that selects individual style
checkers to apply. When this option isn't specified, the script
defaults to all available style checkers. The option may be specified
multiple times to run multiple style checkers.

The option, --fix/-f, can be specified to automatically fix style
violations.

Change-Id: Id7597fba6b65cecfa17a88b1c87c8a4c8315af59
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>

util: git pre-commit hook to check staged files

This patch updates the git-pre-commit hook to check the files as they
will be after the commit, instead of as they are currently, this way we
prevent the undesired situation:
- unstylish modification of a file
- stage said file for commit
- try to commit and fail due to style
- fix style, forgetting staging changes
- try to commit and fail, as although the changes staged are not
styly, the current content of the file is.

Change-Id: I5cc3f783375d9e4162e310e176103ebbf0a59023
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[andreas.sandberg@arm.com: Rebased ontop of latest gem5]

tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)

This patch avoids compiling ALPHA six times as part of running
'util/regress', and instead relis on NULL with different protocols to
run the rubytest. All we need is the memory system, so there is really
no need to compile the ISA over and over again.

The one downside is the removal of running 'hello' for the variuos
ALPHA and protocol combinations, but if this is a concern we should
rather beef up the synthetic tests for the variuos protocols.

dev: Add m5 op to toggle synchronization for dist-gem5.
This patch adds the ability for an application to request dist-gem5 to begin/
end synchronization using an m5 op. When toggling on sync, all nodes agree
on the next sync point based on the maximum of all nodes' ticks. CPUs are
suspended until the sync point to avoid sending network messages until sync has
been enabled. Toggling off sync acts like a global execution barrier, where
all CPUs are disabled until every node reaches the toggle off point. This
avoids tricky situations such as one node hitting a toggle off followed by a
toggle on before the other nodes hit the first toggle off.

arm: Fix for ARM's Streamline conversion script

tracked down issue with ARM's version of gem5 using the "cluster" name.
The public/github version of ARM Gem5 does not use the "cluster" naming
mechanism.

Signed-off-by: Dam Sunwoo <dam.sunwoo@arm.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

style: Make the style fixers safe

Adds a wrapper to the fix functions of the verifiers. This wrapper first
copies the original file to a backup file, then performs the fix. If an
error occurs, the backup file is used to restore the original file.

Also fixed a line-length error in verifiers.py

arm: bank GIC registers per CPU

Updated according to GICv2 documentation.

Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3

misc: SystemC Elastic Trace Player Example.

This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.

Committed by Jason Lowe-Power <jason@lowepower.com>

misc: fix a compile error due to incompability with SystemC 2.3.1

This patch fixes an ambigous call compile error

Committed by Jason Lowe-Power <jason@lowepower.com>

misc: Separate stats file for SystemC-gem5 co-simulation

In previous versions of systemC-gem5 coupling statistics were not updated
for the systemc-gem5 simulation. systemC-gem5 simulation only need the
previously built config.ini file and normal gem5 simulation has to be run
once to generate config.ini file. Thus stats.txt inside the m5out folder is
redundant for systemC-gem5 simulation. A new stats file is now generated
with the all the statistics for systemC-gem5 simulation. This will also
resolve the stats issue in tlm-sysmtemC simulation.

Committed by Jason Lowe-Power <jason@lowepower.com>

style: Fix incorrect references style verifiers

The style checker for spacing around control statements (ControlSpace)
and the whitespace checker (Whitespace) didn't refer to some of their
configuration variables correctly. This changeset fixes those issues.

Reported-by: Jason Lowe-Power <power.jg@gmail.com>

style: catch trailing white spaces in make and dts files

Change-Id: I2a4f1893919660e51599902b972a6f3f5717e305
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

dist, dev: Fixed the packet ordering in etherswitch

This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>

style: remove extra newline from white space verifier fix method

Change-Id: I7bce7d1cb04efe20d31445eb67ea5ffd2a4a41f4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: respect per verifier ignores for git commit

Change-Id: Id00379bdb17594e627ee49c077fb75f499ea550e
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: Move the last bits of file_types.py to the style package

The commit that refactored the style checkers into a new Python
package (style: Refactor the style checker as a Python package)
accidentally left a fragment of file_types.py in the old location
(util/style.py). This was caused by a race between the commit that
moved the file and Nate's commit that added a copyright header to the
file.

This commit moves the last fragment (the copyright header) and removes
the old file.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: ignore test data in style checks

Change-Id: If797eaf3842b5c1604942bb60f091800ee814a2a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: respect ignores for git commit

Previously it ignored the ignores for git but not Mercurial.

Change-Id: I178fe879ebd268e863063eb9e30ec87e8ac8faec
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: improve compatibility with old git versions

Older versions of git need the '=' to connect --diff-filter to
its argument.

Change-Id: Ic62057567db061684be88a7c2d80a6a5d4c11dcf

style: Don't include diff context in git style hook

The git style hook currently includes a few lines of diff context when
determining changed regions. This is undesirable as this triggers
false positives when modifying existing files with a lot of style
violations. This change sets the amount of context to 0, which is the
default value when requesting staged regions from the git helper.

Change-Id: Ibe03123e329ea0241281e104183a68d6c495b190
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>

style: Fix Python 2.6 compatibility

The style checker code needs to disable autojunk when diffing source
files using Python's difflib. Support for this was only introduced in
Python 2.7, which leads to a TypeError exception on older Python
version. This changeset adds a fallback mechanism for old Python
versions.

misc: Bugfix in TLM memInhibit Command

memInhibitAsserted() has been removed from packet.hh. This change has been
reflected in TLM based SystemC memory.
This patch also adds a number of panics asserting the SystemC memory only
sees requests it expects.

Committed by Jason Lowe-Power <power.jg@gmail.com>

dist: config file for distributed switch

Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.

mem: Add Program Counter to MemTraceProbe

arm: Clean up m5ops assembly library

The m5ops assembly library contains a lot of repetitive code. This
changeset adds two macros, FOREACH_M5OP and FOREACH_M5_ANNOTATION, to
m5ops.h that simplify architecture-specific implementations. The ARM
and ARMv8 m5op implementations have been updated to use the new
macros.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

style: Change maximum line length to 79 characters

The old style guide used to mandate 78 characters as the maximum line
length to accommodate traditional diffs on 80-column terminals. This
is an uncommon use case and it has therefore been decided (see email
thread on gem5-dev [1]) that a maximum length of 79-characters makes
more sense.

[1] http://comments.gmane.org/gmane.comp.emulators.m5.devel/29789

Signed-off-by: Andreas Sandberg <aandreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>

style: Add a style checker that doesn't depend on Mercurial

The current style checker script, hgstyle.py, assumes that it is being
run from Mercurial. This means that it depends on the Mercurial Python
libraries, which aren't necessarily present if using git. This
changeset adds a new style checker script, style.py, that has
been designed to be run from the command line.

The script has support for detecting which revision control system is
used and is able to query both git and Mercurial for changes. This
enables the script to operate on modified regions and/or all of the
modified files in the repository.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

scons: Automatically install the git style hook

Add a check in the main SConscript that installs the git pre-commit
hook in util/ if git is used.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
[andreas.sandberg@arm.com: Cleanups suggested by Steve]
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

style: Add a git pre-commit hook

Add a git pre-commit hook that verifies that files that are about to
be committed. Since git stages changes into an index and the index
contains the changes that will be committed, the style checker only
looks at the state of files in the index.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

style: Add repository helper functions

Add an AbstractRepo class and implementations for git and Mercurial
that provide a common interface to query repository status for style
checkers. The class defines the interfaces to list modified files that
are about to be committed and methods to identify changed regions.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

style: Remove style validators

Style validators provide a subset of the style verifier functionality
and are only exposed through the "hg m5format" command. This
functionality seems to be both redundant and unused.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

style: Add a control character checker

Add a style checker that verifies that source code doesn't contain
non-printable (control) characters. The only allowed control
characters are:

* 0x0a / \n: New line
* 0x09 / \t: Tab (the whitespace checker enforces no-tabs for C/C++ files)

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>

style: Refactor the style checker as a Python package

Refactor the style checker into a Python module that can be reused by
command line tools that integrate with git. In particular:

* Create a style package in util
* Move style validators from style.py to the style/validators.py.
* Move style verifiers from style.py to the style/verifiers.py.
* Move utility functions (sort_includes, region handling,
file_types) into the style package
* Move generic code from style.py to style/style.py.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

style: Change include sorter to yield one line at a time

The include sorter class normally yields one string per line and
relies on the caller to merge lines into a block of text separated by
newlines. However, there are cases when this isn't true. This makes
diffing using Python's difflib hard. This changeset updates the
include sorter to never do this and always yield one line at a time.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

scons, style: Rename style.py to hgstyle.py

The Mercurial style checker extensions are currently stored in
style.py. This is not ideal since they won't work with other version
control systems. This changeset renames style.py to hgstyle.py and
adds upgrade code to scons that automatically updates the hooks in
hgrc.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>

style: Remove unsupported style.py commands

Remove the unsupported style.py subcommands (fixwhite, chkwhite),
which leaves the chkformat command as the only remaining
command. Since the script now only supports one command, remove the
sub-command support altogether.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>

copyright: Update copyright in sort_includes.py

The following changes introduced substantial changes to sort_includes.py:
- hg:84b4d6af0ecc - util: Fix state leakage in ...
- hg:e2f9644a7738 - style: Update the style checker to handle new ...

Since the file didn't include a copyright header at the time, I never
added the correct ARM copyright notice. This changeset adds the
correct copyright notice.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

copyright: add copyright missing from files I created

style: Strip newline when checking lines

The style checker incorrectly includes newlines when checking lines of
code, which effectively decreases the column limit by 1. This
changeset strips the newline character from before calling line
checkers.

Change-Id: I0a8c7707ece57d782d11cc86db4b8064db291ce0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Fix argument handling for m5 initparam util

configs: Add a lat_mem_rd style test script

This patch adds a config script that broadly replicates the behaviour
of lat_mem_rd. The test is based on traffic generators, and as such we
simply randomise addresses in increasingly large ranges, and play them
back using the trace functionality of the traffic generator.

The test script is accompanied by a post-processing and visualisation
script. At the moment no configurability is added to tweak the memory
hierarchy, but a follow on patch could easily extend the
functionality.

util: update Java JNI interface to m5ops

Synchronize with
ab19693da "pseudo inst,util: Add optional key to initparam pseudo instruction"

cpu: TraceGen fix for tick frequency check

Bug fix for check on protobuf file frequency being different than
global frequency.

The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.

util: fix apparent statetrace bug

In the process of trying to eliminate boolean comparisons,
I ran across this statement that appears to be a bug
(should have been an assignment).

util: added line length and boolean comparison style checkers

Added checkers for line length and boolean comparisons
(== true/== false) to the style script.

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

util: clean up and extend style checker

Added a new Verifier object to check for and fix spacing
between if/while/for and following paren.

Restructured Verifier class to make it easier to add
new subclasses, particularly by using a global list of
verifiers to auto-generate command line options and
simplify the invocation loop.

util: delete old unused style-checking scripts

The functions in these scripts were apparently folded into style.py but the
old scripts were orphaned without being deleted. Get rid of them so their
existence is no longer confusing.

gpu-compute: AMD's baseline GPU model

config: Updates for distributed gem5 simulations

dev: Distributed Ethernet link for distributed gem5 simulations

Distributed gem5 (abbreviated dist-gem5) is the result of the
convergence effort between multi-gem5 and pd-gem5 (from Univ. of
Wisconsin). It relies on the base multi-gem5 infrastructure for packet
forwarding, synchronisation and checkpointing but combines those with
the elaborated network switch model from pd-gem5.

pseudo inst,util: Add optional key to initparam pseudo instruction

The key parameter can be used to read out various config parameters from
within the simulated software.

dev, arm: Add gem5 extensions to support more than 8 cores

Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.

When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.

This changeset is based on previous work by Matt Evans.

cpu: Support virtual addr in elastic traces

This patch adds support to optionally capture the virtual address and asid
for load/store instructions in the elastic traces. If they are present in
the traces, Trace CPU will set those fields of the request during replay.

cpu: Create record type enum for elastic traces

This patch replaces the booleans that specified the elastic trace record
type with an enum type. The source of change is the proto message for
elastic trace where the enum is introduced. The struct definitions in the
elastic trace probe listener as well as the Trace CPU replace the boleans
with the proto message enum.

The patch does not impact functionality, but traces are not compatible with
previous version. This is preparation for adding new types of records in
subsequent patches.

util: Add decode and encode scripts for elastic traces

This patch adds python scripts to parse a protobuf encoded O3CPU
elastic trace and convert it to a text file output and vice versa.

util: term: drop CC from Makefile

With clang there are systems without gcc being installed anymore and we should
not rely on that. This patch drops CC so that system's default compiler is
invoked.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

util: DrainManager/Checkpoint changes in SystemC coupling

Due to changes in Drain Manager, the lastest systemc coupling doesn't work. The
code for handling Checkpoint has been modified and it is now compatiable with
new drain manager.

Testing is being done on systemC coupling. It needs more testing to verify
checkpointing feature.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

sim: Update C++ config example to match SystemC example

Update the use of the drain manager, and checkpointing to
match changes to gem5 since the example was written.

config: Minor fixes to the DRAM utilisation sweep

base: remove Trace::enabled flag

The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.

isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.

util: Fix minor issues in DRAM sweep scripts

This patch fixes a few issues in the sweep scripts, bringing them
up-to-date with the latest memory configs and options.

misc: Bugfix for Freezing Terminal in SystemC Simulation

If the terminal was used in the SystemC or TLM simulations the simulation gets
in a deadlock state. This is because of the Event queue gets locked while
servicing the async events leading to event queue deadlock. This was solved by
locking the queue at the beginning of service of async events.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

misc: Bugfix in TLM integration regarding CleanEvict Command
The CleanEvict command was not considered in /util/tlm/sc_port.cc this could
lead to a simulator crash. This issue is solved by ignoring this special
command type.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

dev, arm: Rewrite the HDLCD controller

Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:

* Broken/missing interrupt support (VSync, underrun, DMA end)
* Fragile resolution changes (changing resolutions used
to cause assertion errors).
* Support for resolutions with a width that isn't divisible by 32.
* The pixel clock can now be set dynamically.

This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).

sim: tag-based checkpoint versioning

This commit addresses gem5 checkpoints' linear versioning bottleneck.
Since development is distributed across many private trees, there exists
a sort of 'race' for checkpoint version numbers: internally a checkpoint
version may be used but then resynchronizing with the external tree causes
a conflict on that version. This change replaces the linear version number
with a set of unique strings called tags. Now the only conflicts that can
arise are of tag names, where collisions are much easier to avoid.

The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version
representation, as one would expect. Each tag version implements its
upgrader code in a python file in the util/cpt_upgraders directory
rather than adding a function to the upgrader script itself.

The version tags are stored in the 'Globals' section rather than 'root'
(as the version was previously) because 'Globals' gets unserialized
first and can provide a warning before any other unserialization errors
can occur.

util: Enable DRAM sweep to print power and efficiency

This patch enhances the functionality of the DRAM sweep script to not
only plot the bandwidth utilisation, but also total power and power
efficiency. To do so, a command-line switch is added, and a bit more
data extracted from the stats.

misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.

Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension. For event
handling single events are now created.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

util: added .cl OpenCL extension to file_type.py

util: added .mk makefile extension to file_types.py

util: add a vimrc that matches gem5 style guide

base: refactor process class (specifically FdMap and friends)

This patch extends the previous patch's alterations around fd_map. It cleans
up some of the uglier code in the process file and replaces it with a more
concise C++11 version. As part of the changes, the FdMap class is pulled out
of the Process class and receives its own file.

dev: add support for multi gem5 runs

Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).

The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.

There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.

A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.

Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).

util: Remove DRAMPower trace script

This script is deprecated and DRAMPower is now properly integrated
with the controller model.

sim, arm: add checkpoint upgrader for d02b45a5

The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
obsoletes old checkpoints.

config: Add soak test for memtest.py

This patch adds a random option to memtest.py which allows the user to
easily test valid random tree topologies. The patch also adds a
wrapper script to run soak tests using the newly introduced option.

We also adjust the progress interval and progress limit check to make
the output less noisy, and avoid false positives.

Bring on the pain.

cpu: add support for outputing a protobuf formatted CPU trace

Doesn't support x86 due to static instruction representation.

style: Fix broken m5format command

The m5format command didn't actually work due to parameter handling
issues and missing language detection. This changeset fixes those
issues and cleans up some of the code to shared between the style
checker and the format checker.

style: Fix incorrect style checker option name

The style used to support the option -w to automatically fix white
space issues. However, this option was actually wired up to fix all
styles issues the checker encountered. This changeset cleans up the
code that handles automatic fixing and adds an option to fix all
issues, and separate options for white spaces and include ordering.

style: Update the style checker to handle new include order

As of August 2014, the gem5 style guide mandates that a source file's
primary header is included first in that source file. This helps to
ensure that the header file does not depend on include file ordering
and avoids surprises down the road when someone tries to reuse code.

In the new order, include files are grouped into the following blocks:
* Primary header file (e.g., foo.hh for foo.cc)
* Python headers
* C system/stdlib includes
* C++ stdlib includes
* Include files in the gem5 source tree

Just like before, include files within a block are required to be
sorted in alphabetical order.

This changeset updates the style checker to enforce the new order.

config: Fix to SystemC example's event handling

This patch fixes checkpoint restore in the SystemC hosting example by handling
early PollEvent events correctly before any EventQueue events are posted.

The SystemC event queue handler (SCEventQueue) reports an error if the event
loop is entered with no Events posted. It is possible for this to happen
after instantiate due to PollEvent events. This patch separates out
`external' events into a different handler in sc_module.cc to prevent the
error from occurring.

This fix also improves the event handling of asynchronous events by:

1) Making asynchronous events 'catch up' gem5 time to SystemC
time to avoid the appearance that events have been lost
while servicing an asynchronous event that schedules an
event loop exit event

2) Add an in_simulate data member to Module to allow the event
loop to check whether events should be processed or deferred
until the next time Module::simulate is entered

3) Cancel pending events around the entry/exit of the event loop
in Module::simulate

4) Moving the state initialisation of the example entirely into
run to correct a problem with early events in checkpoint
restore.

It is still possible to schedule asynchronous events (and talk PollQueue
actions) while simulate is not running. This behaviour may stil cause
some problems.

config: SystemC Gem5Control top level additions

This patch cleans up a few style issues and adds a few capabilities to the
SystemC top level 'Gem5Control/Gem5System' mechanism. These include:

1) A space to store/retrieve a version string for a model
2) A mechanism for registering functions to be called at the end of
elaboration to perform simulation setup tasks in SystemC
3) Adding setGDBRemotePort to the Gem5Control
4) Changing the sc_set_time_resolution behaviour to instead check that
the SystemC time resolution is already acceptable

kvm, x86: Adding support for SE mode execution
This patch adds methods in KvmCPU model to handle KVM exits caused by syscall
instructions and page faults. These types of exits will be encountered if
KvmCPU is run in SE mode.

config: Fix checkpoint restore in C++ config example

This patch fixes the checkpoint restore option in the example of C++
configuration (util/cxx_config).

The fix introduces a call to config_manager->startup() (which calls startup
on all SimObjects managed by that manager) to replicate the loop of
SimObject::startup calls in src/python/m5/simulate.py::simulate guarded by
need_startup. As util/cxx_config/main.cc is a C++ analogue of
src/python/mt/simulate.py, it should make a similar set of calls.

sim: SystemC hosting

This patch hosts gem5 onto SystemC scheduler. There's already an upstream
review board patch that does something similar but this patch ...:

1) is less obtrusive to the existing gem5 code organisation. It's divided
into the 'generic' preparatory patches (already submitted) and this patch
which affects no existing files

2) does not try to exactly track the gem5 event queue with notifys into
SystemC and so doesn't requive the event queue to be modified for
anything other than 'out of event queue' scheduling events

3) supports debug logging with SC_REPORT

The patch consists of the files:
util/systemc/
sc_gem5_control.{cc,hh} -- top level objects to use to
instantiate gem5 Systems within
larger SystemC test harnesses as
sc_module objects
sc_logger.{cc,hh} -- logging support
sc_module.{cc,hh} -- a separated event loop specific to
SystemC
stats.{cc,hh} -- example Stats handling for the sample
top level
main.{cc,hh} -- a sample top level

On the downside this patch is only currently functional with C++
configuration at the top level.

The above sc_... files are indended to be compiled alongside gem5 (as a
library, see main.cc for a command line and util/systemc/README for
more details.)

The top-level system instantiation in sc_gem5_control.{cc,hh} provides
two classes: Gem5Control and Gem5System

Gem5Control is a simulation control class (from which a singleton
object should be created) derived from Gem5SystemC::Module which
carries the top level simulation control interface for gem5. This
includes hosting a system-building configuration file and
instantiating the Root object from that file.

Gem5System is a base class for instantiating renamed gem5 Systems
from the config file hosted by the Gem5Control object. In use, a
SystemC module class should be made which represents the desired,
instantiable gem5 System. That class's instances should create
a Gem5System during their construction, set the parameters of that
system and then call instantiate to build that system. If this
is all carried out in the sc_core::sc_module-derived classes
constructor, the System's external ports will become children of
that module and can then be recovered by name using sc_core::
sc_find_object.

It is intended that this interface is used with dlopen. To that
end, the header file sc_gem5_control.hh includes no other header
files from gem5 (and so can be easily copied into another project).
The classes Gem5System and Gem5Control have all their member
functions declared `virtual' so that those functions can be called
through the vtable acquired by building the top level Gem5Control
using dlsym(..., "makeGem5Control") and `makeSystem' on the
Gem5Control.

config: Add the ability to read a config file using C++ and Python

This patch adds the ability to load in config.ini files generated from
gem5 into another instance of gem5 built without Python configuration
support. The intended use case is for configuring gem5 when it is a
library embedded in another simulation system.

A parallel config file reader is also provided purely in Python to
demonstrate the approach taken and to provided similar functionality
for as-yet-unknown use models. The Python configuration file reader
can read both .ini and .json files.

C++ configuration file reading:

A command line option has been added for scons to enable C++ configuration
file reading: --with-cxx-config

There is an example in util/cxx_config that shows C++ configuration in action.
util/cxx_config/README explains how to build the example.

Configuration is achieved by the object CxxConfigManager. It handles
reading object descriptions from a CxxConfigFileBase object which
wraps a config file reader. The wrapper class CxxIniFile is provided
which wraps an IniFile for reading .ini files. Reading .json files
from C++ would be possible with a similar wrapper and a JSON parser.

After reading object descriptions, CxxConfigManager creates
SimObjectParam-derived objects from the classes in the (generated with this
patch) directory build/ARCH/cxx_config

CxxConfigManager can then build SimObjects from those SimObjectParams (in an
order dictated by the SimObject-value parameters on other objects) and bind
ports of the produced SimObjects.

A minimal set of instantiate-replacing member functions are provided by
CxxConfigManager and few of the member functions of SimObject (such as drain)
are extended onto CxxConfigManager.

Python configuration file reading (configs/example/read_config.py):

A Python version of the reader is also supplied with a similar interface to
CxxConfigFileBase (In Python: ConfigFile) to config file readers.

The Python config file reading will handle both .ini and .json files.

The object construction strategy is slightly different in Python from the C++
reader as you need to avoid objects prematurely becoming the children of other
objects when setting parameters.

Port binding also needs to be strictly in the same port-index order as the
original instantiation.

util: adds a script for using DSENT
This patch adds a python script that processes the configuration and the
statistics file from a simulation run. Configuration and activity of network
routers and links obtained from this processing is fed to DSENT via its Python
interface. DSENT then computes the area and the power consumption of these
network components. The script outputs these quantities to the console.

config: Update Streamline scripts and configs

Updated the stat_config.ini files to reflect new structure.

Moved to a more generic stat naming scheme that can easily handle
multiple CPUs and L2s by letting the script replace pre-defined #
symbols to CPU or L2 ids.

Removed the previous per_switch_cpus sections. Still can be used by
spelling out the stat names if necessary. (Resuming from checkpoints
no longer use switch_cpus. Only fast-forwarding does.)

arm: use condition code registers for ARM ISA

Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.

mem: Add utility script to plot DRAM efficiency sweep

This patch adds basic functionality to quickly visualise the output
from the DRAM efficiency script. There are some unfortunate hacks
needed to communicate the needed information from one script to the
other, and we fall back on (ab)using the simout to do this.

As part of this patch we also trim the efficiency sweep to stop at 512
bytes as this should be sufficient for all forseeable DRAMs.

style: Add support for a style ignore list and ignore ext/

There are some directories within the repository where we don't want
to enforce our coding style. Specifically, we don't want the style
hooks to warn whenever we update external code in the ext/ directory.

style: Fixup strange semantics in hg m5style

The 'hg m5style' command had some rather strange semantics. When
called without arguments, it applied the style checker to all added
files and modified regions of modified files. However, when providing
a list of files, it used that list as an ignore list instead of
specifically checking those files.

This patch makes the m5style command behave more like other Mercurial
commands where the arguments are used to specify which files to work
on instead of which files to ignore.

sim: bump checkpoint version for multiple event queues

This patch adds a fix for older checkpoints before support for
multiple event queues were added in changeset 2cce74fe359e. The change
in checkpoint version should really hav ebeen part of the
aforementioned changeset.

util: Fix state leakage in the SortIncludes style verifier

There are cases where the state of a SortIncludes object gets messed
up and leaks between invocations/files. This typically happens when a
file ends with an include block (dump_block() gets called at the end
of __call__). In this case, the state of the class is not reset
between files. This bug manifests itself as ghost includes that leak
between files when applying the style hooks.

This changeset adds a reset at the beginning of the __call__ method
which ensures that the class is always in a clean state when
processing a new file.

util: Move packet trace file read to protolib

This patch moves the code for opening an input protobuf packet trace into
a function defined in the protobuf library. This is because the code is
commonly used in decode scripts and is independent of the src protobuf
message.

cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036

util: Add DVFS perfLevel to checkpoint upgrade script

This patch updates the checkpoint upgrader script. It adds the _perfLevel
variable in the clock domain and voltage domain simObjects used for DVFS.

mem: DRAMPower trace formatting script

This patch adds a first version of a script that processes the debug
output and generates a command trace for DRAMPower. This is work in
progress and is intended as a snapshot of ongoing work at this point.

The longer term plan is to link in DRAMPower as a library and have one
instance of the model per rank, and instantiate it based on a struct
passed from gem5. Each command will then be a call to the model and no
parsing of traces will be necessary.

Util: Do not style check symlinks

The style checker used to traverse symlinks if they pointed to files, which can
result in style checker failure if the pointed-to file doesn't exist. This
style check is actually unnecessary, since symlinks either point to other files
that are already style checked, or files outside gem5, which shouldn't be
checked. Skip symlinks.

arm: Add Makefile for aarch64 build of util/m5

util: Valgrind suppression addition

Adds a suppression rule to util/valgrind-suppressions due to a minor bug
present in zlib that has no impact on simulation.

ruby: recorder: Fix (de-)serializing with different cache block-sizes

Upon aggregating records, serialize system's cache-block size, as the
cache-block size can be different when restoring from a checkpoint. This way,
we can correctly read all records when restoring from a checkpoints, even if
the cache-block size is different.

Note, that it is only possible to restore from a checkpoint if the
desired cache-block size is smaller or equal to the cache-block size
when the checkpoint was taken; we can split one larger request into
multiple small ones, but it is not reliable to do the opposite.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

arm: fix typos in makefile for ARM m5 util and link statically

1) fixes a typo for clean target libgemOpJni.so -> libgem5OpJni.so
2) addes jni_gem5Op.h to clean since it is added during make
3) links the m5 utility statically since it won't work on some images otherwise

util: Add support for detection of gzipped packet traces

This patch adds support for automatically detecting a gzipped packet
trace, thus accepting either a compressed or uncompressed trace.

mem: Edit proto Packet and enhance the python script

This patch changes the decode script to output the optional fields of
the proto message Packet, namely id and flags. The flags field is set
by the communication monitor.

The id field is useful for CPU trace experiments, e.g. linking the
fetch side to decode side. It had to be renamed because it clashes
with a built in python function id() for getting the "identity" of an
object.

This patch also takes a few common function definitions out from the
multiple scripts and adds them to a protolib python module.

util: Enhance the error messages for packet encode/decode

This patch adds a more verbose error message when the Python protobuf
module cannot be loaded.

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

util: updated Streamline flow to support ARM DS-5 v5.17 protocol

The previous flow supported ARM DS-5 v5.13 protocol.

ruby: rename MESI_CMP_directory to MESI_Two_Level

This is because the next patch introduces a three level hierarchy.

util: update checkpoint aggregation script
The checkpoint aggregation script had become outdated due to numerous changes
to checkpoints over the past couple of years. This updates the script. It
now supports aggregation for x86 architecture instead of alpha. Also a couple
of new options have been added that specify the size of the memory file to be
created and whether or not the memory file should be compressed.

ARM: add support for TEEHBR access

Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier
in arch/arm/kernel/thumbee.c. The Linux kernel code just seems
to be saving and restoring the register. This patch adds support
for the TEEHBR cp14 register. Note, this may be a special case
when restoring from an image that was run on a system that
supports ThumbEE.

dev: Fix race conditions in IDE device on newer kernels

Newer linux kernels and distros exercise more functionality in the IDE device
than previously, exposing 2 races. The first race is the handling of aborted
DMA commands would immediately report the device is ready back to the kernel
and cause already in flight commands to assert the simulator when they returned
and discovered an inconsitent device state. The second race was due to the
Status register not being handled correctly, the interrupt status bit would get
stuck at 1 and the driver eventually views this as a bad state and logs the
condition to the terminal. This patch fixes these two conditions by making the
device handle aborted commands gracefully and properly handles clearing the
interrupt status bit in the Status register.

arm: fix m5ops binary for ARM and add m5fail.

Changes to make m5ops work under virtualization seemed to break them working
with non-virtualized systems and the recently added m5 fail command makes
the m5op binary not compile. For now remove the code for virtualization.