sim-se, tests: add a new sim-se test

This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).

After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.

Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.

Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Rewrite Makefiles for pthreads test

The Makefiles for the pthreads test don't behave like typical
Makefiles that support cross compilation. Rewrite the Makefile to make
cross-compilation more convenient and add targets for aarch{32,64}.

Change-Id: I7cae378492681744b6bb11dd5af69db81ec54229
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests: add a stack printer test

Add a test to print out stack contents for SE mode programs.
The test will print out argc, argv, envp, and some auxiliary
vectors.

Change-Id: I489d752ee40fde24c531d8918d0c050f4df936c5
Reviewed-on: https://gem5-review.googlesource.com/3440
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

tests: Add Makefiles for hello

This adds Makefiles for hello for ARM and x86 by leveraging docker and
dockcross. See https://github.com/dockcross/dockcross for more
information.

These Makefiles also allow for automatic uploading to the correct location
for users to download when running the new tests.

Change-Id: I7085000393cd5283502a7af362c85befda749181
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4883

tests: Fix hello.c test program

Update the hello test to have a sane return code.

Change-Id: I9576b71ee995d8aa410c4ed19d44cc4e9fad10ee
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests,style: add RISC-V assembly tests

This patch adds a subset (rv64*) of RISC-V assembly tests. The original
riscv-test project can be found here:
https://github.com/riscv/riscv-tests. The riscv-test project is under the
BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE)
and is maintained separately from gem5 project.

The tests have been slightly modified to work in gem5 SE mode:

(1) Removed a trap handler used in riscv-tests for bare-metal systems

(2) Instead of throwing an exception, the tests call the exit syscall
with
the exit code of
- '0' if SUCCESS
- Failed test case's number (non-zero) if FAILURE
The exit code can be captured after a simuation completes.

In addition to original RISC-V assembly tests, this patch adds several
assembly tests specifically for AMO, LR, SC and system calls. Those
tests target a multi-core system.

(1) rv64uamt: multi-threaded tests for A-extension instructions

(2) rv64samt: multi-threaded tests for clone and futex system calls

This patch also makes the style checker ignore RISC-V assembly test
directory. The assembly tests are maintained in an external project
that does not follow the gem5 coding conventions.

Please find more details in the README file included in this patch.

Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0
Reviewed-on: https://gem5-review.googlesource.com/6703
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

tests: Add test program for C++ threads

Simple program that spawns threads equal to the number of CPU cores and
has some false sharing for testing coherence protocols.

Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8901
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

arch-riscv: Make use of ImmOp's polymorphism

This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.

Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

tests: Upate RISC-V binaries and results

This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.

Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-riscv,tests: Add insttests for RV64C

This patch adds instruction tests for the RV64C extension
implementation. It also updates existing executables for the latest
riscv-tools now that they are compatible.

[Update for changes to parents.]

Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e
Reviewed-on: https://gem5-review.googlesource.com/3862
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests: Update RISC-V hello test and stats

Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.

Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

riscv: fix Linux problems with LR and SC ops

Some of the functions in the Linux toolchain that allocate memory make
use of paired LR and SC instructions, which didn't work properly for
that toolchain. This patch fixes that so attempting to use those
functions doesn't cause an endless loop of failed SC instructions.

Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7
Reviewed-on: https://gem5-review.googlesource.com/2340
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: fix compatibility with Linux toolchain

Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain
(riscv64-unknown-elf-*) due to incorrect assumptions made in the initial
setup of the user stack in SE mode. This patch fixes that by referring
to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and
setting up the stack according to how it does it. Now binaries compiled
using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as
well.

[Update for recent changes to MemState to add accessors and mutators to
get its members.]

Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285
Reviewed-on: https://gem5-review.googlesource.com/2305
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

alpha: Remove ALPHA tru64 support and associated tests

No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.

tests: Add example of using KVM acceleration with an app

Add #ifdef's to gpu-hello.cpp demonstrating how to annotate an application
for KVM acceleration.

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.

gpu-compute: AMD's baseline GPU model

tests: A test program for the new mwait implementation.

This is a simple test program for the new mwait implemenation. It is uses
m5threads to create to threads of execution in syscall emulation mode that
interact using the mwait instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

X86: Add a 32 bit hello world test binary.

test: Hello world test program for Power
includes reference outputs for the Hello World tests on simple-atomic
and o3-timing.

ARM: Replace hello world with an EABI version.

ARM: Add a hello world binary.

Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.

Add Alpha Linux version of "hello world" test.

Alpha "hello world" test is really Tru64 not Linux... oops.

Finish test clean-up & reorg.

configs/common/FSConfig.py:
Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
make it work again
src/python/m5/objects/BaseCPU.py:
Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
Increase default stack size so we don't get an
'increasing stack' message on 'hello world'
tests/SConscript:
Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
fix
tests/run.py:
move configs to separate dir

More restructuring of regression tests.
Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
Create default TLBs in full system.
Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
Add _mem_ports
tests/run.py:
Add binpath()
Change maxtick default to 'forever'
tests/simple-atomic.py:
Use connectmemPorts()
tests/simple-timing.py:
Fix up.