tests, arm: Make switcheroo and checkpoint tests functional

Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.

Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

stats: Update to match classic memory changes

stats: update references

stats: update references

stats: Update stats to reflect ARM changes

stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

stats: Update ref stats to match ARM TLB changes

stats: Update to match ARM ISA changes

stats: update and fix e273e86a873d

stats: update for snoop filter tweak

stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.

stats: overdue updates to long regressions

stats: Update stats to reflect changes to cache and crossbar

stats: Update to reflect changes to PCI handling

stats: Update to reflect changes to RealView platform code

stats: remove wb_penalized and wb_penalized_rate

stats: Update stats to match cache changes

stats: Update stats to reflect snoop-filter changes

stats: updates due to recent changesets including d0934b57735a

stats: Update ARM stats to include programmable oscillators

stats: update stale config.ini files, eio and few other stats.

stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.

arm, stats: Update stats to reflect reduction in misc reg reads

stats: Update stats to reflect cache changes

stats: update for previous changeset

Very small differences in IQ-specific O3 stats.

stats: changes to due to recent set of patches

stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

stats: Bump stats for fixes, mostly TLB and WriteInvalidate

stats: Bump regressions to match latest changes

Updates after timezone hick-up and sorting of dictionary items in the
SimObject.

tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.

tests: Update regressions for the new kernels and various preceeding fixes.

stats: updates due to changes to x86, stale configs.