stats: Update ARM FS stats.

The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.

commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000

arm, kmi: Clear interrupts in KMI devices

Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Get all stats updated to reflect current behaviour

Line everything up again.

stats: Update stats to reflect cache changes

stats: Update stats to reflect recent changes to floats

Mostly just splitting out the floats ops and corresponding
reads/writes.

stats: update references

stats: Update to match classic memory changes

stats: update references

stats: Update stats to reflect ARM changes

stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

stats: update and fix e273e86a873d

stats: update for snoop filter tweak

stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.

stats: Update stats to reflect changes to cache and crossbar

stats: Update to reflect changes to PCI handling

stats: Update to reflect changes to RealView platform code

stats: Update stats to match cache changes

stats: Update stats to reflect snoop-filter changes

stats: updates due to recent changesets including d0934b57735a

stats: Update ARM stats to include programmable oscillators

stats: update stale config.ini files, eio and few other stats.

stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.

stats: Update MinorCPU regressions after accounting fix

arm, stats: Update stats to reflect changes to generic timer

The addition of a virtual timer affects stats in minor and o3.

stats: Update stats to reflect cache changes

stats: update Minor stats due to PF bug fix

A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads. Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly. These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.

stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

stats: changes due to recent changesets.

stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

stats: Bump stats for fixes, mostly TLB and WriteInvalidate

stats: Bump regressions to match latest changes

Updates after timezone hick-up and sorting of dictionary items in the
SimObject.

tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.

tests: Update regressions for the new kernels and various preceeding fixes.