14143:0981b2cc0a73 |
29-May-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Add Arm full system regressions to the new framework
Change-Id: I7e0499c8c3d63798d44f936580eecd40dc650694 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18989 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
14142:e732d3191b7c |
29-May-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Add support for downloaded archive fixtures
This changes add support for specifying fixtures that download archives and uncompress them to the desired directory.
Change-Id: Ib3f6ee111b8d6130200507cbd170ecaf9fb39445 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18988 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
14141:b3ceff47211a |
18-Jun-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Refactor the Gem5Fixture to derive from UniqueFixture
Gem5Fixture is used to define a fixture for building the gem5 binary. Most tests are expected to define their own Gem5Fixture, however, as some might depend on the same binary (e.g., ./build/ARM/gem5.opt), they will try to re-define a fixture for the same target. This patchset changes Gem5Fixture to derive from UniqueFixture.
In addition, this patchset changes the way global fixtures are discovered to work with the new Gem5Fixture class. Instead of enumerating them when test definitions are loaded, we do so after the tests have been filtered according to specified tags (e.g., include opt variant, exclude fast, debug variants).
Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19251 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
14140:1e197b8006e2 |
18-Jun-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Add base class for fixtures that generate a target file
The new TargetFixture can be used as a base class for fixtures that generate/download a file. These fixtures are guarrantied to be unique and their setup function is only executed once.
Change-Id: I6a8737b06c4e74f3e29736ec363f61251d85da8c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19250 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14137:31b40f827718 |
11-Mar-2019 |
Brandon Potter <brandon.potter@amd.com> |
sim-se, tests: add a new sim-se test
This changeset adds a test to check the redirection features added in faux-filesystem changeset. The test contains a "chdir" system call to "/proc" which should be redirected to "$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo" file which should output a configuration of a fake cpu with values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error, make sure that you run this test with "-n2" supplied to the "config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17112 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13950:9e276d20eb41 |
08-May-2019 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
tests: Fix import scope of test
Add missing scope delimiters to Alpha tester
Change-Id: Ib6796864c0dc8fc3108d9d2a7c2f770d2122889a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18708 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13929:10f74274f35b |
01-May-2019 |
Gabe Black <gabeblack@google.com> |
tests: There is no architecture called "timing".
I'm sure that's supposed to be "x86". By switching it over, the x86 regression tests became runnable again.
Change-Id: I9505703a0be71047ef3dd312ae83e76c2b32fdb5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18568 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13916:efa5b9e899e3 |
01-May-2019 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
tests: Add missing kernels to system creation
Change 149c1fc2d070a8ce073263880ecf2ccf7535e569 removed the default value of the kernels, and fs tests rely on those.
Change-Id: I6d83420af5881ab59c2d223a9915f363dd8a1c69 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18528 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13852:9bed9098eefe |
11-Mar-2019 |
Rutuja Oza <roza@ucdavis.edu> |
tests: Add tests for learning_gem5 configs
Change-Id: Ia9cbb77115c741051c871526517bb7d8124a8051 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17873 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13851:a71317af0ac2 |
04-Apr-2019 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add protocol as an option to SconsFixture
Change-Id: I16e9a6169e7ad50601e460e221d6a05db1208783 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17872 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13850:2fe3f3dff0d7 |
28-Feb-2019 |
Hoa Nguyen <hoanguyen@ucdavis.edu> |
tests: add riscv to cpu tests
Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13833:adc8bcd80f59 |
03-Dec-2018 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add Jenkins presubmit and continuous test scripts
Note that continuous currently isn't used.
Change-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13794:358671c535ce |
15-Mar-2019 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add ignore for stdin not terminal
Change-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13793:3fc62003f9cc |
15-Mar-2019 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Use full path for DownloadedProgram
Change-Id: I1dceca80a425293d64f81b06ddff499363f18bc0 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17454 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13792:5c285a1a059a |
14-Mar-2019 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Fix race condition in download fixture
Change-Id: Idace0e9e71a484080fc581e232ce217b449085c1 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17453 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13790:ed7f0a384c22 |
13-Mar-2019 |
Jason Lowe-Power <jason@lowepower.com> |
tests,ext: Add skip_cleanup implementation for TempdirFixture
Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13789:d7b2be2c468b |
14-Mar-2019 |
Jason Lowe-Power <jason@lowepower.com> |
ext,tests: Make return code based on test results
This patch also fixes a spelling mistake.
Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13718:89e8bcc7253b |
28-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Update test scripts to work with Python 3
Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13680:c55979b076f1 |
24-Jan-2019 |
Ayaz Akram <yazakram@ucdavis.edu> |
tests: add cpu tests to the new testing infrastructure
Change-Id: I42996ddc802ef279ab4970afc37cb0df25c04b08 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15857 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13679:bc1188a6c0f0 |
24-Jan-2019 |
Ayaz Akram <yazakram@ucdavis.edu> |
tests: Move test programs paths to related test scripts
This change is needed to make sure that the DownloadedProgram fixture does not fail, in case the test binaries are not stored in test-progs/ (e.g. in the case of cpu tests)
Change-Id: Icf96f2537b038502e78da560c7ccebc44984b509 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15856 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rutuja Govind Oza <roza@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13677:948898e8b17e |
23-Aug-2018 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Convert memtest to new framework
The original memtest is located at: https://gem5.googlesource.com/public/gem5/+/master/tests/configs/memtest.py
Change-Id: I58be6fb1675f6502d6644d502915df80aa197a4a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/15836 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13676:831fc4270d4c |
23-Aug-2018 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Convert tgen-simple-memory to new framework
The original test is located at: https://gem5.googlesource.com/public/gem5/+/master/tests/configs/tgen-simple-mem.py
Change-Id: I13a58cfb3d01d08ef7c818fc00fb56ba126eb4b6 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/15835 Reviewed-by: Rutuja Govind Oza <roza@ucdavis.edu> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13666:ea0c43328b8c |
10-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Rewrite Makefiles for pthreads test
The Makefiles for the pthreads test don't behave like typical Makefiles that support cross compilation. Rewrite the Makefile to make cross-compilation more convenient and add targets for aarch{32,64}.
Change-Id: I7cae378492681744b6bb11dd5af69db81ec54229 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13619:44b5224b2ff4 |
28-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add a helper to run external scripts
Some tests are really just a wrapper around a test script in configs/. Add a helper method to wrap these scripts to make sure they are executed in a consistent environment. This wrapper sets up a global environment that is identical to that created by main() when it executes the script. Unlike the old wrappers, it updates the module search path to make relative imports work correctly in Python 3.
Change-Id: Ie9f81ec4e2689aa8cf5ecb9fc8025d3534b5c9ca Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15976 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13618:47a709f53226 |
27-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Don't override tick rate in Ruby tests
Most Ruby tests assume that the highest frequency in the system under test is 1GHz and limits the global tick rate to this frequency. This assumption is broken since the default Ruby configuration scripts clock the CPU at 2Ghz, which results in warnings and sometimes incorrect behaviour.
Change-Id: I4b204660862ce3b0ea4a13df42caacd4398fef8c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15975 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13607:6f34290bb182 |
25-Jan-2019 |
Ciro Santilli <ciro.santilli@arm.com> |
tests: fix arm regression due to kernel not found
At Ia49298304f658701ea0800bd79e08db404a655c3 we removed the default kernel and DTB filenames from FSConfig.py.
However, the regression tests rely on that to find those blobs.
This commit restores those default filenames just for the config of the regression tests.
Change-Id: I9d7d869b0087ee8a3b63088693f753a703ead5d6 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15957 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13566:4f44bb849db4 |
16-Jan-2019 |
Gabe Black <gabeblack@google.com> |
tests: Fix tests/main.py so it can be run from anywhere.
tests/main.py was trying to find paths relative to itself using the string __name__ (which was __main__) when it should have been using the string __file__ which holds the name of the file being executed.
Change-Id: I5ff4c42fc7d8b75ff6b96c3cde61baf731d84738 Reviewed-on: https://gem5-review.googlesource.com/c/15675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13540:da30e62884ee |
10-Jan-2019 |
Andrea Mondelli <andrea.mondelli@ucf.edu> |
misc: updated shabang for python script
The default python on MacOS doesn’t have an alias to python2. The official python version supported in gem5 is Python2.7.
This patch updates the shabang according to the version required in gem5.
Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0 Reviewed-on: https://gem5-review.googlesource.com/c/15375 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
13012:5fbc6b9c64bc |
15-Mar-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
cpu: Replace the fastmem with a new CPU model
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12891:be237bd778f8 |
19-May-2017 |
Brandon Potter <brandon.potter@amd.com> |
tests: add a stack printer test
Add a test to print out stack contents for SE mode programs. The test will print out argc, argv, envp, and some auxiliary vectors.
Change-Id: I489d752ee40fde24c531d8918d0c050f4df936c5 Reviewed-on: https://gem5-review.googlesource.com/3440 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12887:ffa7ebca19b0 |
18-Apr-2018 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add explicit build test
Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/10121 |
12886:cba9b724a357 |
03-Aug-2017 |
Sean Wilson <spwilson2@wisc.edu> |
tests: Add test for the m5-exit instruction.
Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4423 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> |
12885:27839b63374a |
03-Aug-2017 |
Sean Wilson <spwilson2@wisc.edu> |
tests: Add a simple example test
Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4422 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> |
12884:47532842a728 |
21-Sep-2017 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add Makefiles for hello
This adds Makefiles for hello for ARM and x86 by leveraging docker and dockcross. See https://github.com/dockcross/dockcross for more information.
These Makefiles also allow for automatic uploading to the correct location for users to download when running the new tests.
Change-Id: I7085000393cd5283502a7af362c85befda749181 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4883 |
12882:dd87d7f2f3e5 |
03-Aug-2017 |
Sean Wilson <spwilson2@wisc.edu> |
tests,ext: Add a new testing library proposal
The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5.
Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12881:57339a66cd77 |
21-Sep-2017 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Fix hello.c test program
Update the hello test to have a sane return code.
Change-Id: I9576b71ee995d8aa410c4ed19d44cc4e9fad10ee Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4881 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12771:75508af5d8dc |
22-May-2018 |
Tuan Ta <qtt2@cornell.edu> |
tests,style: add RISC-V assembly tests
This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project.
The tests have been slightly modified to work in gem5 SE mode:
(1) Removed a trap handler used in riscv-tests for bare-metal systems
(2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes.
In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system.
(1) rv64uamt: multi-threaded tests for A-extension instructions
(2) rv64samt: multi-threaded tests for clone and futex system calls
This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions.
Please find more details in the README file included in this patch.
Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12751:05138dd753f8 |
13-Feb-2018 |
Tuan Ta <qtt2@cornell.edu> |
tests: add some pthread and std::thread unit tests
This patch adds some pthread and C++11 std::thread unit tests.
Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72 Reviewed-on: https://gem5-review.googlesource.com/8221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
12726:850e9965525b |
05-Feb-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
mem-cache: Add a non-coherent cache
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded.
This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com>
Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
12598:b80b2d9a251b |
12-Feb-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arch-arm, configs: Treat the bootloader rom as cacheable memory
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12590:e483f68d2aae |
25-Jul-2017 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Add test program for C++ threads
Simple program that spawns threads equal to the number of CPU cores and has some false sharing for testing coherence protocols.
Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8901 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
12581:a8f1d31d3492 |
13-Mar-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
tests: Add missing print replacements in tests subdir
Some python files were still using deprecated print statement.
Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9141 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12575:16ada03839d9 |
09-Mar-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
tests: Python regression scripts using new print function
Change-Id: I92060da4537e4ff1c0ff665f2f6ffc3850c50e88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8892 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12563:8d59ed22ae79 |
06-Mar-2018 |
Gabe Black <gabeblack@google.com> |
scons: Switch from the print statement to the print function.
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files.
Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12428:ddc6b7179c81 |
02-Dec-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Make use of ImmOp's polymorphism
This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
12268:54566b73dc61 |
16-Dec-2016 |
Radhika Jagtap <radhika.jagtap@arm.com> |
tests: Add tests for DRAM low power modes
This patch adds two regression tests that execute the script in the configs dir for triggering low power mode transitions. A separate test is required for each page policy because for close-adaptive page policy the DRAM goes into the Precharge Power-down mode while for open-adaptive page policy it goes into the Activate Power-down mode.
Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5726 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12246:9ffa51416f39 |
08-Nov-2017 |
Gabe Black <gabeblack@google.com> |
scons: Move Transform and termcap functionality into their own files.
Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7 Reviewed-on: https://gem5-review.googlesource.com/5565 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
12215:5f6e684f3f16 |
27-Sep-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
tests: Fix path for module imports in ARM system configs again
One configuration was missed in "tests: Fix path for module imports in ARM system configs", which this changeset remedies.
Change-Id: I705e64298a8251dcfefbdca927d61c9bbb8bbea7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12147:af4da4e636f5 |
25-Jul-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Fix path for module imports in ARM system configs
Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4220 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12142:f6ccdb328a23 |
30-Jun-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Don't treat new stats as a cause for failures
We currently fail the stat diff stage of tests if there are new stats. This is usually undesirable since this would require any change that adds a stat to also update the regressions.
Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3962 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12137:d877205ec1bc |
13-Jul-2017 |
Alec Roelke <ar4jc@virginia.edu> |
tests: Upate RISC-V binaries and results
This patch updates the binaries and results for hello and insttest regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12121:663aa56b08b4 |
09-Jul-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv,tests: Add insttests for RV64C
This patch adds instruction tests for the RV64C extension implementation. It also updates existing executables for the latest riscv-tools now that they are compatible.
[Update for changes to parents.]
Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e Reviewed-on: https://gem5-review.googlesource.com/3862 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12097:77a3d2890ba6 |
26-Jun-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
config: Move core timing models to config/common/cores
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12075:2f691b779441 |
15-Jun-2017 |
Sean Wilson <spwilson2@wisc.edu> |
tests: Fix a typo for the default MI_example protocol
Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3795 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12070:d89ac2ebc159 |
30-Mar-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Add ARM MOESI_CMP_directory regressions
Change-Id: I3d9c1249a2d39f20fb60c4d4e8af7d1d5731dbef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2908 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12068:0097c445aa64 |
17-Mar-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
scons: Make MOESI_CMP_directory the default ARM ruby protocol
Previously ARM binaries were by default compiled with the MI_example protocol. The MI_example protocol cannot properly support load/store exclusive instructions and therefore it cannot be used to simulate multicore ARM systems. This change changes to MOESI_CMP_directory as the default ruby protocol for ARM systems.
Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2906 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12062:d6ee16239a26 |
31-May-2017 |
Alec Roelke <ar4jc@virginia.edu> |
tests: Update RISC-V hello test and stats
Update the "Hello, world!" executable for RISC-V to use the latest GNU Linux toolchain and fix the stats accordingly.
Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022 Reviewed-on: https://gem5-review.googlesource.com/3560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
11988:665cd5f8b52b |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Use PyBind11 instead of SWIG for Python wrappers
Use the PyBind11 wrapping infrastructure instead of SWIG to generate wrappers for functionality that needs to be exported to Python. This has several benefits:
* PyBind11 can be redistributed with gem5, which means that we have full control of the version used. This avoid a large number of hard-to-debug SWIG issues we have seen in the past.
* PyBind11 doesn't rely on a custom C++ parser, instead it relies on wrappers being explicitly declared in C++. The leads to slightly more boiler-plate code in manually created wrappers, but doesn't doesn't increase the overall code size. A big benefit is that this avoids strange compilation errors when SWIG doesn't understand modern language features.
* Unlike SWIG, there is no risk that the wrapper code incorporates incorrect type casts (this has happened on numerous occasions in the past) since these will result in compile-time errors.
As a part of this change, the mechanism to define exported methods has been redesigned slightly. New methods can be exported either by declaring them in the SimObject declaration and decorating them with the cxxMethod decorator or by adding an instance of PyBindMethod/PyBindProperty to the cxx_exports class variable. The decorator has the added benefit of making it possible to add a docstring and naming the method's parameters.
The new wrappers have the following known issues:
* Global events can't be memory managed correctly. This was the case in SWIG as well.
Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2231 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves PĂ©neau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11976:d1f151ee0e08 |
21-Apr-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Remove unused options from tests.py
The test sub-command in tests.py incorrectly accepts various formatting options in its usage string. These options aren't needed since the test command doesn't produce any output.
Change-Id: I6d4731aa32a25a2286aa66548eaa0154a9392f79 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11965:41e942451f59 |
21-Mar-2017 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: fix Linux problems with LR and SC ops
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions.
Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11964:0b67d2ce9801 |
21-Mar-2017 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: fix compatibility with Linux toolchain
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well.
[Update for recent changes to MemState to add accessors and mutators to get its members.]
Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11960:c7bf1b698ccd |
29-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11959:c000bfbbdadd |
30-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the stats for 70.twolf for x86 o3-timing mode.
The following CL changed the stats:
commit 43418e7f81099072fb7d56dae11110ae1d858162 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 13:07:43 2017 -0600
syscall-emul: Move memState into its own file
It would be a good idea to try to figure out why, since it doesn't *look* like this change was intended to move things around in memory or otherwise change simulated behavior.
Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63 Reviewed-on: https://gem5-review.googlesource.com/2655 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11958:baaa90eed7b3 |
28-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update 04.gpu stats.
A new stat was added by the CL:
commit b043dcf58ad766582aeab162fb855cc3fc95f2cf Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Feb 27 13:17:51 2017 +0000
gpu-compute: Fix Python/C++ object hierarchy discrepancies
Change-Id: I665a7eb0bea19f379c5fbaaf4686fcbe8c008159 Reviewed-on: https://gem5-review.googlesource.com/2654 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11957:90bb43dfc028 |
29-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update ARM FS stats.
The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression.
commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000
arm, kmi: Clear interrupts in KMI devices
Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11956:9366df873131 |
30-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the 40.m5threads stats.
The change below changed the stats for the o3 version of the 40.m5threads regression.
commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
Change-Id: I601c58d8d1453cf93f2065ea5816b63b553610e0 Reviewed-on: https://gem5-review.googlesource.com/2652 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11955:1170d039b31e |
03-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Rename num_syscalls to numSyscalls in the reference stats.
The name of the stat was changed in the following change which broke all the reference outputs.
commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40 Reviewed-on: https://gem5-review.googlesource.com/2651 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11954:19e1cd4edfd2 |
30-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.
The following change removed a write to an integer register when completing a system call. This changed the reference statistics slightly.
commit 073cb266079edddec64ea8cd5169dd2cbef8f812 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:02 2017 -0500
syscall_emul: [patch 14/22] adds identifier system calls
Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d Reviewed-on: https://gem5-review.googlesource.com/2650 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11953:b6924be765e4 |
28-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the stats for 04.gpu for x86/linux/gpu-ruby-GPU_Rf0.
These stats were changed by this CL:
commit a4b546c3a139aeb33f087422637ac06fc4477d11 Author: Matthew Poremba <matthew.poremba@amd.com> Date: Thu Jan 19 11:58:59 2017 -0500
ruby: Add occupancy stats to MessageBuffers
Change-Id: I9713ed44d94cba424cdfa92d746dfe8007583b40 Reviewed-on: https://gem5-review.googlesource.com/2649 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11952:a1b3c659b926 |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the solaris boot stats for the new op classes.
The change below introduced some new op classes which have their own stats, and the counts the instructions used to be under have gone down.
commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318 Author: Fernando Endo <fernando.endo2@gmail.com> Date: Sat Oct 15 14:58:45 2016 -0500
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb Reviewed-on: https://gem5-review.googlesource.com/2648 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11951:fbc62d4732be |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the solaris boot stats for the default snoop_filter.
The snoop_filter was enabled by default by this change:
commit 080d4e08d627b5b726afec71d38370373b7376c5 Author: Andreas Hansson <andreas.hansson@arm.com> Date: Fri Aug 12 14:11:45 2016 +0100
mem: Add snoop filter to SystemXBar by default
Change-Id: I850473c70437588b47812f1dc00d6ecdb66daa36 Reviewed-on: https://gem5-review.googlesource.com/2647 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11950:8011fd8ce05c |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update the solaris boot stats for new snoopTraffic stat.
The following change added the new stat:
commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100
mem: Add snoop traffic statistic
Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11948:b6e775495efd |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Update SPARC solaris boot stats.
The CPU power state bins where changed by the following CL:
commit fb5fc11da49938660ea22c336964677cdba890e1 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100
pwr: Low-power idle power state for idle CPUs
Change-Id: I8b3924681c8a85b7bbe061b671faf274ce882f91 Reviewed-on: https://gem5-review.googlesource.com/2644 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11947:a352cfd27fc6 |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Remove stats from the SPARC solaris boot which were silenced.
These were silenced in:
commit d4342aff4ce347ad8ab5a01fdd41993106cd3ece Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100
stats: Silence unused power stats
Change-Id: I273e8190b76335505bedfea88ef89abee1739b8a Reviewed-on: https://gem5-review.googlesource.com/2643 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11946:8eb1f2595a92 |
04-Apr-2017 |
Gabe Black <gabeblack@google.com> |
stats: Add a boat load of stats to the SPARC solaris boot regression.
A large number of stats were added by the following change:
commit 5350879f499470a2683dfec6cff021dd7ac20fa6 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100
pwr: Add power states to ClockedObject
Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2 Reviewed-on: https://gem5-review.googlesource.com/2642 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11945:b5d6a502d2da |
28-Mar-2017 |
Gabe Black <gabeblack@google.com> |
stats: Un-empty the SPARC FS stats.txt file.
This was emptied accidentally by the CL below. A lot of other files were too, but those were eventually refilled.
commit 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce Author: Curtis Dunham <Curtis.Dunham@arm.com> Date: Tue May 31 11:07:18 2016 +0100
stats: update for snoop filter tweak
Change-Id: I34aefca51a92a6a98f6a8fdbdab7106cc1fff171 Reviewed-on: https://gem5-review.googlesource.com/2641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
11917:6b5cded90c35 |
01-Sep-2016 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
tests: Warn not fail when reading invalid pickle status files
With this change, the test script will output a warning when it reads an incomplete (e.g., when a regression is still running) or corrupt status file instead of throwing an exception. When the scipt is used to show the results the corrupt file is skipped; when it is used to test if all regressions run successfully it will return an error value (2).
Change-Id: Ie7d9b457b200e3abc7ae6238e3efbf3d18cf4297 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2320 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
11885:79af314e9f0d |
27-Feb-2017 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 14/22] adds identifier system calls
This changeset add fields to the process object and adds the following three system calls: setpgid, gettid, getpid. |
11880:8c369af31b6c |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
base: Refactor logging to make log level selection cleaner
It's currently possible to change the log level in gem5 by tweaking a set of global variables. These variables are currently exposed to Python using SWIG. This mechanism is far from ideal for two reasons: First, changing the log level requires that the Python world enables or disables individual levels. Ideally, this should be a single call where a log level is selected. Second, exporting global variables is poorly supported by most Python frameworks. SWIG puts variables in their own namespace and PyBind doesn't seem to support it at all.
This changeset refactors the logging code to create a more abstract interface. Each log level is associated with an instance of a Logger class. This class contains common functionality, an enable flag, and a verbose flag.
Available LogLevels are described by the LogLevel class. Lower log levels are used for more critical messages (PANIC being level 0) and higher levels for less critical messages. The highest log level that is printed is controlled by calling Logger:setLevel().
Change-Id: I31e44299d242d953197a8e62679250c91d6ef776 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11879:7388b21d7eac |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Disable descriptions in stat files
Don't output verbose text descriptions in stat files when running tests. This saves a lot of space when storing reference data.
Change-Id: I2a7ead4843586e800ecf83846694b73f0c356373 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> |
11860:67dee11badea |
19-Feb-2017 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Get all stats updated to reflect current behaviour
Line everything up again. |
11851:824055fe6b30 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process. |
11837:17b37f38944a |
14-Feb-2017 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both the channel and device data width.
Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width
Total channel width can be calculated by n*w
Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11836:3195e72010da |
14-Feb-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
tests: check for gem5 binary before tests
Provides a helpful error when tests.py is invoked without the gem5 binary.
Before: Running 0 tests
After: gem5 binary 'quick/...' not an executable file
Change-Id: I1566802206c9e21ca89bd03e91db22844168a085 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11833:0e73ec98b6bc |
13-Feb-2017 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: Remove ECALL tests from insttest
The system calls tested in rv64i.cpp in RISC-V's insttest suite have different behavior depending on the operating system and file system they are run on. This patch ignores the output of those tests and only ensures that the instructions in RV64I complete successfully.
[Change deletion of ECALL test to block comment.] [Restore ECALL test but remove test output to test only for completion without error.] [Update patch description and again try to push EMPTY files for rv64i tests.] |
11828:36b064696175 |
10-Feb-2017 |
Jason Lowe-Power <jason@lowepower.com> |
misc: Update #!env calls for python to explicit version
In some newer Linux distributions, env python default to Python 3.0. This patch explicitly uses "python2" instead of just "python" for all scripts that use #!
Reported-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Jason Lowe-Power <jason@lowepower.com> |
11802:be62996c95d1 |
26-Jan-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Move native wrappers to the _m5 namespace
Swig wrappers for native objects currently share the _m5.internal name space with Python code. This is undesirable if we ever want to switch from Swig to some other framework for native binding (e.g., PyBind11 or Boost::Python). This changeset moves all of such wrappers to the _m5 namespace, which is now reserved for native code.
Change-Id: I2d2bc12dbc05b57b7c5a75f072e08124413d77f3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11775:0eadb0b6e9de |
19-Dec-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references |
11754:c209cb86278a |
05-Dec-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect cache changes |
11731:c473ca7cc650 |
30-Nov-2016 |
Jason Lowe-Power <jason@lowepower.com> |
tests: Regression stats updated for recent patches |
11730:08ab68477ea0 |
30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: [Patch 8/5] Added some regression tests to RISC-V
This patch is the eighth patch in a series adding RISC-V to gem5, and third of the bonus patches to the original series of five. It adds some regression tests to RISC-V.
Regression tests included: - se/00.hello - se/02.insttest (split into several binaries which are not included due to large size)
The tests added to 00.insttest will need to be build manually; to facilitate this, a Makefile is included. The required toolchain and compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools GitHub repository at https://github.com/riscv/riscv-tools.
Note that because EBREAK only makes sense when gdb is running or while in FS mode, it is not included in the linux-rv64i insttest. ERET is not included because it does not make sense in SE mode and, in fact, causes a panic by design.
Note also that not every system call is tested in linux-rv64i; of the ones defined in linux/process.hh, some have been given numbers but not definitions for the toolchain, or are merely stubs that always return 0. Of the ones that do work properly, only a subset are tested due to similar functionality.
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
11720:482900205561 |
30-Nov-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Check for TrafficGen as part of memcheck regression
Since protobuf is still considered optional we do not always have the TrafficGen. Check before running the memcheck regression. |
11707:1d085f66c4ca |
17-Nov-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats, alpha: Update ALPHA stats
Reflect the removal of the syscall tracking. |
11706:7339a92fffb5 |
17-Nov-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)
This patch avoids compiling ALPHA six times as part of running 'util/regress', and instead relis on NULL with different protocols to run the rubytest. All we need is the memory system, so there is really no need to compile the ISA over and over again.
The one downside is the removal of running 'hello' for the variuos ALPHA and protocol combinations, but if this is a concern we should rather beef up the synthetic tests for the variuos protocols. |
11705:d40bdd3c5778 |
17-Nov-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues and increases the development and maintenance effort. |
11687:b3d5f0e9e258 |
19-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding reads/writes. |
11682:612f75cf36a0 |
14-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Make configs/common a Python package
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package.
All affected config scripts are updated (hopefully).
Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages. |
11680:b4d943429dc6 |
13-Oct-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references |
11670:6ce719503eae |
13-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
ruby: Fix regressions and make Ruby configs Python packages
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories.
As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified. |
11651:d000cf4157ae |
21-Sep-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests, arm: Reinstate accidentally removed switcheroo tests
Two of the switcheroo tests were accidentally removed due to unexpected Mercurial behavior.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11649:f54a527153f4 |
22-Sep-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
test: Make the memtest and memcheck tests functional only
The memtest and memcheck are not designed to test timing. Make them functional only to make ref diffs less noisy in the future.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11648:200501cf7025 |
22-Sep-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Make remaining switcheroo tests functional only
The switcheroo tests only really serve to check functional correctness. Checking for stat differences in them just increases the size of reference diffs.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11637:94fd30b3e1cb |
16-Sep-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be successful if they run to completion. Remove all reference output files from the switcheroo and checkopint tests to make them purely functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11636:2cdb85a2e980 |
16-Sep-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add support for functional only tests
Modify the ClassicTest class to only emit a stat verification test unit if there is a reference stat file. This makes it possible to design tests that don't care about stat changes.
To generate purely functional tests, we need to be able to create empty test reference directories. This does not work well with many revision control systems. As a workaround, add a file named EMPTY to the list of ignored files in the test harness. This file can be used as a placeholder in otherwise empty test directories.
Change-Id: I583c8c4e55479f0d48fa99d0b0d1eac9221e6652 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11615:ceece50bbf08 |
22-Aug-2016 |
David Hashe <david.j.hashe@gmail.com> |
tests: Add example of using KVM acceleration with an app
Add #ifdef's to gpu-hello.cpp demonstrating how to annotate an application for KVM acceleration. |
11607:b2720503a978 |
13-Aug-2016 |
Steve Reinhardt <stever@gmail.com> |
tests: remove EIO tests
An email sent to gem5-users and gem5-dev asking if anyone was still using EIO traces got no responses, so it seems like it's not worth maintaining this any longer. |
11606:6b749761c398 |
12-Aug-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update to match classic memory changes |
11604:b254396b7759 |
12-Aug-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add snoop filter to SystemXBar by default
This patch changes the default behaviour of the SystemXBar, adding a snoop filter. With the recent updates to the snoop filter allocation behaviour this change no longer causes problems for the regressions without caches.
Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> |
11589:af2f7fef4875 |
02-Aug-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references |
11571:62f97810876a |
22-Jul-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add regex-based ignore rules for ref files
There are cases where we need to ignore files with specific extensions (e.g., when Mercurial litters the file system with patch rejects). Implement this functionality using a helper class (FileIgnoreList) that supports both regular expressions and basic string comparisons.
Change-Id: I34549754bd2e10ed230ffb2dc057403349f8fa78 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11570:4aac82f10951 |
21-Jul-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update references |
11552:354e5631a6c1 |
01-Jul-2016 |
Abdul Mutaal Ahmad <abdul.mutaal@gmail.com> |
mem: tester for new HMC configuration
This patch provides the example test script to configure different HMC architecture and run traffic through traffic generator.
Committed by Jason Lowe-Power <jason@lowepower.com> |
11547:dd6dfd38b6c2 |
21-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update stats to reflect ARM changes |
11543:b5435e0310c7 |
20-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add a test command to get test status as an exit code
Add a "test" command to tests.py that queries a test pickle file and returns different exit codes depending on the outcome of the tests in the file. The following exit codes can currently be returned:
* 0: All tests were successful or skipped.
* 1: General fault in the script such as incorrect parameters or failing to parse a pickle file.
* 2: At least one test failed to run. This is what the summary formatter usually shows as a 'FAILED'.
* 3: All tests ran correctly, but at least one failed to verify its output. When displaying test output using the summary formatter, such a test would show up as 'CHANGED'.
The command can be invoked like this:
./tests/tests.py test `find build/ARM/tests/opt/ -name status.pickle`
Change-Id: I7e6bc661516f38ff08dfda7c4359a1e10bf97864 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11542:ecd058e3dcbe |
20-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Split test results into running and verification
The test base class already assumes that test cases consists of a run stage and a verification stage. Reflect this in the results class to make it possible to detect cases where a run was successful, but didn't verify.
Change-Id: I31ef393e496671221c5408aca41649cd8dda74ca Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11540:582b379f6d4f |
20-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
mem: Resolve TrafficGen trace relative to the config
The traffic generator currently resolves relative trace paths relative to gem5's current working directory. This can lead to surprising results for relative paths where the expectation would normally be that they are resolved relative to the configuration file. This changeset implements config-relative trace file lookups. The old behavior is kept as a fallback for configs that expect that behavior.
Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11535:80e79ae636ca |
12-Jun-2016 |
Steve Reinhardt <stever@gmail.com> |
stats: update EIO stats |
11530:6e143fd2cabf |
06-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee |
11521:4ad81380c5e8 |
06-Jun-2016 |
Steve Reinhardt <stever@gmail.com> |
stats: update EIO stats |
11518:7e0f869f8f7e |
02-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update ref stats to match ARM TLB changes |
11516:12928a51616a |
02-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Remove working dir assumption in tgen tests
The traffic generator tests currently assume that they are run from the root of the source directory. This sometimes breaks tests when they are run using the new test framework.
Change-Id: I6538a7902694c5d2c980295e076ea1c09acc4291 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11515:c48c7cc5a522 |
02-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update to match ARM ISA changes |
11512:060fc1591151 |
02-Jun-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
tests: add 'CHANGED' output to pickle viewer
Change-Id: I64c69fde8657c273adea69122877c5348a4f867a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11511:3c383d9a7c31 |
02-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Only run Ruby tests when testing Ruby targets
Limit the test configs to Ruby-only configs when testing a Ruby target that isn't MI_example. This avoids re-running configs that has already been tested by the generic (non-Ruby) ISA target. This behavior was the expected behavior prior to switching to the new test framework.
Change-Id: I3f138dbf9c7071ce862d1073aaec57c59afbc921 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11507:be6065c1d8d2 |
31-May-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update and fix e273e86a873d |
11504:f3184dd8257f |
31-May-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
scons: Use the new test framework from scons
Rewrite the SCons script responsible for launching tests to use the new test framework. The biggest visible change after this changeset is that SCons no longer produces a "status" file in test build directories. Instead, it creates a status.pickle file. That file can be inspected using the new tests.py script. Another visible change is that timed out tests are now reported as failed rather than a using a separate summary message.
Since the pickle file will remain in the build directory after running tests, it's now possible to convert the test results into other formats. For example:
./tests/tests.py show --format junit -o junit.xml \ `find build/ -name status.pickle`
To better facilitate running outside of scons, there is now a set of targets that generate test listings that can be used by the test script. There are currently three targets, quick.list, long.list, and all.list. For example:
scons build/ARM/tests/opt/all.list for F in `cat build/ARM/tests/opt/all.list`; do ./tests/tests.py run build/ARM/gem5.opt $F done
Change-Id: I2c0f8ca0080d7af737362e198eda4cb3a72e6c36 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11503:e9b095599766 |
31-May-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Fix incorrect stat.txt ignore when updating refs
ClassicTest was incorrectly ignoring stats.txt when updating reference statistics. This was caused by ignore rules being applied too aggressively when listing reference files. This changeset splits the ignore rules into two different lists: 1) diff_ignore_files that lists the files that shouldn't be diff:ed using the normal diff tool, and 2) ref_ignore_files which lists files that should be ignored by the test system.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11502:e273e86a873d |
31-May-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update for snoop filter tweak |
11501:9345c4320477 |
27-May-2016 |
Stephan Diestelhorst <stephan.diestelhorst@arm.com> |
mem, config: Selective use of snoop filter
Disable the default snoop filter in the SystemXBar so that the typical membus does not have a snoop filter by default. Instead, add the snoop filter only when there are caches added to the system (with the caches / l2cache options).
The underlying problem is that the snoop filter grows without bounds (for now) if there are no caches to tell it that lines have been evicted. This causes slow regression runs for all the atomic regressions. This patch fixes this behaviour. |
11482:2ca1efb451e4 |
26-May-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add test infrastructure as a Python module
Implement gem5's test infrastructure as a Python module and a run script that can be used without scons. The new implementation has several features that were lacking from the previous test infrastructure such as support for multiple output formats, automatic runtime tracking, and better support for being run in a cluster environment.
Tests consist of one or more steps (TestUnit). Units are run in two stages, the first a run stage and then a verify stage. Units in the verify stage are automatically skipped if any unit run stage wasn't run. The library currently contains TestUnit implementations that run gem5, diff stat files, and diff output files.
Existing tests are implemented by the ClassicTest class and "just work". New tests can that don't rely on the old "run gem5 once and diff output" strategy can be implemented by subclassing the Test base class or ClassicTest.
Test results can be output in multiple formats. The module currently supports JUnit, text (short and verbose), and Python's pickle format. JUnit output allows CI systems to automatically get more information about test failures. The pickled output contains all state necessary to reconstruct a tests results object and is mainly intended for the build system and CI systems.
Since many JUnit parsers parsers assume that test suite names look like Java package names. We currently output path-like names with slashes separating components. Test names are translated according to these rules:
* '.' -> '-" * '/' -> '.'
The test tool, tests.py, supports the following features:
* Test listing. Example: ./tests.py list arm/quick
* Running tests. Example: ./tests.py run -o output.pickle --format pickle \ ../build/ARM/gem5.opt \ quick/se/00.hello/arm/linux/simple-timing
* Displaying pickled results. Example: ./tests.py show --format summary *.pickle
Change-Id: I527164bd791237aacfc65e7d7c0b67b695c5d17c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joel Hestness <jthestness@gmail.com> |
11475:d372458be20f |
09-May-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Enable test running outside of gem5's source tree
The learning gem5 scripts currently assumes that the current working directory is the root of gem5's source tree. This isn't necessarily the case when running the tests using gem5's new test runner.
Change-Id: Ief569bbe77b1b3e2b0fb0e6c575fb0705bbba9b3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> |
11474:a22c4bac7e15 |
07-May-2016 |
Steve Reinhardt <stever@gmail.com> |
tests: update EIO ref stats for removed cache stats
Complaints about changes in EIO tests were due to reference files that still have removed cache stats from cset 11454:e55afadc4e19. |
11464:5160d2a58007 |
28-Apr-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Remove stale reference output files
Remove test reference files that are not generated any more:
* chair.cook.ppm: This file should be generated by eon and not mcf, so it shouldn't be included as an output from mcf.
* system.pc.terminal: The terminal device has been renamed so this file is no longer generated.
Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11458:91834ba4b16d |
25-Apr-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing memcheck.py script. |
11457:21434dcc83d5 |
21-Apr-2016 |
Jason Power <powerjg@cs.wisc.edu> |
tests: Update learning gem5 tests scripts with copyright |
11456:c0fb4435b80f |
21-Apr-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding. |
11441:0edcf757b6a2 |
09-Apr-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes throughout. |
11440:76b5639162af |
08-Apr-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: update stats for thermals, indirect BP |
11390:f40859930028 |
17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries. |
11388:bd4125134e77 |
17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for mmap changes |
11384:e3cbd2823210 |
17-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call. |
11376:a6968f06a5e0 |
17-Mar-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats to match cache changes
Update stats to match current behaviour. As a result of the earlier conflict check we are seeing a few prefetch requests being ignored before being sent as upward snoops. |
11374:c1525cc9ec7f |
16-Mar-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: overdue updates to long regressions |
11369:0c1ae495b5e4 |
18-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update gpu-ruby-GPU_RfO stats
Output changed way back in this cset:
changeset: 11345:b6a66a90e0a1 user: John Kalamatianos <john.kalamatianos@amd.com> summary: gpu: fix bugs with MemFence, Flat Instrs and Resource utilization |
11356:a80884911971 |
19-Jul-2015 |
Krishnendra Nathella <krinat01@arm.com> |
cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU, recvAtomicSnoop was checking if the incoming packet was an invalidation (isInvalidate) and only then handled a locked snoop. But, writes are seen instead of invalidates when running without caches (fast-forward configurations). As as simple fix, now handleLockedSnoop is also called even if the incoming snoop packet are from writes. |
11353:31c5786945b4 |
24-Feb-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect forwarding of InvalidateReq |
11351:bfc1285c61eb |
24-Feb-2016 |
Matteo Andreozzi <Matteo.Andreozzi@arm.com> |
cpu: TraceGen fix for tick frequency check
Bug fix for check on protobuf file frequency being different than global frequency.
The ASCII encoder script is also fixed, and the example trace used in the regressions is updated. |
11336:b318499f676c |
10-Feb-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect changes to cache and crossbar |
11321:02e930db812d |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'. |
11320:42ecb523c64a |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'. |
11316:b51a72edfcff |
06-Feb-2016 |
Steve Reinhardt <stever@gmail.com> |
stats: update EIO stats for recent changes |
11312:3d7a85d71bd1 |
22-Jan-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
stats: update stats to after GPU checkin |
11310:b4bbf540d1a7 |
22-Jan-2016 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: changed all references to numCPs to num-cp |
11308:7d8836fd043d |
19-Jan-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
gpu-compute: AMD's baseline GPU model |
11298:e535b95573c0 |
17-Jan-2016 |
Steve Reinhardt <stever@gmail.com> |
stats: update SPARC FS stats
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was broken for so long that, now that it's working again, the stats output is out of date. This changeset updates the outputs, on the assumption that the stats changes are all valid differences due to other changes made while it was broken. |
11281:953f7d1cc9e3 |
30-Dec-2015 |
Steve Reinhardt <stever@gmail.com> |
stats: more updates due to PCI changes
A couple of the long regressions have been showing as CHANGED since 11244:a2af58a06c4e despite the updates in 11245:1c5102c0a7a9. The x86 regression looks like it was just missed, but it's not clear why the ARM one is giving different results (perhaps a non-determinism between zizzer and wherever the updated results were run?). |
11280:456e9a93be4b |
28-Dec-2015 |
Steve Reinhardt <stever@gmail.com> |
tests: update EIO reference outputs |
11268:8b4b55d79ddd |
12-Dec-2015 |
Anthony Gutierrez <atgutier@umich.edu> |
stats: bump stats to reflect ruby tester changes |
11267:aa32b0639ee2 |
11-Dec-2015 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: updates required for the compute-gpu patches |
11245:1c5102c0a7a9 |
04-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update to reflect changes to PCI handling |
11239:3be64e1f80ed |
03-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update to reflect changes to RealView platform code |
11232:135c16fa409d |
02-Dec-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats to match current behaviour |
11219:b65d4e878ed2 |
16-Nov-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent chagnesets |
11214:966091379ded |
16-Nov-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: remove wb_penalized and wb_penalized_rate |
11201:b1bd4afb6b16 |
06-Nov-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to match cache changes |
11167:207d6f2f1d53 |
10-Oct-2015 |
Joel Hestness <jthestness@gmail.com> |
stats: Update for UDelayEvent quiesce change |
11156:a37dda0f0202 |
05-Oct-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Update SMT tests to correctly configure CPUs
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. |
11155:d660f0d38e3b |
02-Oct-2015 |
Steve Reinhardt <stever@gmail.com> |
stats: update EIO stats for snoop filter changes |
11150:a8a64cca231b |
30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems. |
11147:cc8d6e99cf46 |
30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be used with other SMT-supported CPUs. Example usage: this enables the TimingSimpleCPU to be used to warmup caches before swapping to detailed mode with the in-order or out-of-order based CPU models. |
11138:a611a23c8cc2 |
25-Sep-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect snoop-filter changes |
11115:39219e0eb24c |
16-Sep-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to MOESI_hammer |
11112:2e49619509e0 |
16-Sep-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: slight changes to MOESI_CMP_token.
Due slight change to latency for the reissue table. |
11106:878dd30741c4 |
16-Sep-2015 |
Jason Lowe-Power <power.jg@gmail.com> |
stats: files for regression tests for Learning gem5 scripts
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
11105:9a1c2b16a2f9 |
16-Sep-2015 |
Jason Lowe-Power <power.jg@gmail.com> |
tests: Add tests for the Learning gem5 scripts
These tests will ensure that Learning gem5 scripts are always up to date with the changes in the mainline of gem5.
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
11103:38f6188421e0 |
15-Sep-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent changesets including d0934b57735a |
11066:969113566d50 |
30-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent changes. |
11026:bf2fc8f7e432 |
14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates to ruby fs regression test
Changes due to recent patches: fc1e41e88fd3, 882ce080c9f7, e8a6637afa4c, and e6e3b7097810 by Joel Hestness. |
11023:97cf7ba82f0c |
14-Aug-2015 |
Joel Hestness <jthestness@gmail.com> |
stats: Bump for MessageBuffer, cache latency changes |
11014:863d314f6356 |
07-Aug-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update ARM stats to include programmable oscillators |
10999:e5744056cf76 |
05-Aug-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Reflect current behaviour
Not sure what went wrong in the pushing of the Ruby patches, but somehow these regressions are not updated. |
10997:32a40cc147ef |
04-Aug-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update stats for tgen to reflect CommMonitor changes
The name of the stack distance stats changed slightly when the stack distance calculator was redesigned as a probe. Update the reference stats to reflect this. |
10996:d48fda705f4d |
04-Aug-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
mem: Move trace functionality from the CommMonitor to a probe
This changeset moves the access trace functionality from the CommMonitor into a separate probe. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet.
This patch moves the dependency on Google's Protocol Buffers library from the CommMonitor to the MemTraceProbe, which means that the CommMonitor (including stack distance profiling) no long depends on it. |
10995:a114e2712642 |
04-Aug-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
mem: Redesign the stack distance calculator as a probe
This changeset removes the stack distance calculator hooks from the CommMonitor class and implements a stack distance calculator as a memory system probe instead. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet. |
10951:d4d836796511 |
31-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update switcheroo reference stats
The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change. |
10948:40526b73c7db |
30-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Bump stats after Minor switcheroo inclusion |
10947:6d86c48f7806 |
30-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Add Minor to the ARM full switcheroo tests
Add the Minor CPU to the RealView and RealView64 full switcheroo tests. |
10944:412eb87b1cfc |
30-Jul-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for clean eviction addition |
10937:a099d3ff2b1f |
30-Jul-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats to match current behaviour
Somehow this one seems to have slipped through. Perhaps non-determinism somewhere? |
10925:3a925f9856b1 |
18-Jul-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: x86: updates due to patch on vex |
10914:0ffd72d69092 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after decoupling draining from the SimObject hierarchy. This is expected since objects aren't drained in the exact same order as before. |
10912:b99a6662d7c2 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and calling drain()/drainResume() on the SimObjects. This is not ideal when non-SimObjects (e.g., ports) need draining since this means that SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need draining from SimObjects and the Python-side of the simulator to the DrainManager. The DrainManager now maintains a set of all objects that need draining. To reduce the overhead in classes owning non-SimObjects that need draining, objects inheriting from Drainable now automatically register with the DrainManager. If such an object is destroyed, it is automatically unregistered. This means that drain() and drainResume() should never be called directly on a Drainable object.
While implementing the new functionality, the DrainManager has now been made thread safe. In practice, this means that it takes a lock whenever it manipulates the set of Drainable objects since SimObjects in different threads may create Drainable objects dynamically. Similarly, the drain counter is now an atomic_uint, which ensures that it is manipulated correctly when objects signal that they are done draining.
A nice side effect of these changes is that it makes the drain state changes stricter, which the simulation scripts can exploit to avoid redundant drains. |
10904:532f423d6760 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
tests: Skip SPARC tests if the required binaries are missing
The full-system SPARC tests depend on several binaries that aren't generally available to the wider community. Flag the tests as skipped instead of failed if these binaries can't be found. |
10901:8cfa8dac39fe |
05-Jul-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: x86: update stats missed out on in preivous changeset |
10900:ac6617bf9967 |
04-Jul-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: update stale config.ini files, eio and few other stats. |
10892:bd37e25fb3b7 |
03-Jul-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling.
Needless to say, almost every regression is affected. |
10884:c60acdbdd6ad |
03-Jul-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only cache, for example for the instruction cache, or table-walker cache (not for x86). A number of checks are put in place in the code to ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only cache to explicitly ask for clean data. |
10855:117db3a0d78c |
26-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
arm, stats: Update stats to reflect reduction in misc reg reads |
10852:5b58b4cccfd7 |
26-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update MinorCPU regressions after accounting fix |
10848:e61f847e74fd |
23-May-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm, stats: Update stats to reflect changes to generic timer
The addition of a virtual timer affects stats in minor and o3. |
10830:bd8bf83de1f4 |
05-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats, arm: Update stats for missing FPEXC.EN check
Only one regression is affected. |
10827:7f5467f2f8b8 |
05-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect cache changes |
10813:c6189a9b8cd7 |
05-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bring regression stats in line with actual behaviour |
10812:bacaefeb126a |
30-Apr-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: arm: updates |
10811:e6b20e6b5cf9 |
29-Apr-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: x86: updates due to change in div latency |
10798:74e3c7359393 |
22-Apr-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update for previous changeset
Very small differences in IQ-specific O3 stats. |
10791:a80d2d716a53 |
20-Apr-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update a few stats from long O3 runs
Very small changes to iew.predictedNotTakenIncorrect and iew.branchMispredicts. Looks like similar updates were committed on April 3 (changeset 235ff1c046df), but only for the quick tests. |
10787:3c6a78d23507 |
14-Apr-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: x86: changes due to recent patches
The change in 20.parser is from new x87 instructions. The change to pc-o3-timing is not clear to me. It seems that this test might be invoking some undefined behavior. |
10778:235ff1c046df |
03-Apr-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent changesets. |
10765:ee0e03afd9da |
27-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Update stats for cache block alignment |
10754:02621b4f013b |
23-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Final reclassification of quick regressions
A few regressions were still considered long, but finished well within the 180 seconds. They are only a handful (mostly mcf in atomic). |
10753:48a72150f82c |
19-Mar-2015 |
Steve Reinhardt <stever@gmail.com> |
stats: update Minor stats due to PF bug fix
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs. |
10752:62b24818c8c6 |
19-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Recategorise regressions based on run time
This patch takes a first stab at recategorising the regression tests based on actual run times. The simple-atomic and simple-timing runs of vortex and twolf all finish in less than 180 s, and they are consequently moved from long to quick. All realview64 linux-boot regressions take more than 700 s, and they are therefore moved to long.
Later patches will rename quick to short, and further divide the regressions into short, medium and long. |
10751:11d4a587d43a |
19-Mar-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
test, arm: Add scripts to test checkpoints
Add a set of scripts to automatically test checkpointing in the regression framework. The checkpointing tests are similar to the switcheroo tests, but instead of switching between CPUs, they checkpoint the system and restore from the checkpoint again. This is done at regular intervals, typically while booting Linux.
The implementation is fairly straight forward, with the exception that we have to work around gem5's inability to restore from a checkpoint after a system has been instantiated. We work around this by forking off child processes that does the actual simulation and never instantiate a system in the parent process unless a maximum checkpoint count is reached (in which case we just simulate the system to completion in the parent).
Checkpoint testing is currently only enabled 32- and 64-bit ARM systems using atomic CPUs.
Note: An unfortunate side-effect of forking is that every new process will overwrite the stats and terminal output from the previous process. This means that the output directory only contains data from the last checkpoint. |
10742:cb77dfd5db54 |
19-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Bump timeout to 5 hours
Align with observed run-times just above 4 hours for some hosts. |
10737:9a0f26a90db9 |
09-Mar-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
tests: remove not maintained 20.eio-short detailed test |
10736:4433fb00fa7d |
09-Mar-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes to due to recent set of patches |
10727:67f3b26c65c5 |
07-Mar-2015 |
Steve Reinhardt <stever@gmail.com> |
stats: update eio stats
Minor differences apparently from recent changes |
10726:8a20e2a1562d |
02-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU. |
10720:67b3e74de9ae |
02-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios.
Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden. |
10710:9b71309d29f9 |
02-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Run regression timeout as foreground
Allow the user to send signals such as Ctrl C to the gem5 runs. Note that this assumes coreutils >= 8.13, which aligns with Ubuntu 12.04 and RHE6. |
10689:12632859858a |
11-Feb-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump the MemTest regression stats
Reflect changes in the tester behaviour. |
10688:22452667fd5c |
11-Feb-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
cpu: Tidy up the MemTest and make false sharing more obvious
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed.
The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work.
In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing. |
10655:b7ff344c3061 |
22-Jan-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect x86 table walker changes |
10649:104ef22a25f3 |
20-Jan-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Remove deprecated InOrderCPU tests
This patch removes the three MIPS and SPARC regressions that use the deprecated InOrderCPU.
This is the first step in completely removing the code from the tree, avoiding confusion, and focusing all development efforts on the MinorCPU. Brave new world. |
10645:cd95d4d51659 |
10-Jan-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes due to recent changesets. |
10639:469cf1ea40f5 |
07-Jan-2015 |
Gabe Black <gabeblack@google.com> |
stats: x86: Update stats for the CPUID change. |
10636:9ac724889705 |
04-Jan-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes due to recent changesets. |
10628:c9b7e0c69f88 |
23-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
10616:6d4da9dc90a1 |
23-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Add a regression for the stack distance calculator
Re-use the existing traffic generator regression, and enable the stack distance calculation in the comm monitor, along with the verification stack.
The traffic generator config is also tuned to not increase the run-time too much (and actually have some address re-use). |
10585:1c9d5d9417b3 |
02-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate |
10576:de2979ff873a |
02-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for o3 LSQ changes |
10560:dd04eb06ad42 |
24-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats after static analysis fixes
Fixing up the uninitialised values changes two of the x86 Linux boot regressions slightly. |
10549:6317351a288c |
21-Nov-2014 |
Gabe Black <gabeblack@google.com> |
x86: Update stats for the new Linux delay port. |
10540:45204db420c0 |
17-Nov-2014 |
Gabe Black <gabeblack@google.com> |
x86: Update the stats for the x86 FS o3 boot test. |
10535:4ccec5baf82c |
12-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump regressions to match latest changes
Updates after timezone hick-up and sorting of dictionary items in the SimObject. |
10530:533ec854b2f1 |
11-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes to x86 o3 fs and sparc fs regression tests. |
10528:a69d27a14460 |
06-Nov-2014 |
Marc Orr <morr@cs.wisc.edu> |
tests: A test program for the new mwait implementation.
This is a simple test program for the new mwait implemenation. It is uses m5threads to create to threads of execution in syscall emulation mode that interact using the mwait instruction.
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10526:0068ad93a67e |
06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ruby |
10524:fff17530cef6 |
06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. |
10519:7a3ad4b09ce4 |
06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby. |
10517:ba51f8572571 |
03-Nov-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of instruction differences. |
10516:cae494887847 |
30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm, tests: Forgot the system.terminal files for the new regressions. |
10515:bd7c2aa12122 |
30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm, tests: Add 64-bit ARM regression tests |
10513:ca4438b6e39a |
30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
tests: Update regressions for the new kernels and various preceeding fixes. |
10512:b423e1d0735e |
30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm, tests: Update config files to more recent kernels and create 64-bit regressions.
This changes the default ARM system to a Versatile Express-like system that supports 2GB of memory and PCI devices and updates the default kernels/file-systems for AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some platforms that are no longer supported have been pruned from the configuration files.
In addition a set of 64-bit ARM regressions have been added to the regression system. |
10488:7c27480a5031 |
20-Oct-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to previous mmap and exit_group patches. |
10452:be23c690f8c0 |
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Small bump of trailing stats
Somehow these seem to have been missed. |
10451:3a87241adfb8 |
11-Oct-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to x86, stale configs. |
10433:821cbe4a183b |
09-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Add DRAM power statistics to reference output |
10419:28b31101d9e6 |
28-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect ARM fixes
As a result of the fixes, the full-system dual-core ARM regressions are slightly changed. Hopefully this also means there will no longer be any discrepancies between the results observed on different hosts. |
10411:d96740732a61 |
21-Sep-2014 |
Steve Reinhardt <stever@gmail.com> |
stats: update t1000 stats for recent changes |
10410:2b1bb16fd3d0 |
21-Sep-2014 |
Steve Reinhardt <stever@gmail.com> |
stats: update eio stats for recent changes |
10409:8c80b91944c5 |
20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs. |
10406:3819b85ff21a |
20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Use more representative configs for ARM tests
This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher. |
10405:7a618c07e663 |
20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. |
10404:560aead2320f |
20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Add a memtest version using the ideal SnoopFilter
This patch adds a basic regression test for the snoop filter. |
10384:fa66d9c5e180 |
25-Aug-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
tests: automatically kill regressions that take too long
When GNU coreutils 'timeout' is available, limit each regression simulation to 4 hours. |
10369:cc10d6851778 |
12-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Minor update of Minor stats after uncacheable fix |
10352:5f1f92bf76ee |
03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches. |
10351:ee383b8e4d3f |
03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Use medium dataset for perlbmk regressions
This patch changes the perlbmk regression script from the large to the medium dataset to reduce the regression run time. For all ISAs and CPU models, the total perlbmk host CPU time with the large dataset is roughly 12 hours (constituting >30% of the total regression host time). There is, most likely, almost no added value in terms of code coverage for this rather excessive run time. |
10350:35241e33c38f |
03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
alpha: Stop using 'inorder' and rely entirely on 'minor'
This patch avoids building the 'inorder' CPU model for any permutation of ALPHA, and also removes the ALPHA regressions using the 'inorder' CPU. The 'minor' CPU is already providing a broader test coverage. |
10336:60dddc0a6f78 |
03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Use O3_ARM_v7a config for full-system ARM regressions
This patch changes the CPU configuration used for the full-system ARM regressions to increase the test coverage. Note that it is only the core configuration, and not the caches etc. |
10315:9e02c14446bb |
01-Sep-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to recent ruby and x86 changes Also updates many out of date config files. |
10300:ed3816dae6d5 |
01-Sep-2014 |
Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu> |
ruby: Fixes clock domains in configuration files
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain.
Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements.
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10261:dc198e224a85 |
28-Jul-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for the regressions using the minor CPU
Updating the stats to match the current behaviour. |
10260:384d554cea8c |
23-Jul-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
cpu: Minor CPU add regression tests for ARM and ALPHA
This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA. |
10258:23384aa97d85 |
19-Jul-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update for syscall DPRINTF change
Only printing one rather than two args for the ignored syscall warning means the count of register accesses has changed on a few runs. Oddly only Alpha Tru64 seems to have any ignored syscalls in the regression tests. |
10242:cb4e86c17767 |
22-Jun-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. |
10230:a2bb75a474fd |
24-May-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes due to recent o3 patch. |
10229:aae7735450a9 |
23-May-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: changes due to o3 cpu and ruby message buffer patches |
10222:d51e31eef415 |
12-May-2014 |
Steve Reinhardt <stever@gmail.com> |
tests: update t1000 & pc-switcheroo-full stats
committed reference config.json files too |
10221:cc6408469397 |
10-May-2014 |
Steve Reinhardt <stever@gmail.com> |
tests: update eio ref outputs for new stats
Also committed reference config.json files for the eio tests. |
10220:9eab5efc02e8 |
09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats for the fixes, and mostly DRAM controller changes |
10218:5a45f124a2f7 |
09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Reflect name change in DRAM tests
This patch reflects the recent name change in the DRAM TrafficGen tests and also tidies up the test directory. |
10196:be0e1724eb39 |
09-May-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arch: teach ISA parser how to split code across files
This patch encompasses several interrelated and interdependent changes to the ISA generation step. The end goal is to reduce the size of the generated compilation units for instruction execution and decoding so that batch compilation can proceed with all CPUs active without exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can accept 'split [output_type];' directives at the top level of the grammar and 'split(output_type)' python calls within 'exec {{ ... }}' blocks. This has the effect of "splitting" the files into smaller compilation units. I use air-quotes around "splitting" because the files themselves are not split, but preprocessing directives are inserted to have the same effect.
Architecturally, the ISA parser has had some changes in how it works. In general, it emits code sooner. It doesn't generate per-CPU files, and instead defers to the C preprocessor to create the duplicate copies for each CPU type. Likewise there are more files emitted and the C preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a dynamic list of source files coming out of the ISA parser. The changes to the SCons{cript,truct} files support this. In broad strokes, the targets requested on the command line are hidden from SCons until all the build dependencies are determined, otherwise it would try, realize it can't reach the goal, and terminate in failure. Since build steps (i.e. running the ISA parser) must be taken to determine the file list, several new build stages have been inserted at the very start of the build. First, the build dependencies from the ISA parser will be emitted to arch/$ISA/generated/inc.d, which is then read by a new SCons builder to finalize the dependencies. (Once inc.d exists, the ISA parser will not need to be run to complete this step.) Once the dependencies are known, the 'Environments' are made by the makeEnv() function. This function used to be called before the build began but now happens during the build. It is easy to see that this step is quite slow; this is a known issue and it's important to realize that it was already slow, but there was no obvious cause to attribute it to since nothing was displayed to the terminal. Since new steps that used to be performed serially are now in a potentially-parallel build phase, the pathname handling in the SCons scripts has been tightened up to deal with chdir() race conditions. In general, pathnames are computed earlier and more likely to be stored, passed around, and processed as absolute paths rather than relative paths. In the end, some of these issues had to be fixed by inserting serializing dependencies in the build.
Minor note: For the null ISA, we just provide a dummy inc.d so SCons is never compelled to try to generate it. While it seems slightly wrong to have anything in src/arch/*/generated (i.e. a non-generated 'generated' file), it's by far the simplest solution. |
10189:94d6ffac1e9b |
09-May-2014 |
Sascha Bischoff <sascha.bischoff@ARM.com> |
mem: Auto-generate CommMonitor trace file names
Splits the CommMonitor trace_file parameter into three parameters. Previously, the trace was only enabled if the trace_file parameter was set, and would be written to this file. This patch adds in a trace_enable and trace_compress parameter to the CommMonitor.
No trace is generated if trace_enable is set to False. If it is set to True, the trace is written to a file based on the name of the SimObject in the simulation hierarchy. For example, system.cluster.il1_commmonitor.trc. This filename can be overridden by additionally specifying a file name to the trace_file parameter (more on this later).
The trace_compress parameter will append .gz to any filename if set to True. This enables compression of the generated traces. If the file name already ends in .gz, then no changes are made.
The trace_file parameter will override the name set by the trace_enable parameter. In the case that the specified name does not end in .gz but trace_compress is set to true, .gz is appended to the supplied file name. |
10168:7d7f635e7447 |
22-Apr-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: updates for pc-switcheroo-full due to o3 smt fix |
10167:7ce13057a7c1 |
19-Apr-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to o3 smt fix + changes to one ruby regression config.ini file. |
10148:4574d5882066 |
23-Mar-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM controller. |
10124:46ccaf2cdef3 |
20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ruby config scripts These updates to ruby regression stats are due to renaming piobus to iobus and dropping piobus in the se mode. |
10120:f5ceb3c3edb6 |
20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: ruby: rename _cpu_ruby_ports to _cpu_ports |
10118:5e1f04b4d5e4 |
20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression. |
10117:37e333de580f |
20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: no piobus in se mode Piobus was recently added to se scripts for ruby so that the interrupt controller can be connected to something (required since the interrupt controller sends address range messages). This patch removes the piobus and instead, the pio port of ruby port will now ignore the range change messages in se mode. |
10093:9c55c0214404 |
24-Feb-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to c0db268f811b |
10092:c0db268f811b |
24-Feb-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: correct errors in changeset 4eec7bdde5b0 Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols. |
10091:d76312a74915 |
23-Feb-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ruby pio access handling |
10090:4eec7bdde5b0 |
23-Feb-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: route all packets through ruby port Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch. |
10072:fa5c8a8a7bab |
19-Feb-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Bump stats after FS config script update
This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions). |
10063:9595c7a1d837 |
16-Feb-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to branch predictor warming |
10040:48a9e57de52e |
27-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: update sparc fs stats |
10039:d1ddffa63fd4 |
27-Jan-2014 |
Steve Reinhardt <stever@gmail.com> |
stats: update eio stats for recent changes |
10038:7eccd14e2610 |
24-Jan-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: update stats for ARMv8 changes |
10036:80e84beef3bb |
24-Jan-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: update stats for cache occupancy and clock domain changes |
10013:2e9e2fb2fa71 |
10-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ruby |
10007:94d286db85c1 |
04-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: rename MESI_CMP_directory to MESI_Two_Level
This is because the next patch introduces a three level hierarchy. |
10003:459491344fcf |
03-Jan-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
config, x86: move kernel specification from tests to FSConfig.py
For some reason, the default x86 kernel is specified in tests/configs/x86_generic.py and not in configs/common/FSConfig.py, where the kernels for all the other ISAs are. This means that running configs/example/fs.py for x86 fails because no kernel is specified. Moving the specification over fixes this problem.
There is another problem that this uncovers, which is that going past the init stage (i.e., past where the regression test stops) fails because the fsck test on the disk device fails, but that's a separate issue. |
9998:4b872fdba3af |
26-Dec-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to bug fixed in mesi coherence protocol |
9988:0b2e590c85be |
26-Nov-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ticksToCycles() |
9980:cc02ad629b36 |
14-Nov-2013 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: suppress output on switcheroo tests
The output from the switcheroo tests is voluminous and (because it includes timestamps) highly sensitive to minor changes, leading to extremely large updates to the reference outputs. This patch addresses this problem by suppressing output from the tests. An internal parameter can be set to enable the output. Wiring that up to a command-line flag (perhaps even the rudimantary -v/-q options in m5/main.py) is left for future work. |
9978:81d7551dd3be |
01-Nov-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
9962:7aef35367a21 |
01-Nov-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump stats after shifting to SimpleMemory
Match stats with new regression configs. |
9961:1991dd858e47 |
01-Nov-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
test: Use SimpleMemory for atomic full-system tests
Keep it simple and use the SimpleMemory rather than the DRAM controller model for atomic full-system tests. |
9924:31ef410b6843 |
16-Oct-2013 |
Steve Reinhardt <steve.reinhardt@amd.com> |
test: update stats
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses. |
9922:4eec8250c38d |
15-Oct-2013 |
Steve Reinhardt <steve.reinhardt@amd.com> |
scons: fix minor update-ref bug in regressions
In the unusual case that regressions are run with --update-ref when there is no existing regression output, scons gets confused because it depends on stats.txt to trigger the update, but it has no indication that running the test will generate the stats.txt file. (In the typical case where stats.txt already exists, scons doesn't care about where it came from.)
It's easy to fix this just by adding the stats.txt file to the target list for the test action. |
9908:67c8fbe5d629 |
09-Oct-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump pc-simple-timing-ruby stats
This patch simply brings the stats for the pc-simple-timing-ruby regression up to date. The particular regression seems to give different results on different systems unfortunately, and this update reflects the current behaviour on zizzer. |
9901:13c5fea24be1 |
02-Oct-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
stats: Update x86 stats after x87 fixes
The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support. |
9885:afd9ea6101d9 |
28-Sep-2013 |
Steve Reinhardt <stever@gmail.com> |
tests: update reference outputs
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority. |
9871:c1b28ea22ff8 |
15-Sep-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: update sparc fs due to recent changes to memory class. |
9864:1ee14c8f6555 |
06-Sep-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: ruby: updates due to recent changes. |
9851:14e6caa5a1de |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Move ISA-independent tests to the NULL ISA
This patch simply takes a first step to use the NULL ISA build for tests that do not make use of a CPU. Most of the Ruby tests could go the same way, but to avoid duplicating a lot of compilation targets that will have to wait until Ruby is built as a library and linked in independently. |
9844:8c4c9bfd902c |
24-Aug-2013 |
Steve Reinhardt <stever@gmail.com> |
stats: update eio stats |
9842:d75f37065089 |
20-Aug-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: update ruby.stats, config.ini files for x86 fs test |
9841:69c158420c51 |
20-Aug-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: add option for number of transitions per cycle The number of transitions per cycle that a controller can carry out is a proxy for the number of ports that a controller has. This value is currently 32 which is way too high. The patch introduces an option for the number of ports and uses this option in the protocol files to set the number of transitions. The default value is being set to 4. None of the se regressions change. Ruby stats for the fs regression change and are being updated. |
9838:43d22d746e7a |
19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models.
The main reason for bundling them up is to minimise the changeset size. |
9835:cc7a7fc71c42 |
19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change. |
9827:f47274776aa0 |
19-Aug-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set.
A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain.
The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic.
The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. |
9826:014ff1fbff6d |
19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions.
The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1.
Going forward, options will be added to support the addition of multi-channel memory controllers. |
9803:86b426640960 |
02-Jul-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update a couple stats.txt The statistics for 30.eio-mp, pc-simple-timing-ruby tests are being updated to incorporate the changes due to recent patches. |
9802:eec242a5252d |
02-Jul-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update a couple of configs The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been updated correctly in the patch 6e6cefc1db1f. |
9797:9cd5f91e7a79 |
27-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index. |
9793:6e6cefc1db1f |
27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the ClockedObjects. As such, all clock information is moved to the clock domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock period, or derived domains that have a parent domain and a divider (potentially chained). For piece of logic that runs at a derived clock (a ratio of the clock its parent is running at) the necessary derived clock domain is created from its corresponding parent clock domain. For now, the derived clock domain only supports a divider, thus ensuring a lower speed compared to its parent. Multiplier functionality implies a PLL logic that has not been modelled yet (create a separate clock instead).
The clock domains should be used as a mechanism to provide a controllable clock source that affects clock for every clocked object lying beneath it. The clock of the domain can (in a future patch) be controlled by a handler responsible for dynamic frequency scaling of the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For the System a default SrcClockDomain is created. For CPUs that run at a different speed than the system, there is a seperate clock domain created. This domain incorporates the CPU and the associated caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual functions or multiplications are needed when calling clockPeriod. Instead, the clock period is pre-computed when any changes occur. For this to be possible, each clock domain tracks its children. |
9792:c02004c2cc5b |
27-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add a BaseSESystem builder for re-use in regressions
This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point).
The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration.
Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same. |
9790:ccc428657233 |
27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign clocks to the system during instantiation.
As part of this change, the default clock in the System class is removed and whenever a system is instantiated a system clock value must be set. A default value is provided for the command-line option.
The configs and tests are updated accordingly. |
9788:5558ee8dd7d9 |
27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the introduction of clock domains. |
9787:562bb3ea2b69 |
27-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
tests: Prune 00.gzip from the regressions
This patch prunes the 00.gzip regressions with the main motivation being that it adds little (or no) coverage and requires a substantial amount of run time.
A complete regression run, including compilation from a clean repo, is almost 20% faster(!). |
9781:2bddf82f610b |
27-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Identify runs that fail and runs with stats differences
This patch changes the regression script such that it is possible to identify the runs that fail with an exit code, and those that finish with stats differences. The ones that truly fail are reported as FAILED, and those that finish with changed stats as CHANGED.
The yellow colour has been reclaimed from the skipped regressions and is now used for the changed ones. With no obvious good option left the skipped ones are now in cyan.
While I was editing the script I also bumped any occurence of M5 to gem5. |
9776:5fe711f40d18 |
25-Jun-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to stat collection in ruby |
9772:1e364e47b73c |
24-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump x86 stats
This patch bumps the x86 stats to reflect the recent fixes. |
9748:4f2a448d3896 |
10-Jun-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates due to changes to ruby Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated. |
9741:3db869bbcdd1 |
08-Jun-2013 |
Steve Reinhardt <stever@gmail.com> |
Updating EIO regression reference outputs for new stats. |
9729:e2fafd224f43 |
30-May-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate. |
9728:7daeab1685e9 |
30-May-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations to better reflect what memory they are based on. The speed and interface width is now part of the name, and also the alias that is used to select them on the command line.
Some minor changes are done to the actual parameters, to better reflect the named configurations. As a result of these changes the regressions change slightly and the stats will be bumped in a separate patch. |
9702:094d0280e481 |
21-May-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86, regressions: updates stats This is due to op class, function call, walker patches. |
9698:db85c5348a96 |
21-May-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
stats: updates statistics for ruby regressions |
9680:217bdd9a3ad9 |
28-Apr-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Added memory type to t1000 regression
This patch adds the memory type parameter to the t1000 regression. |
9674:d35bd171cf2a |
23-Apr-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: regressions: add switcher full test |
9672:4a4294822ec5 |
23-Apr-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86, stats: updates due to lret bugfix |
9665:6dbdeee787cc |
22-Apr-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a mem-type command-line option. Behind the scenes, this option is treated much like the cpu-type, and a similar framework is used to resolve the valid options, and translate the short-hand description to a valid class.
The regression scripts are updated with a hardcoded memory class for the moment. The best solution going forward is probably to get the memory out of the makeSystem functions, but Ruby complicates things as it does not connect the memory controller to the membus. |
9661:18755c467503 |
22-Apr-2013 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: Update stats for O3 switching fix. |
9654:64b653b3d72f |
22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
tests: Add support for testing KVM-based CPUs
This changeset adds support for initializing a KVM VM in the BaseSystem test class and adds the following methods in run.py:
require_file -- Test if a file exists and abort/skip if not. require_kvm -- Test if KVM support has been compiled into gem5 (i.e., BaseKvmCPU exists) and the KVM device exists on the host. |
9649:c717bd5e0a1d |
22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Enable support for triggering a sim panic on kernel panics
Add the options 'panic_on_panic' and 'panic_on_oops' to the LinuxArmSystem SimObject. When these option are enabled, the simulator panics when the guest kernel panics or oopses. Enable panic on panic and panic on oops in ARM-based test cases. |
9643:745e42ffcc80 |
19-Apr-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for ldr_ret_uop (changeset 35198406dd72)
This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72. |
9636:531a176f863d |
16-Apr-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump the vortex stats to match latest behaviour
This patch bumps the stats for the failing vortex o3 regression. |
9635:6d4158ff7b82 |
09-Apr-2013 |
Joel Hestness <jthestness@gmail.com> |
stats: Bump Ruby stats for new changesets
The new changeset that can reorder Ruby profilers will cause the ruby.stats files to reordered statistics (the point of the patch). Update the references to ensure that these changes are reflected in regressions. |
9625:47591444a7c5 |
29-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: updates due to changes to o3 cpu, x86 memory map |
9621:e63744697af3 |
28-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update eio stats due to cache latency fix |
9620:89aa34e10625 |
27-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update due to cache latency fix |
9615:daa8a14ec85e |
26-Mar-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes are minimal (in the <0.01% range). |
9613:0245dca0f2a2 |
26-Mar-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer. |
9605:b645e31a97b3 |
22-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: updates to config.ini for ruby tests |
9583:c1a5a20cc1fa |
11-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: x86: stats updates due to new x87 insts |
9578:49b40999f4a2 |
06-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: stats updates due to no physmem in ruby |
9577:91cac7c9c636 |
06-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. |
9575:6c4d6fdf3644 |
04-Mar-2013 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: update patches for branch predictor and fetch updates. |
9568:cd1351d4d850 |
01-Mar-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats. |
9558:c77795f711a3 |
19-Feb-2013 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: more zizzer stats fun |
9536:8149223cd7db |
15-Feb-2013 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: update regressions for o3 changes in renaming and translation. |
9521:1cd02decbfd3 |
15-Feb-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system
m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above.
This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications:
* changeToTiming and changeToAtomic are no longer needed, so they have been removed.
* changeMemoryMode is only used internally, so it is has been renamed to be private.
* switchCpus requires a reference to the system containing the CPUs as its first parameter.
WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus(). |
9510:921d858c5bc7 |
10-Feb-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats due to changes to ruby |
9490:e6a09d97bdc9 |
31-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default. |
9489:172dbcb74a0e |
31-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward.
The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration. |
9482:798c2cec8e37 |
28-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3
This patch bumps the stats for 20.parser for ARM o3-timing to reflect a namechange of the branch predictor. |
9481:b0fa6b872f40 |
24-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables. |
9474:23c3e1c0e9e4 |
15-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86 regressions: updates due to new instructions and cpuid |
9469:d2eeba87c4a8 |
14-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats due to changes in ruby obj hierarchy |
9463:13e68ad8db54 |
14-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Bump failing x86 regression stats
This patch bumps the stats of mcf and twolf for the o3 CPU such that the regressions pass. |
9459:8ca90cef0183 |
08-Jan-2013 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: update stats for previous six changes |
9449:56610ab73040 |
07-Jan-2013 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: update stats for previous changes. |
9447:156f74caf0d4 |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process.
The in-order CPU model was not included in any of the tests as it does not support CPU handover. |
9435:e7c4f86ffa40 |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
tests: Update the ignore regexps to reflect the M5->gem5 name change |
9408:10a84dceab25 |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge.
The change is needed to allow interleaved memory controllers in the system. |
9402:f6e3c60f04e5 |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
cpu: Add support for protobuf input for the trace generator
This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor.
A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch. |
9401:9f0918fbb07f |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
tests: Add support for skipping tests, skip EIO tests if not enabled
The EIO tests depend on the EIO support from the "encumbered" repository, which means that they are not normally built with gem5. This causes all EIO related tests to fail, which is both annoying and confusing. This patch addresses this by adding support for skipping tests if certain conditions (e.g., the presence of a SimObject) can not be met. It introduces the following Python functions that can be called from within a test case:
* skip_test -- Skip a test and optionally print why the test was skipped.
* has_sim_object -- Test if a SimObject exists.
* require_sim_object -- Test if a SimObject exists and skip, or optionally fail, the test if not.
Additionally, this patch updates the EIO tests to check for the presence of EioProcess. |
9398:6a348f61220c |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add tracing support in the communication monitor
This patch adds packet tracing to the communication monitor using a protobuf as the mechanism for creating the trace.
If no file is specified, then the tracing is disabled. If a file is specified, then for every packet that is successfully sent, a protobuf message is serialized to the file. |
9393:ebabcce1880f |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update DRAM regression stats to match new config
This patch updates the regression stats to reflect the change in the traffic gen configuration. |
9392:bcb7441ae83c |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Reduce DRAM controller regression traffic rate
This patch changes the traffic generator period such that it does not completely saturate the DRAM controller and create an ever-growing backlog in the queued port.
A separate patch updates the stats. |
9384:877293183bdf |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU. |
9381:ffec48040ac1 |
07-Jan-2013 |
Ali Saidi <Ali.Saidi@ARM.com> |
tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it. |
9380:e428871da248 |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
tests: Create base classes to encapsulate common test configurations
Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration.
The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation.
* BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations.
* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible.
Architecture specific implementations are provided for ARM, Alpha, and X86. |
9378:36ed6d4654bb |
04-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: stats update due to decoder changes |
9373:26ba525347fe |
30-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86 regressions: stats update due to new x87 instructions |
9370:5172ffaf6e30 |
12-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
arm regressions: updates to config.ini, terminal files |
9367:0a034df1c6a7 |
11-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: stats update due to stats from ruby prefetcher |
9361:5b6087e0750f |
06-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regression test: update a couple of config.ini files |
9355:0fea324c832c |
10-Nov-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: stats update due to ruby functional access patch |
9348:44d31345e360 |
02-Nov-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
update stats for preceeding changes |
9324:8650f0c53db5 |
31-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration. |
9323:e22374824171 |
31-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the simple-atomic-mp regression configuration. |
9322:01c8c5ff2c3b |
30-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions. |
9321:7f0464326b2b |
30-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the regressions instead of declaring different, but very similar, configurations in the different scripts.
The patch also changes the default L2 configuration to match what it used to be for the fs and se scripts (until the last patch that updated the regressions to also make use of the cache config). The MSHRs and targets per MSHR are now set to a more realistic default of 20 and 12, respectively.
As a result of both the aforementioned changes, many of the regression stats are changed. A follow-on patch will bump the stats. |
9320:e71f71ce233a |
27-Oct-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats for ruby fs test |
9315:2e00867b5001 |
26-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts. |
9314:63e7cfff4188 |
25-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace. |
9312:e05e1b69ebf2 |
25-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller. |
9311:227d19399b51 |
25-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of SimpleMemory for all regressions that involve the o3 or inorder CPU, or are full system (in other words, where the actual performance of the memory is important for the overall performance).
Moving forward, the solution for FSConfig and the users of fs.py and se.py is probably something similar to what we use to choose the CPU type. I envision a few pre-set configurations SimpleLPDDR2, SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on this part is welcome.
This patch changes plenty stats and adds all the DRAM controller related stats. A follow-on patch updates the relevant statistics. The total run-time for the entire regression goes up with ~5% with this patch due to the added complexity of the SimpleDRAM model. This is a concious trade-off to ensure that the model is properly tested. |
9310:aa7bf10e822a |
25-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch.
The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions.
As only regressions that shared the same cache configuration are updated, no regressions are affected. |
9308:f634a34f2f0b |
23-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in the DMA port. |
9306:d6bca167cee4 |
23-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
stats: Update t1000 stats to match recent changes
This patch brings the t1000 stats up to date. |
9304:b4bd51f8b7a0 |
16-Oct-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats for eio tests |
9303:2caaf1da7237 |
15-Oct-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
regressions: update stats due to change to ruby memory system |
9289:a31a1243a3ed |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. |
9288:3d6da8559605 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency.
The stat blocked_cycles that actually counter in ticks is now updated to count in cycles.
As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions. |
9287:4482cfb36c51 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update memtest stats after setting clock
This patch updates the memtest stats to reflect the addition of a clock other than the default one. |
9286:f610f5942ded |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz, similar to the CPUs in the other regressions. This is useful as the caches will adopt the same clock as the CPU. The bus clock rate is scaled accordingly, and the L1-L2 bus is kept at the CPU clock while the memory bus is at half that frequency.
A separate patch updates the affected stats. |
9285:9901180cd573 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches. |
9283:490958b032d6 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats for use of two-level builder
This patch updates the name of the l2 stats. |
9282:ac627fdc8991 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween.
The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock.
The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache. |
9276:a5ede748a1d9 |
02-Oct-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression Tests: Update statistics |
9265:8fe936e937bd |
25-Sep-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: update stats for bp and squash fixes. |
9263:066099902102 |
25-Sep-2012 |
Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> |
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path. |
9247:73c3eb0dd733 |
24-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats for twosys-tsunami after setting CPU clock
This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick. |
9246:ab0f995552fc |
24-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Regression: Set the clock for twosys-tsunami CPUs
This patch merely adds a clock other than the default 1 Tick for the CPUs of both the test system and drive system for the twosys-tsunami regression.
The CPU frequency of the driver system is choosed to be twice that of the test system to ensure it is not the bottleneck (although in this case it mostly serves as a demonstration of a two-system setup), |
9244:4672c12307a7 |
21-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
SimpleDRAM: A basic SimpleDRAM regression |
9242:256143419b40 |
21-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
TrafficGen: Add a basic traffic generator regression
This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly. |
9229:65f927bda74d |
18-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory. |
9223:be1c1059438b |
13-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Remove the reference stats that are no longer present
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU. |
9213:5cab5448909c |
11-Sep-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86 Regressions: Update stats due to register predication |
9207:ee27d0bf7353 |
10-Sep-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: Updates due to changes to Ruby memory controller |
9204:09d63f1e3559 |
10-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Ruby: Bump the stats after recent memory controller changes
This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense. |
9199:2a5516167688 |
10-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change in PIO and PCI latency. |
9183:8ee71266699b |
05-Sep-2012 |
Joel Hestness <hestness@cs.wisc.edu> |
stats: Update Ruby regressions for memory controller fix |
9177:a0f5d867151b |
28-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Checker: Bump the realview-o3-checker regression
This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch. |
9169:89acf0b76858 |
25-Aug-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: updates ruby.stats due to change in virtual network |
9164:d112473185ea |
22-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them.
The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split).
As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up. |
9150:a2370fa5c793 |
15-Aug-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: Update stats for syscall emulation Linux kernel changes. |
9137:d164268bc35c |
30-Jul-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update |
9136:2481b3ef5385 |
28-Jul-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: fix some miss-committed changes from the icache change |
9134:275232ad377d |
27-Jul-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: update stats for icache change not allowing dirty data |
9127:6e40da21a0e6 |
23-Jul-2012 |
Steve Reinhardt <stever@gmail.com> |
test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs were clobbered. |
9126:6521b0f1db5b |
23-Jul-2012 |
Steve Reinhardt <stever@gmail.com> |
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using a binary compiled without eio, resulting in broken refernce outputs. |
9125:65423863d963 |
22-Jul-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: Update stats due to changes to x86 cpuid instruction |
9123:281b3ac0e0a1 |
21-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Regression: Fix topologies path in failing pc-simple-timing-ruby
This patch updates the path to the Ruby topologies and thus fixes a failing regression. |
9120:48eeef8a0997 |
12-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses. |
9118:fdfe72857f89 |
12-Jul-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: update ruby.stats file |
9113:9a72589ce4fd |
11-Jul-2012 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: ruby stat additions and config changes |
9096:8971a998190a |
09-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes. |
9079:9a244ebdc3c9 |
29-Jun-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Update stats for RAS and LRU fixes. |
9067:d0d9d10b3930 |
11-Jun-2012 |
Marc Orr <marc.orr@gmail.com> |
Regression: Fix some bugs in simple-timing-mp-ruby.py. |
9055:38f1926fb599 |
05-Jun-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
all: Update stats for memory per master and total fix. |
9039:9a22621c741c |
04-Jun-2012 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the CPUID change. |
9036:6385cf85bf12 |
31-May-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect.
The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses.
A bit of minor tidying up has also been done. |
9035:1e783db0f3af |
09-May-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Fix stats to match output after changeset 8800b05e1cb3
This patch updates the stats for parser to be aligned with the most up-to-date behaviour. Somehow the wrong results got committed as part of 8800b05e1cb3 (see details below) when fixing the no_value -> nan stats.
changeset: 8983:8800b05e1cb3 user: Nathan Binkert <nate@binkert.org> summary: stats: update stats for no_value -> nan |
9027:1f2568933bc5 |
27-May-2012 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add a 32 bit hello world test binary. |
9013:afa278317136 |
22-May-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
X86 Regression: update stats due to cc register split |
9005:f681719e2e99 |
10-May-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: update stats for clock frequency fix. |
8983:8800b05e1cb3 |
09-May-2012 |
Nathan Binkert <nate@binkert.org> |
stats: update stats for no_value -> nan Lots of accumulated older changes too. |
8977:42ea79acf35f |
04-May-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: Move x86 fs ruby simulation from quick to long |
8974:fe542ba8a878 |
30-Apr-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: Stats update for X86 Ruby FS test The kernel originally used to generate the stats is different from the one at use on zizzer. This patch updates the stats with the correct kernel in use. |
8968:6d11b01e2c53 |
25-Apr-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regression: Add a test for x86 timing full system ruby simulation |
8963:91a6f8f07074 |
24-Apr-2012 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the slightly changed TLB behavior. |
8947:217fbc57df05 |
14-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Regression: Add ANSI colours to highlight test status
This patch adds a very basic pretty-printing of the test status (passed or failed) to highlight failing tests even more: green for passed, and red for failed. The printing only uses ANSI it the target output is a tty and supports ANSI colours. Hence, any regression scripts that are outputting to files or sending e-mails etc should still be fine. |
8944:d062cc7a8bdf |
12-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update with use of std::map for ordered iteration in Ruby
This patch updates the stats to reflect the changes due to the use of std::map instead of the hash map order-dependent iteration in Ruby. |
8940:a48540069b8d |
06-Apr-2012 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: ruby random tester and hammer stats updates |
8933:2727a5a0aadc |
06-Apr-2012 |
Brad Beckmann <Brad.Beckmann@amd.com> |
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality |
8931:7a1dfb191e3f |
06-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range.
All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables.
Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. |
8920:99083b5b7ed4 |
28-Mar-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: Change the way options are added I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required. |
8911:4da2ea94319f |
21-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for IT and conditional branch changes |
8893:e29c604a2582 |
09-Mar-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Update stats for CBNZ fix. |
8891:b4249e884de4 |
09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for valgrind fix and replace config.inis which are out of date. |
8889:2e38fd9937a9 |
09-Mar-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support only at this point. |
8883:c92153af04ac |
09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
cache: Allow main memory to be at disjoint address ranges. |
8882:87cafa076695 |
08-Mar-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Fix the SPARC fs regression by adding a call to createInterruptController. |
8880:b5d80698c948 |
06-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and bzip2 regressions for ARM o3-timing. This patch merely updates the statistics to reflect these changes. |
8876:44f8e7bb7fdf |
02-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the interrupt controller is created for the cases where it is needed, i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number of the regression scripts. |
8875:ad681c92b07d |
02-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem moved in the object hierarchy and is now under system.realview. |
8859:c69a4493a430 |
29-Feb-2012 |
Steve Reinhardt <stever@gmail.com> |
EIO: update stats (mostly order change, some renames) |
8846:2eaf1809c6c6 |
14-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Script: Fix the scripts that use the num_cpus cache parameter
This patch merely removes the use of the num_cpus cache parameter which no longer exists after the introduction of the masterIds. The affected scripts fail when trying to set the parameter. Note that this patch does not update the regression stats. |
8844:a451e4eda591 |
13-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
bp: fix up stats for changes to branch predictor |
8839:eeb293859255 |
13-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port.
Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. |
8838:6a859084ee92 |
12-Feb-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
tests: fix diff-out script for op/inst stat changes. |
8835:7c68f84d7c4e |
12-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: update stats for insts/ops and master id changes |
8833:2870638642bd |
12-Feb-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions. |
8830:e46277f4b516 |
12-Feb-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regressions: Update stats due to change in MESI protocol |
8825:23b349d77ac1 |
10-Feb-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Regressions: Update stats due to O3 CPU changes |
8808:8af87554ad7e |
31-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository. |
8807:35e77c938919 |
29-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Yet another merge with the main repository. |
8802:ef66a9083bc4 |
28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make both SE and FS tests available all the time. |
8801:1a84c6a81299 |
28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make SE vs. FS mode a runtime parameter. |
8799:dac1e33e07b0 |
28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with the main repo. |
8744:cf8fb1aa1b30 |
09-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Configs: Use connectAllPorts to connect ports for simple-timing-ruby. |
8732:fd510b6e124d |
30-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Ruby: Connect system port in Ruby network test
This patch moves the connection of the system port to create_system in Ruby.py. Thereby it allows the failing Ruby test (and other Ruby systems) to run again. |
8728:2e560ea41774 |
28-Jan-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
X86 Regressions: Update stats due to introduction of TSO |
8721:ba2d2b37e534 |
25-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: Update stats for final tick and memory bandwidth patches |
8713:2f1a3e335255 |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities.
In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time. |
8706:b1838faf3bcc |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy.
The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy |
8705:ab0d7b7d9989 |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Ruby: Change the access permissions for MOESI hammer
Regression statistics update. |
8701:a33fd5964e66 |
16-Jan-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
stats: undo parser change from initparam change |
8679:f72bbe6b13fb |
10-Jan-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
MOESI Hammer: Update regression test output |
8673:9297bba002c0 |
10-Jan-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
X86 Regressions: Update stats due to fence instruction |
8660:b68ae43bc806 |
09-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: Update stats for ARM init param changes. |
8639:91ec198c54ee |
01-Dec-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: updated hammer memtest and rubytest outputs |
8632:7d289398506d |
01-Dec-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
imported patch ext/stats_updates.patch |
8631:8c038d4cd210 |
01-Dec-2011 |
Chander Sudanthi <chander.sudanthi@arm.com> |
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. |
8625:b44e7f5851a1 |
30-Nov-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
SPARC: update SE stats for FP fix |
8622:3553934a5594 |
28-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Update the FS stats for the recent FP fix. |
8616:8b532495bf80 |
17-Nov-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture. |
8613:712d8bf07020 |
05-Nov-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Tests: Update stats due to addition of fence microop |
8599:30d0e4c249b5 |
22-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: fix spurious scons "Error 1" messages
Turns out these are due to diff reporting that files acutally differed via a non-zero exit code. |
8554:e6f58919f7d3 |
17-Sep-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
MIPS: Fix regressions tests |
8546:b80783571492 |
13-Sep-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
O3: Update stats for new ordering fix. |
8540:66b311535265 |
09-Sep-2011 |
Gabe Black <gblack@eecs.umich.edu> |
MIPS: Update MIPS stats for cleaned up operand checks. |
8528:1f95c9a0bb2f |
19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add some MP regressions and clean up the disk images and kernels a bit |
8521:7ab22a73bda1 |
19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
StoreSet: Update stats for store-set clearing |
8517:684ea9e5cd96 |
19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Update stats for LSQ changes. |
8504:2d43dceb2807 |
14-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add an X86_FS o3 regression. |
8501:fe516fba6fc3 |
14-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Small update to stats for change to x86 inst flags. |
8498:22a15643e2ca |
09-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SCons,tests: Tell scons about pc-o3-timing regressions. |
8496:cf2eb466f74d |
09-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update stats for the end of macroop O3 fix. |
8494:0ef219f1d8ca |
09-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update stats for the recent O3 interrupt change. |
8492:1ad244a20877 |
08-Aug-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. |
8490:081ce5ab92ca |
07-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update stats for the previous change. |
8488:30b858787c74 |
07-Aug-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update the stats after the uninitialized branch predictor variable fix. |
8482:353abb676fa2 |
02-Aug-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Scons: Drop RUBY as compile time option. This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled. |
8480:f22c829848a1 |
31-Jul-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update stats for the recent fix to fetch. |
8473:9b48b795bfc5 |
15-Jul-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder-fs: temp. regression removal remove this regression till the fix for the hwrei instruction is put in |
8470:849afe8502c6 |
15-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for better miscreg support for MP configurations. |
8464:2a04edb07407 |
10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Update stats for fetch and bp changes. |
8451:5771ddbe5f1e |
05-Jul-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add a config for an FS regression on O3. |
8441:49e0034e2559 |
03-Jul-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update stats for the x86 store fault fix. |
8438:4e386e993ae8 |
30-Jun-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
Regression: Updates regression outputs for Ruby memtest This patch updates the regression outputs for Ruby memtest. This was required because of the changes carried out by the addition of functional access support to Ruby. |
8436:5648986156db |
30-Jun-2011 |
Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> |
Ruby: Add support for functional accesses This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. |
8431:00766f5b8177 |
20-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: sparc: add 02.insttest regression |
8430:f0978919d459 |
20-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: sparc: add hello world regression - add InOrderCPU compile option to SPARC - add hello regression for SPARC |
8428:020248dd406f |
20-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed. |
8427:f12d1cd32cc7 |
20-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: alpha-hello regression update |
8423:32613e8dc239 |
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: update eon regr w/eon info previous commit copied over O3 stats, this one puts the inorder ones in the right place |
8422:82989a67f73d |
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: add 10.linux-boot regression |
8421:46f5b8edf1a4 |
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: add eon regression |
8420:8e1f305e6d3a |
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: update SE regressions |
8397:7cd61d925338 |
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: make InOrder CPU FS compilable/visible make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile |
8348:7a32aa3acd72 |
12-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
sparc: update long regressions |
8347:ac4da9f8ea80 |
10-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
sparc: update o3 regressions |
8343:ce61b7a13407 |
10-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
sparc: update simple cpu regressions use stats file generated by zizzer |
8322:19949c6de823 |
23-May-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
config: tweak ruby configs to clean up hierarchy
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues.
1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first.
2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.
3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. |
8317:7f106d0bd638 |
23-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Update stats for minor O3 changes below. |
8306:fb0e525008c5 |
13-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix up stats for previous changes to condition codes |
8288:3824fbc8ed9a |
04-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update ARM_FS stats for mp changes |
8279:e169269a1829 |
04-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3/ARM: Update stats for recent changes. |
8264:dba41dbef071 |
28-Apr-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: updates after changing ruby network bandwidth |
8252:b02bca5aed04 |
25-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
stats: update 20.parser o3 now that it works. realview-o3 works too. |
8249:6e368a935ac0 |
22-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
tests: updates for stat name change |
8241:ee4e795343bf |
19-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
tests: update stats for name changes |
8217:cb1e137ac35e |
12-Apr-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix stats for ARM_SE checkpoint restore fix.
Register reads/writes done in startup() count against the stats while they don't count if done in initState(). |
8213:54a65799e4c1 |
04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for default inclusion of CF adapter. |
8210:20362a3a1540 |
04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for previous changes. |
8200:5806937a7c67 |
04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Update stats for memory order violation checking patch. |
8182:832ae3727c2b |
27-Mar-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: update reference outputs for ruby cache index change
MOESI_CMP_token is the only protocol that showed noticeable stats differences. |
8150:d062791aad69 |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update stats for the previous changes and add ARM_FS/O3 regression. |
8141:ce34f14c1f43 |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Update the statistics for rfe patch. |
8135:bb2d04f0b8fb |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Update regressions for mem block caching change. |
8134:b01a51ff05fa |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.
This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. |
8130:2af262e73961 |
17-Mar-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
X86: Update the stats for parser on x86 O3. |
8129:e4b508942ecb |
16-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats for gzip on x86 O3. |
8128:6c9b532da0a6 |
12-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Regressions: Move the X86_FS regressions to "quick" instead of "long". |
8120:e4257cde2d79 |
04-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SCons: Turn some scons variables into command line options. |
8104:0dcd19617556 |
02-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the x86 o3 hello world regression. |
8097:a314f5c2caa0 |
27-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update X86_FS stats. |
8095:5651f447e601 |
27-Feb-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: bzip2 regression update |
8087:3be28ebdb07f |
23-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: MOESI_hammer memtest updates |
8082:03ee2388ea9d |
23-Feb-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: add 00.gzip and 60.bzip2 regression tests |
8078:9dc17725f795 |
23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update regression tests for preceeding changes. |
8061:08e91664adac |
23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems. |
8047:ec39f497eadf |
18-Feb-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder: regr-update: reduce dynamic mem. use to speedup sims previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue) |
7972:42f772dc5a96 |
13-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the improved branch detection/prediction. |
7970:3e00a91c33b4 |
13-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats now that the dest reg isn't read unnecessarily to set flags. |
7968:e64e90b862a7 |
13-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the reduced register reads. |
7960:68a5b8bba293 |
12-Feb-2011 |
Korey Sewell <ksewell@umich.edu> |
inorder:regress: host-inst-rate improved ~58% there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM) |
7951:6548721032fa |
11-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Update the statistics for vnc patch. |
7939:215c8be67063 |
08-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regess: protocol regression tester updates |
7938:685719afafe6 |
08-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
memtest: due to contention increase, increased deadlock threshold |
7935:cb7d946d4211 |
07-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Re update stats. |
7934:0a6e85d5b411 |
07-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Back out broken update. |
7927:2c2dc567a450 |
07-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add stats for the new x86 fs regressions. |
7926:38ade63ef775 |
07-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add scripts to support X86 FS configurations in the regressions. |
7923:05f52a716144 |
07-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: Regression Tester output updates |
7893:44522e30d358 |
05-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add o3 regressions in SE mode.
Exclude bzip2 for now. It works, it just takes too long to run. |
7892:4f5911e3206a |
04-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update ruby stats for stupd change. |
7890:459db0aebcf7 |
04-Feb-2011 |
Korey Sewell <ksewell@umich.edu> |
imported patch regression_updates |
7876:189b9b258779 |
03-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches. |
7873:3b9ea4da3efb |
02-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update the x86 stats to reflect changing stupd to a store and update. |
7860:32b6354d2ae6 |
18-Jan-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM/O3: Add regressions for ARM w/ O3 CPU. |
7859:535cc70e8663 |
18-Jan-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Update stats for previous set of patches. |
7838:696063d6ed04 |
15-Jan-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Update stats for the call r15 as source change. |
7836:a82dcad2bc18 |
13-Jan-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Regression Tests: Update the output for MESI_CMP_directory This patch updates the output for regression tests that are carried out on MESI_CMP_directory protocol. The changes made to the protocol in order to remove the bugs present result in regression failure for the 60.rubytest. Since the earlier protocol was incorrect, so we certainly cannot relay on the earlier reference output. Hence, the update. |
7785:7506ba7f2cdb |
07-Dec-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
Stats: Fix stats for cumulative flags change. |
7765:634d88f0dbd4 |
15-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update the O3 fetch stats for SPARC. |
7761:50d219ed2a59 |
15-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
Regressions: Update regressions for SIMD opclass changes |
7755:5c374c1e0075 |
15-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update regressions for CLCD and KMI additions |
7740:3155a9ccb66b |
10-Nov-2010 |
Ali Saidi <saidi@eecs.umich.edu> |
Update EIO regressions for last set of patches |
7736:f61e079ad05e |
08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update SE stats for TLB stats additions |
7735:a1a85250e897 |
08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add full-system regressions |
7726:0d9de7394e38 |
08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads. |
7721:9d60c5339ae5 |
31-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Ref output: Update refs for PCState change. |
7688:ad9041185274 |
22-Sep-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes. |
7686:e44757c62695 |
22-Sep-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
diff-out: clean up options Make diff-out sort stats changes by percentage by default, with '-a' to use current alpha sort (instead of requiring '-p' to sort by percentage). Other minor options cleanup too. |
7685:9782e93eeb63 |
22-Sep-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: print if output files match Add '-s' flag to diff command generating outdiff file so we have positive confirmation when outputs match. |
7670:f6e808dd36af |
09-Sep-2010 |
Steve Reinhardt <stever@gmail.com> |
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU. |
7647:46054caaf8b6 |
25-Aug-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update regression tests for ldr/str microcode changes. |
7617:aca917ca1ad5 |
23-Aug-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ALPHA: The previous O3 patch causes a slight stats change with fullsys. |
7570:417ef5d444bd |
20-Aug-2010 |
Brad Beckmann <Brad.Beckmann@amd.com> |
regress: Regression tester updates
Regression tester updates required by the following patches:
brad/moved_python_protocol_files: config: moved python protocol config files brad/ruby_options_movement: config: reorganized how ruby specifies command-line options brad/config_token_bcast: ruby: added token broadcast config params to cmd options brad/topology_name: config: Added the topology description to m5 config.ini brad/ruby_system_names: config: Improve ruby simobject names brad/consolidated_protocol_stats: slicc: Consolidated the protocol stats printing brad/ruby_request_type_ostream_fix: ruby: Added ruby_request_type ostream def to libruby.hh brad/memtest_dma_extension: memtest: Memtester support for DMA brad/token_dma_lockdown_fix: MOESI_CMP_token: Fixed dma persistent lockdown bugs brad/profile_generic_mach_type: ruby: Reincarnated the responding machine profiling brad/network_msg_consolidated_stats: ruby: Added consolidated network msg stats brad/bcast_msg_profiling: ruby: Added bcast msg profiling to hammer and token brad/l2cache_profiling_fix: ruby: Fixed L2 cache miss profiling brad/llsc_ruby_m5_fix: ruby: fix ruby llsc support to sync sc outcomes brad/ruby_latency_fixes: ruby: Reduced ruby latencies brad/hammer_l2_cache_latency: ruby: Updated MOESI_hammer L2 latency behavior brad/deterministic_resurrection: ruby: Resurrected Ruby's deterministic tests brad/token_dma_fixes: ruby: MOESI_CMP_token dma fixes brad/ruby_cmd_options: config: added cmd options to control ruby debug brad/token_owner_fixes: ruby: fixed token bugs associated with owner token counts brad/ruby_remove_try_except: ruby: Improved try except blocks in ruby creation brad/ruby_port_callback_fix: ruby: Fixed RubyPort sendTiming callbacks brad/interrupt_drain_fix: devices: Fixed periodic interrupts to work with draining brad/llsc_trace_profile: ruby: Added SC fail indication to trace profiling brad/no_migrate_atomic: ruby: Disable migratory sharing for token and hammer brad/ruby_start_time_fix: ruby: Reset ruby stats in RubySystem unserialize brad/numa_bit_select_fix: ruby: fixed DirectoryMemory's numa_high_bit configuration brad/hammer_probe_filter: ruby: added probe filter support to hammer brad/miss_latency_detail_profile: MOESI_hammer: break down miss latency stalled cycles brad/recycle_latency_fix: ruby: Recycle latency fix for hammer brad/stall_and_wait: ruby: Stall and wait input messages instead of recycling brad/rubytest_request_flag_fix: ruby: Fixed minor bug in ruby test for setting the request type brad/hammer_merge_gets: ruby: Added merge GETS optimization to hammer brad/regress_updates: regress: Regression tester updates |
7529:383498e0a1cd |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
test: Update stats for python object iteration. Small changes in tests with data races due to new object creation order. |
7526:4bb5f5207617 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: fail on implicit creation of orphans via ports Orphan SimObjects (not in the config hierarchy) could get created implicitly if they have a port connection to a SimObject that is in the hierarchy. This means that there are objects on the C++ SimObject list (created via the C++ SimObject constructor call) that are unknown to Python and will get skipped if we walk the hierarchy from the Python side (as we are about to do). This patch detects this situation and prints an error message.
Also fix the rubytester config script which happened to rely on this behavior. |
7525:722f2ad014a7 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: make Python Root object a singleton Enforce that the Python Root SimObject is instantiated only once. The C++ Root object already panics if more than one is created. This change avoids the need to track what the root object is, since it's available from Root.getInstance() (if it exists). It's now redundant to have the user pass the root object to functions like instantiate(), checkpoint(), and restoreCheckpoint(), so that arg is gone. Users who use configs/common/Simulate.py should not notice. |
7524:1eb0be76e800 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: update reference config.ini files for previous cset Rename 'responder_set' to 'use_default_range'. |
7513:a3a439363a47 |
27-Jul-2010 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Add regression tests |
7483:333ca39e832a |
25-Jun-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update regressions from RAS fix |
7479:1b1f8f32fe86 |
24-Jun-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update regressions |
7474:ddd77866bf82 |
23-Jun-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update regressions |
7466:c880d4812539 |
16-Jun-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update stats for SC protocol change Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences. |
7461:5a07045d0af2 |
15-Jun-2010 |
Nathan Binkert <nate@binkert.org> |
stats: only consider a formula initialized if there is a formula |
7449:111f36470db4 |
06-Jun-2010 |
m5test <m5test@zizzer> |
tests: Update O3 ref outputs to reflect Lisa's dist format change. |
7448:ba1a0193c050 |
06-Jun-2010 |
Steve Reinhardt <stever@gmail.com> |
stats: fix stats diff script Previously the return value ignored missing/added stats, making the regressions not tell you when you needed to update the reference stats because of these changes. Also stop filtering distributions when reporting these; not sure why we did that in the first place. Also get rid of obsolete hacks for the "fetch-loss" stats that have been gone for a long time. |
7415:dda264727e75 |
02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Updated regressions for changes in SE mode stack |
7198:6cb879bc1924 |
02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Update the stats for the new syscall behavior. |
7180:a654c4bffac9 |
02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Update the stats now that VFP load/store multiple is implemented. |
7086:87782b4966d9 |
19-May-2010 |
Ali Saidi <saidi@eecs.umich.edu> |
BPRED: Update one missing regression |
7083:d915b0f60b22 |
13-May-2010 |
Ali Saidi <saidi@eecs.umich.edu> |
BPRED: Update regressions for tournament predictor fix. |
7077:b9480b90cf18 |
06-May-2010 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats for the new aux vectors in the ruby regression. I forgot to turn on ruby when updating the stats before. |
7074:e46d048f7e69 |
03-May-2010 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for the updated auxilliary vectors. |
7062:0f513e623826 |
11-Apr-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update regressions for fwd-ing patch |
7051:d4921c2e136b |
27-Mar-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update twolf/vortex regressions |
7043:86558845c195 |
23-Mar-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update hello world for alpha and mips |
7041:ba1ff0a71710 |
23-Mar-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update twolf regression |
7040:0039707f915e |
22-Mar-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update vortex regression |
7034:6bf327b128c6 |
22-Mar-2010 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: Regression updates for new ruby config locations |
6980:9ec11ecd228a |
25-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
stats: update stats for the changes I pushed re: shared cache occupancy |
6978:ab05e20dc4a7 |
23-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
cache: Make caches sharing aware and add occupancy stats. On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0). |
6964:a3a20caba701 |
31-Jan-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update hello world mips |
6963:d96b8280b306 |
31-Jan-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: vortex alpha regression |
6962:1670a39731f4 |
31-Jan-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: twolf alpha regression |
6961:e307fe70f59d |
31-Jan-2010 |
Korey Sewell <ksewell@umich.edu> |
inorder: update hello world alpha |
6928:5bd33f7c26ea |
29-Jan-2010 |
Brad Beckmann <Brad.Beckmann@amd.com> |
m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. |
6919:dd45a54732aa |
29-Jan-2010 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: memtest-ruby updated to the new config system |
6874:22df98a968bf |
29-Jan-2010 |
Steve Reinhardt <Steve.Reinhardt@amd.com> |
tests: added M5_TEST_PROGS environment variable to allow override of global location for regression test binaries. |
6870:5707ef3691b5 |
25-Jan-2010 |
Derek Hower <drh5@cs.wisc.edu> |
config: changed default ruby config file for regression |
6864:40d2245c6679 |
19-Jan-2010 |
Derek Hower <drh5@cs.wisc.edu> |
memtest differences from Derek's changes |
6862:3d308cbd1657 |
19-Jan-2010 |
Derek Hower <drh5@cs.wisc.edu> |
merge |
6836:1a01f799bd76 |
11-Sep-2009 |
Derek Hower <drh5@cs.wisc.edu> |
ruby: cleaned up unified MESI/MOESI configuration |
6813:9e14a8c76257 |
02-Jan-2010 |
Gabe Black <gblack@eecs.umich.edu> |
MIPS: Update the stats of the RUBY version of the regressions. |
6812:451ddd5d50d6 |
31-Dec-2009 |
Gabe Black <gblack@eecs.umich.edu> |
MIPS: Update stats for updated initial environment. |
6798:289ac904233d |
18-Nov-2009 |
Brad Beckmann <Brad.Beckmann@amd.com> |
m5: refreshed the ruby memtest regression stats |
6767:71b272bd988e |
18-Nov-2009 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: included ruby config parameter ports per core Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port. |
6765:b5101309174d |
18-Nov-2009 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: Support for merging ALPHA_FS and ruby Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports. |
6729:362fd710ac5f |
08-Nov-2009 |
Nathan Binkert <nate@binkert.org> |
tests: update statistics for change caused by vsyscall support in x86 Caused by a slight change in memory layout. |
6710:9c3577d9704a |
04-Nov-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: update memtest-ruby I don't know if the new stats are right or not, but we've been too long with a useless regression so I'm just going to update them. |
6692:a3c85a29b838 |
27-Oct-2009 |
Timothy M. Jones <tjones1@inf.ed.ac.uk> |
test: Hello world test program for Power includes reference outputs for the Hello World tests on simple-atomic and o3-timing. |
6688:9cf72f7eb5c4 |
24-Oct-2009 |
Nathan Binkert <nate@binkert.org> |
tests: update test for slight change due to the change in brk. |
6675:8b3818b0b34c |
06-Oct-2009 |
Korey Sewell <ksewell@umich.edu> |
mips: update hello-ruby stats |
6662:8dc0b1a04a96 |
24-Sep-2009 |
Korey Sewell <ksewell@umich.edu> |
mips-stats: update regressions of arguments fix |
6654:4c84e771cca7 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. |
6613:4f4318647837 |
18-Aug-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for new SSE instructions. |
6495:04a90b404da6 |
11-Aug-2009 |
Tushar Krishna <Tushar.Krishna@amd.com> |
ruby/network data_msg_size bug fix with updated stats |
6494:be123e27612f |
11-Aug-2009 |
Brad Beckmann <Brad.Beckmann@amd.com> |
merged Tushar's bug fix with public repository changes |
6493:1fa51760a963 |
07-Aug-2009 |
Tushar Krishna <Tushar.Krishna@amd.com> |
bug fix for data_msg_size in network/Network.cc |
6487:297b8ef5eb35 |
09-Aug-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats on the ruby x86 regressions for the new CMOVcc implementation. |
6483:6187a528a5c5 |
08-Aug-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats for the slightly lengthened cmov. |
6471:2d4c2adb45fc |
05-Aug-2009 |
Derek Hower <drh5@cs.wisc.edu> |
regression: updated stats |
6435:e32e9c02178d |
31-Jul-2009 |
Derek Hower <drh5@cs.wisc.edu> |
regression: updated stats |
6414:3a2197efb6ec |
27-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Update the stats for the EABI version of hello world. |
6396:2f551f287dd0 |
27-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Update the reference outputs for the new binary and fstat64 struct. |
6394:0097bc59a0a7 |
27-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Replace hello world with an EABI version. |
6389:2352ea7fb955 |
25-Jul-2009 |
Korey Sewell <ksewell@umich.edu> |
regress: edit 2t hello smt file to specify numThreads |
6374:11423b4639c0 |
20-Jul-2009 |
Derek Hower <drh5@cs.wisc.edu> |
ruby: moved cache stats from Profiler to CacheMemory
Caches are now responsible for their own statistic gathering. This requires a direct callback from the protocol on misses, and so all future protocols need to take this into account. |
6357:bd813379f121 |
15-Jul-2009 |
pdudnik@gmail.com |
Tester update |
6339:61f8eb04e96d |
13-Jul-2009 |
Derek Hower <drh5@cs.wisc.edu> |
regression: updated memtest-ruby stats
This also includes a change to the default Ruby random seed, which was previously set using the wall clock. It is now set to 1234 so that the stat files don't change for the regression tester. |
6293:a37f8971b271 |
07-Jul-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Add ability to skip tests by adding 'skip' file to test dir, and skip simple-timing-mp-ruby test for now (until we fix ruby atomics). |
6291:2e91670790c8 |
06-Jul-2009 |
Nathan Binkert <nate@binkert.org> |
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff |
6290:21a58cf03386 |
06-Jul-2009 |
Nathan Binkert <nate@binkert.org> |
tests: update regression tests for changes in stats output and changes in ruby. |
6289:a9e7d19871b5 |
06-Jul-2009 |
Nathan Binkert <nate@binkert.org> |
ruby: Fix RubyMemory to work with the newer ruby. |
6282:eae881827513 |
05-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
inorder: Fix up some reference stats. |
6238:2f66c82a2e20 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a hello world regression. |
6237:ee66c4856854 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a hello world binary. |
6210:1d6fac03f389 |
13-May-2009 |
Korey Sewell <ksewell@umich.edu> |
mips-merge: merge hello world regress for inorder cpu w/latest changes |
6209:ce59a9265cdc |
13-May-2009 |
Korey Sewell <ksewell@umich.edu> |
inorder-regress: add hello MIPS_SE |
6198:173f58c8a718 |
12-May-2009 |
Korey Sewell <ksewell@umich.edu> |
inorder-regress: missing regress config file regressions need to access this file to setup the InOrderCPU object |
6196:acff712232e9 |
12-May-2009 |
Korey Sewell <ksewell@umich.edu> |
inorder-regress: add vortex ALPHA_SE |
6195:84fff8772f51 |
12-May-2009 |
Korey Sewell <ksewell@umich.edu> |
inorder-regress: add twolf ALPHA-SE |
6194:2078ba7cefe4 |
12-May-2009 |
Korey Sewell <ksewell@umich.edu> |
inorder-regress: add hello world |
6177:8684c61ac457 |
11-May-2009 |
Korey Sewell <ksewell@umich.edu> |
Merge Ruby Stuff |
6168:ba6fe02228db |
11-May-2009 |
Nathan Binkert <nate@binkert.org> |
ruby: add RUBY sticky option that must be set to add ruby to the build Default is false |
6167:8b240f106634 |
11-May-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
ruby: Initial references for ruby regressions |
6166:6fad2d8345b7 |
11-May-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
ruby: Set up Ruby regression tests. |
6127:eb26da1fc16d |
22-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway. |
6123:82c377317a86 |
22-Apr-2009 |
Steve Reinhardt <stever@gmail.com> |
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests. |
6122:9af6fb59752f |
16-Jul-2008 |
Steve Reinhardt <Steve.Reinhardt@amd.com> |
mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
6112:21f6eaab12df |
21-Apr-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs. |
6053:aa9ca21a9af4 |
19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats for the fix for CPUID. |
6039:fd5ed84c460e |
18-Apr-2009 |
Korey Sewell <ksewell@umich.edu> |
o3-mips-regress: add hello word regression. |
6030:63911a3f54f4 |
15-Apr-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Update stats after elimination of Unallocated state. Somehow ending threads with halt() instead of deallocate() reduces the squash count on o3 by 1 (and a few other similarly trivial changes). |
6025:044903442dcb |
09-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
alpha: get rid of all turbolaser remnants |
6024:0555121b5c5f |
09-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
tests: update tests for TLB unification |
6020:0647c8b31a99 |
06-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Merge ARM into the head. ARM will compile but may not actually work. |
6014:77bf0b8db2c5 |
16-Mar-2009 |
Steve Reinhardt <stever@gmail.com> |
Very minor regression stats updates due top previous changeset. Setting dirty bit on swaps added a handful of writebacks in a few of the longer-running SPARC_SE benchmarks. |
6011:27836c06d13d |
11-Mar-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: use env.Execute instead of Execute to pick up env vars. |
6008:fb50ea61a226 |
07-Mar-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Minor tweak to regression exit status message. |
6007:e0344c15e73b |
07-Mar-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Fix up regression execution to better handle tests that end abnormally. E.g., mark aborts due to assertion failures as failed tests, but those that get killed by the user as needing to be rerun, etc. |
6006:5437d5f54973 |
07-Mar-2009 |
Nathan Binkert <nate@binkert.org> |
tests: update tests because of changes in stat names and in the stats package |
5921:80c3baea7444 |
25-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats now that prefetch is implemented. |
5915:156cc0770e74 |
25-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
CPU: Update stats now that there's no fetch in the middle of macroops. |
5896:09065e8e9c50 |
25-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats for in place TLB miss handling. |
5876:7202be891bb4 |
16-Feb-2009 |
Steve Reinhardt <stever@gmail.com> |
Update stats for new prefetching fixes. Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway. |
5850:188dbf56efbd |
01-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update stats now that the micropc isn't always reset on faults. |
5796:20698b854948 |
17-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Stats: Update parser statistics for Linux special files update (parser runs should now be deterministic). |
5778:e5dcc4ca36b0 |
15-Dec-2008 |
Gabe Black <gblack@eecs.umich.edu> |
Update the stats for the fixes to the PCI device class. |
5773:7434b2271b0c |
08-Dec-2008 |
Nathan Binkert <nate@binkert.org> |
output: Change default output directory and files and update tests. |
5759:6e65ac8a2c80 |
05-Dec-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. |
5750:c5447915af50 |
17-Nov-2008 |
Steve Reinhardt <stever@gmail.com> |
Update stats for brk fix (cset f28f020f3006). |
5743:a3fdb234b71a |
14-Nov-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the mcf stats. I must have missed updating these for the change to send both parts of a split packet at the same time. |
5729:f186533c0dc2 |
10-Nov-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add x86 reference output for the timing CPU. |
5723:c36087d4573d |
06-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache. |
5721:11e6f4fa85c3 |
05-Nov-2008 |
Lisa Hsu <hsul@eecs.umich.edu> |
new mp eio test |
5703:7478bc206949 |
20-Oct-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete. |
5660:b7adf50863dc |
12-Oct-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the stats for cpuid's new implementation |
5575:9b3cfab6f42e |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
tests: Update all tests for small outstanding changes. Little differences have accumulated over time and it's worth getting things back in sync for the stable release. |
5574:c911120880b1 |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
tests: rename the terminal files for solaris. I forgot to do this when I renamed everything else. |
5573:f9b13e7aea07 |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
tests: perlbmk now works. Commit stats and assume the're right. Kevin fixed how O3 handles syscalls that change NextPC (longjump). |
5572:16fe9e6c6e0e |
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
tests: Kevin fixed how writebacks are handled in SMT and that changed stats. |
5540:bf358d99eff7 |
03-Sep-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Fix the microcode for sign/zero extending moves that use high byte registers. |
5526:2764c7769ee3 |
04-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Minor fix for test/SConscript... forgot to 'qref' before 'qdel', argh. |
5525:abb8846b2e62 |
04-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Make test/SConscript use new redirection options. |
5523:6279e78a2df2 |
03-Aug-2008 |
Nathan Binkert <nate@binkert.org> |
sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. |
5520:cf280b3621cf |
03-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Make default PhysicalMemory latency slightly more realistic. Also update stats to reflect change. |
5516:12d1a425d249 |
24-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
regress: update regressions for tty emulation fix. |
5511:c3149423e6cc |
22-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
tests: There's a small unknown stats difference in 20.parser, accept it. Hopefully if the difference pops back up, we can figure out what it was |
5510:2f132c18f9bc |
22-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
Mips was missing a few stats |
5509:6d271691faa5 |
22-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion. |
5486:c12f0b8833d2 |
18-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
tests: update tests for slight changes in nsgige posted interrupts |
5479:6130dd6ee658 |
17-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
Change the default output filename for the terminal so it's more obvious. |
5421:df8abcd01ae6 |
12-Jun-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the regressions for the new string instructions. |
5410:179bd970e2f2 |
12-Jun-2008 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the regressions for the fact that rdtsc does something now. |
5382:5310073a6497 |
17-Mar-2008 |
Steve Reinhardt <stever@gmail.com> |
Update long regression stats for semi-recent cache changes. |
5367:10c4b7c31007 |
27-Feb-2008 |
Steve Reinhardt <stever@gmail.com> |
Update outputs for quick tests to reflect fixed cache stats. Will update long tests later. |
5355:39d12ed5a124 |
26-Feb-2008 |
Gabe Black <gblack@eecs.umich.edu> |
Bus: Update the stats for the recent bus fix. |
5351:6cb13630fbc3 |
16-Feb-2008 |
Steve Reinhardt <stever@gmail.com> |
Update stats for new writeback behavior. |
5349:e54743c3b3d2 |
16-Feb-2008 |
Steve Reinhardt <stever@gmail.com> |
Update stats for some unknown minor x86 changes (assuming someone just forgot to do this... tsk tsk). |
5329:dc472c05781a |
16-Jan-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
Update long o3 regressions for o3 change in previous changeset |
5328:e79596220df1 |
15-Jan-2008 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update O3 ref outputs: very minor stats change due to previous cset. (from Steve on behalf of m5test). |
5320:5868393c2ade |
02-Jan-2008 |
Steve Reinhardt <stever@gmail.com> |
Very minor memtest regression stats changes from recent coherence bug fixes. |
5308:cc4cc196e738 |
03-Dec-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Update the parser reference output which has mysteriously changed again? |
5286:0ef359b4a1f2 |
29-Nov-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Fix the initial stack to match what the Linux kernel does. |
5285:c9f212c32260 |
29-Nov-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Combine the 64 and 32 bit process initialization code. Alignment is done as it was for 32 bit processes. |
5272:8bf3ee012ccf |
16-Nov-2007 |
Steve Reinhardt <stever@gmail.com> |
Update memtest results due to new deferred-target-promotion fix. Turned out this scenario was happening, but due to other activity, the writable block returned by the ReadResp would get downgraded or invalidated before the "unnecessary" ReadExResp/UpgradeResp returned, thus avoiding triggering the assertion that led us to catch this. |
5186:cb0094817ed2 |
26-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Forgot to update the hello world stats after adding cda microops. |
5179:9ea5593e01f2 |
22-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Use the cda microop where appropriate. The ENTER instruction still needs these. |
5176:43fb805e1b85 |
21-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Start using the stupd microop, and update statistics accordingly. |
5156:44ba550bd8b2 |
16-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add a bzip2 regression. |
5155:481203e4a4ec |
16-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Fix the parser stats which myseriously differ even for the revision they came from. |
5148:feb9f4559c3f |
12-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add 5 new x86 regressions. |
5146:d933a54b15da |
10-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Regressions: Make mcf have 256MB which it needs for 64 bit builds. |
5102:79d082dd547d |
28-Sep-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Update statistics for the last three revisions |
5017:b8c14d2124d1 |
27-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Update the statistics for the SPARC gzip benchmark in o3. |
5000:f7e42ae49243 |
26-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Stats: Update the stats. |
4979:169ddaa9965e |
14-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Update EIO simple-timing test for new cache. |
4978:f2838f109e8b |
14-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Update insttest regressions for new cache. |
4977:f167d9196a55 |
14-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Use test-progs in /dist instead of tests/test-progs since they all aren't there. |
4971:42ce21888baf |
12-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Update stats for cache changes. |
4966:427e4677e589 |
10-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Regression: Add an I/O Cache to the full system regressions that have a cache. |
4948:55bcb35dc166 |
04-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with head. |
4938:142c12097bee |
03-Aug-2007 |
Steve Reinhardt <stever@gmail.com> |
tests: new ref outputs for new cache model |
4937:04ace9ab855e |
03-Aug-2007 |
Steve Reinhardt <stever@gmail.com> |
tests: replace all dest ref files on upgrade (if possible). Originally we were copying all source files in, but this caused problems when (large) inputs were copied along with outputs. Then we switched to just copying the standard files (m5stats.txt, etc.) but that was missing things like the *.console files. This fix should catch all the non-standard files too as long as they are copied in manually once when the test is set up. Also get a lot nicer about warning when files are ignored, and warn when expected files are missing. Those new Python sets sure are handy. |
4936:b05a404dce16 |
03-Aug-2007 |
Steve Reinhardt <stever@gmail.com> |
tests: config.out no longer exists, eliminate ref copy. |
4876:a18cedc19da5 |
30-Jun-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get rid of remaining traces of obsolete CoherenceProtocol object. |
4831:5f45e5b289ce |
01-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Fix for new parameter stuff. |
4781:59a75bd0ddf4 |
28-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
style: Check/Fix whitespace on SCons files |
4657:fbb52a59e0cc |
22-Jun-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update of reference outputs. SPARC_SE o3 gzip didn't have reference outputs, mcf has a reduced input size, and most of the other changes are for a change in how branch mispredicts work which makes things more accurate. |
4655:c366b36712f9 |
20-Jun-2007 |
Gabe Black <gblack@eecs.umich.edu> |
long is too long |
4646:792c7374e3c8 |
23-Apr-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec |
4643:4725b28e2d14 |
22-Apr-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Change mcf to use smred inputs so it doesn't take two days to run in o3. |
4633:53b16b4952df |
13-Apr-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Adjust references to reflect differences without special delay slot handling. Performance actually went up slightly. |
4611:9471f0fad97b |
21-Jun-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update stats for fixed nextCycle() |
4557:ec3e2e87818c |
12-Jun-2007 |
Nathan Binkert <binkertn@umich.edu> |
update for small parameter and statistics name changes |
4467:cb5715e021ca |
19-May-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. |
4463:8d53dfe8b497 |
15-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update all the regresstion tests for release |
4444:0648bdc8d1c9 |
10-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs
configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs |
4443:6ecf40405296 |
10-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zizzer:/bk/newmem into pb15.local:/Users/ali/work/m5.newmem.zeep
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: the new version of this is what we want |
4441:e60ba189480a |
07-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update for partial write fix changes |
4440:4bf84c726cc1 |
10-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update for bus bridge updates |
4430:c9370bec18b8 |
01-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update for dprintk and not initializing lastTxInt |
4422:69050e472b43 |
30-Apr-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update refs for uart device changes |
4414:7f3e99944792 |
27-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Updates for clock changes. |
4413:ea7be4f09d62 |
27-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Update Alpha reference stats for clock changes.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out: tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr: tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out: tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr: tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr: Update refs for clock changes. |
4398:e4d03e02c412 |
23-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Update refs for CPU clock changes and O3 CPI/IPC calculation updates.
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out: tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini: tests/quick/00.hello/ref/mips/linux/simple-timing/config.out: tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-timing/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini: tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out: tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout: tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini: tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out: tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr: tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr: tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout: tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini: tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out: tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt: tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr: tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout: Update refs. |
4393:6a9abcd8c2c7 |
22-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Updated refs for calculating IPC/CPI. |
4391:48a53b42a6c5 |
22-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Update refs for new CPU frequency changes.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs |
4390:76bbcf725852 |
22-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Update configs to set the CPU clock properly. |
4389:05c01952b1e9 |
23-Apr-2007 |
Lisa Hsu <hsul@eecs.umich.edu> |
update_refs for ALPHA_FS with new disk image.
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout: update_refs |
4364:0c6cffac369a |
15-Apr-2007 |
Kevin Lim <ktlim@umich.edu> |
Update long test refs.
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out: tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini: tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out: tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out: tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out: tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr: Update refs. |
4355:7cf742432c2a |
09-Apr-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC o3 insttest regression. |
4354:52d320a10f8a |
09-Apr-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC simple timing regression for insttest |
4316:c3db63570fcf |
30-Mar-2007 |
Kevin Lim <ktlim@umich.edu> |
Update refs for recent changes. |
4312:a8508d707260 |
29-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC_SE simple timing twolf regression. |
4311:c476c7473db3 |
29-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added a SPARC_SE simple timing mcf regression. |
4306:6e2f543b63ec |
29-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC_SE simple timing gzip regression. |
4304:6575f3ff83a5 |
29-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC_SE simple timing vortex regression. |
4292:b27ad49b17c6 |
29-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add to instruction test sttw instruction |
4289:42b375c9a55c |
25-Mar-2007 |
Kevin Lim <ktlim@umich.edu> |
Update stats for changes. |
4286:de690539735c |
24-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added a SPARC_SE simple atomic regression for the mcf benchmark. |
4270:b2ad46861eec |
21-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Add a s SPARC_SE gzip regression |
4269:6e2c726dad92 |
21-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
created SPARC_SE vortex regression. |
4238:15370ee59b04 |
12-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Added SPARC twolf regression. |
4234:6d51b567ced1 |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
bzip2 is a tru64 regression, not linux |
4233:24be80fab8e8 |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
vortex is a tru64 regression and not linux |
4232:a920feb31f7e |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
perlbmk is a tru64 regression, not a linux one |
4231:6713c0701621 |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
eon is a tru64 regression, not a linux one |
4230:75f70dd5f281 |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
parser is a tru64 regression, not linux. |
4229:5814f5f3ac5a |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
gzip is really a tru64 regression, not linux |
4228:6de1a44ae210 |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
The alpha twolf regression was really for tru64, not linux. |
4227:cd361c36c3be |
11-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Make the SPEC regressions work for any isa/operating system. |
4225:725980b1b5b7 |
03-Apr-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
fixed sttw instruction changes execution trace a bit |
4199:09b4d32a3e49 |
10-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
If you can't get rid of the files you want to make sure are gone, assume they're already gone. Print a warning and move on. |
4170:0194445bca7b |
06-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Add regression for SPARC "hard" instruction test. Only runs in simple-atomic right now since we don't have cache support for the atomic instructions. |
4167:ce5d0f62f13b |
06-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. |
4166:ecebe3ac19b4 |
06-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Get X86 to load an elf and start a process for it.
src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. |
4130:a611c874376e |
03-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add a sparc fs regression
src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress |
4107:3ac1abf8e035 |
27-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Fix issue with twolf where the presence or absence of two files, smred.sav or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3" |
4103:785279436bdd |
03-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore |
4083:8771aaecc2c7 |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt: "Hand merge" that just used the local file. |
4072:60e0e1ebb4c9 |
17-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update for 8k block size. |
4071:58f05aa697a3 |
17-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update reference outputs because twolf was really fixed. |
4069:aa82e7b89f72 |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update 50.vortex simple-timing for 8k blk_size |
4068:07206e9a57bf |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update 50.vortex simple-atomic for 8k blk_size |
4067:f67e66b266f0 |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update 40.perlbmk simple-timing for 8k blk_size |
4066:87bde163dfc6 |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update 40.perlbmk simple-atomic for 8k blk_size |
4065:0c602be9909b |
20-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update 30.eon simple-timing for 8k blk_size. It's strange this is necessary because simple-atomic doesn't seem affected. |
4062:f5aee6e13e5d |
14-Feb-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Reference outputs fixed to reflect branch mispredict change and 8k io buffers. |
4030:4046b2213995 |
23-Mar-2007 |
Kevin Lim <ktlim@umich.edu> |
A couple of minor fixes. 1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true.
src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. |
4019:cdfb21ba304e |
07-Feb-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. |
4013:ed6ea8defc64 |
31-Jan-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Create reference outputs for this regression. |
3974:5940cbe0d123 |
23-Jan-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Update to stats because of minor to branch mispredict accounting. |
3934:ca2aa5d36115 |
25-Jan-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move time forward to Jan 1, 2009 and update stats |
3711:19fd1a8a8056 |
10-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get rid of dummy 'hello world' outputs. |
3710:854260c33770 |
10-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Delete parser reference outputs so that test will no longer be run. Runtimes are way too long with current inputs. |
3702:9820963681cb |
04-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update SPEC CPU2000 tests with actual benchmark output.
tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini: tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out: tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr: tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout: tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini: tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out: tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr: tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout: tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini: tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out: tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr: tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout: tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini: tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out: tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr: tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout: tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini: tests/long/30.eon/ref/alpha/linux/simple-timing/config.out: tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/30.eon/ref/alpha/linux/simple-timing/stderr: tests/long/30.eon/ref/alpha/linux/simple-timing/stdout: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr: tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr: tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout: tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini: tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out: tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr: tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout: tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini: tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out: tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr: tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout: tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini: tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out: tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr: tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout: tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini: tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out: tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr: tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr: tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout: tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini: tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out: tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr: tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout: tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini: tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out: tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr: tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout: tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini: tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out: tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr: tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout: tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini: tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out: tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt: tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr: tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout: Update with actual benchmark output. |
3701:595232e44c52 |
04-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Only update stderr, stdout, m5stats.txt, and config.* on update_ref, since we don't know which of the other files are outputs and which are inputs. |
3700:a2eb0540510c |
04-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Clean up SPEC CPU2000 reference files. Get rid of reference files for o3-atomic (non-existent configuration) and mcf (doesn't seem to be working). Left in empty refs for parser/simple-timing... this appears to be dying because it's running out of memory, so maybe it will be OK once we get the memory leak fixed. |
3697:167e23f5a507 |
02-Dec-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
stats update |
3695:570343eb829f |
01-Dec-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
change this to be a quick one so that it's in the regressions every night - it's only maybe 15 min. long.
tests/configs/twosys-tsunami-simple-atomic.py: don't need this import |
3692:53d3f0b0ebc0 |
30-Nov-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update stats to match writeback fix that was made |
3691:cf8853913972 |
01-Dec-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
add a simple netperf-stream test to the long tests.
tests/SConscript: add a new configuration for two-system tests (atomic simple only) |
3678:a689a7cf337e |
22-Nov-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Do a functional access to levels above on a read as a temporary solution for L2's in FS
Fix a small writeback bug when missing in the L2 in atomic mode
src/mem/bus.cc: Fix a comment to make sense src/mem/cache/cache_impl.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS Also fix a small writeback miss in L2 issue src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: Update ref's for writeback changes |
3671:c60eba24f33b |
16-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Implement a single config file to encompass all of the SPEC CPU2000 stuff, and use it in all of the tests that currently use SPEC |
3638:3bb54104e922 |
13-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Update output refs. Some FS statistics will change (namely the ITB) due to the recent TLB changes. Now PAL mode accesses are counted as hits in the TLB.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: Update refs. |
3622:58281027913f |
12-Nov-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update refs for functional access fixes |
3594:e401993e0cbb |
10-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem |
3518:51a02f5fe895 |
08-Nov-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
the tests assume -1 to signify MaxTick, that's changed, so fix that here. |
3505:d2f89e2b0107 |
08-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Update refs.
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: Update config. tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: Update ref. |
3493:845fd014c443 |
05-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Update refs. |
3475:45bdddb5e7f0 |
10-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Also include a function to form the input path. |
3474:6ecde62f3e99 |
10-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Try to setup commands properly. |
3428:07732a1601c8 |
27-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Update stats for fill/spill handlers |
3402:db60546818d0 |
31-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. |
3389:6e5d98b43d70 |
23-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Add reference outputs for SPARC on the atomic timing cpu model |
3341:82c51d920701 |
19-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Fix corner case on assertion. I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses |
3312:dbaec4804adf |
18-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now). |
3301:9fe568b143d8 |
13-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Fix stats for new bus model |
3294:3df57e3ccbab |
12-Oct-2006 |
Korey Sewell <ksewell@umich.edu> |
config file updates |
3257:269df2f3bb2b |
11-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Interesting memtest finally. Get over 500,000 reads on each of 8 testers before memory leak becomes large.
tests/configs/memtest.py: Update test to be more interesting |
3233:cfa0ef1ae742 |
10-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Updates refs.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: Update refs. |
3230:e86a03911728 |
09-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/simple/timing.hh: tests/configs/o3-timing-mp.py: Hand merge. |
3223:a2b6fa575c05 |
08-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Clean up configs.
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. |
3213:abec59cb96ce |
09-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
updated reference output |
3208:97d9cc1e626f |
10-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Fix several bugs pertaining to upgrades/mem leaks.
src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase |
3200:4b072dcc7a57 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update configs for cpu_id
tests/configs/o3-timing-mp.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: Update config for cpu_id |
3198:b2e5b4926042 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Multiprogrammed workload, need to generate ref's for it yet. But Nate wanted the config. Not sure on the naming convention for tests. |
3196:8eb90bc29df8 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Make memtest work with 8 memtesters
src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system |
3187:7eefad0aed11 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update the Memtester, commit a config file/test for it.
src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description |
3186:19b99d8aa248 |
08-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update stats for functional path fix |
3176:1dc4dc8310c2 |
08-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it).
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout: update for m5 base linux. |
3171:64a140d10a65 |
08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update ref stats: ll/sc, cpu_id, new kernel (?) |
3170:37fd1e73f836 |
08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation.
src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. |
3154:5d7de9a5dffe |
07-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update stats for change in functional path in cache |
3147:544c694a8024 |
07-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Update refs.
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: Update refs. (Korey's initial push didn't use the default O3-timing config?) |
3142:58fd57ea43e4 |
06-Oct-2006 |
Korey Sewell <ksewell@umich.edu> |
add SMT hello world test - 2 threads |
3140:ce16cedf0ea0 |
06-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
update full system references for newest disk image from linux-dist. |
3135:8e008e281579 |
05-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Fixes for functional accesses to use the snoop path. And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh: Make timing response at the time of send. src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: Update probe interface to be bi-directional for functional accesses src/mem/packet.hh: Add the function to create an atomic response to a given request |
3134:cf578b0dd70d |
05-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
First pass at snooping stuff that compiles and doesn't break.
Still need: -Handle NACK's on the recieve side -Distinguish top level caches -Handle repsonses from caches failing the fast path -Handle BusError and propogate it -Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc: Make sure to snoop on functional accesses src/mem/cache/base_cache.cc: Wait to make a request into a response until it is ready to be issued src/mem/cache/base_cache.hh: Support range changes for snoops Set up snoop responses for cache->cache transfers src/mem/cache/cache_impl.hh: Only access the cache if it wasn't satisfied by cache->cache transfer Handle snoop phases (detect block, then snoop) Fix functional access to work properly (still need to fix snoop path for functional accesses) |
3108:cf6faaf11e04 |
07-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update port numbers from new unproxy ordering. |
3104:8dc2faebd9b1 |
05-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update reference config.ini files to include port mappings. |
3096:f621bee6e8df |
01-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add o3-timing configuration for ALPHA_SE "Hello world" tests.
build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. |
3095:b11f671d6e05 |
01-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
diff-out: Don't consider it a success if no stats at all were found.
tests/diff-out: Don't consider it a success if no stats at all were found. |
3076:6ffcc6282bf5 |
24-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update a few bogus reference outputs
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: Update reference outputs |
3072:bd31bd22c798 |
22-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update refs for tru64 with initialized cache stats |
3052:598010a4ccd7 |
21-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update REFs for statistics patch in cache |
3051:b4f73000973b |
21-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Merge zizzer:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py: Merge duplicate change |
3048:3da8c7e43b85 |
20-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add Alpha Linux version of "hello world" test. |
3047:d289176e6b94 |
20-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Alpha "hello world" test is really Tru64 not Linux... oops. |
3045:6d46915c242c |
19-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
SConscript: Fix BATCH_CMD bug.
tests/SConscript: Fix BATCH_CMD bug. |
3041:8d690c7c2efc |
18-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update reference outputs |
3040:1fbdad0df45e |
18-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add caches in, fix cpu.mem param |
3021:3b67ff91f0d6 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
More regression updates. Get rid of caches in simple-timing config for now.
tests/SConscript: another line for diff to ignore tests/configs/simple-timing.py: turn off caches for now tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout: tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout: update for inst/tick rate (old one was debug?) tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: works now (no caches) |
3020:a33d8709d348 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Minor regression fixes.
src/python/m5/objects/BaseCPU.py: bug fix tests/SConscript: fix up diff ignore strings to reflect changes in m5 output |
3017:972510aadad0 |
16-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py: Make mem parameter a MemObject, not just a PhysicalMemory Fix a reference not using self tests/configs/simple-atomic.py: Set the mem paramter tests/configs/simple-timing.py: Set the mem parameter |
3006:c665c85d2567 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update reference outputs |
3005:ceb86e85d62d |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Finish test clean-up & reorg.
configs/common/FSConfig.py: Add default Machine() param configs/example/fs.py: configs/example/se.py: make it work again src/python/m5/objects/BaseCPU.py: Make mem PhysicalMemory so that a Parent.any proxy works well src/sim/process.cc: Increase default stack size so we don't get an 'increasing stack' message on 'hello world' tests/SConscript: Add full list of current configs. tests/configs/simple-atomic.py: tests/configs/simple-timing.py: don't need SEConfig anymore tests/quick/00.hello/test.py: tests/quick/20.eio-short/test.py: fix tests/run.py: move configs to separate dir |
2998:1d5ea4e433f5 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
More restructuring of regression tests. Moving work back to zizzer...
configs/common/FSConfig.py: configs/test/fs.py: Move CPU connections out of makeLinuxAlphaSystem() src/python/m5/objects/BaseCPU.py: Create default TLBs in full system. Move utility cache functions here. src/python/m5/objects/O3CPU.py: Add _mem_ports tests/run.py: Add binpath() Change maxtick default to 'forever' tests/simple-atomic.py: Use connectmemPorts() tests/simple-timing.py: Fix up. |
2997:d4f750d960e5 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Halfway through setting up new test structure... committing so O can move to my laptop.
tests/SConscript: Start to simplify. |
2968:c4f1867cc365 |
27-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Update ref stats.
tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. |
2953:10e7700b27f6 |
22-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct: Make test CPUs option non-sticky. configs/common/FSConfig.py: Be sure to set the memory mode. configs/test/fs.py: Wrong string. tests/SConscript: Only test valid CPUs that have been compiled in. tests/test1/ref/alpha/atomic/config.ini: tests/test1/ref/alpha/atomic/config.out: tests/test1/ref/alpha/atomic/m5stats.txt: tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/config.ini: tests/test1/ref/alpha/detailed/config.out: tests/test1/ref/alpha/detailed/m5stats.txt: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/config.ini: tests/test1/ref/alpha/timing/config.out: tests/test1/ref/alpha/timing/m5stats.txt: tests/test1/ref/alpha/timing/stdout: Update output. |
2934:0b091d7d00f0 |
21-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py: Pull out a lot of common code and put it into configs/common/FSConfig.py. |
2932:eba74420a01c |
21-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Minor functionality updates.
SConstruct: Include an option to specify the CPUs being tested. src/cpu/SConscript: Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker. src/python/m5/objects/O3CPU.py: Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used. tests/SConscript: Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on. |
2929:f986dc04e25f |
19-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model>
Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files.
Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.
Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed.
SConstruct: Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again. src/cpu/SConscript: Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only. |