History log of /gem5/system/arm/aarch64_bootloader/
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14113:a443e7bca88b 23-Jul-2019 Chun-Chen TK Hsu <chunchenhsu@google.com>

system-arm: Initialize ICC_SRE_EL3 register

Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.

Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13509:e9fd7d157c80 11-Oct-2018 Jairo Balart <jairo.balart@metempsy.com>

system-arm: Add aarch64 bootloader support for GICv3

Change-Id: If75262709868cc59d320f60273a32397339f1dd5
Signed-off-by: Jairo Balart <jairo.balart@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13435
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12271:fcd15e59fcd5 13-Jun-2017 Jose Marinho <jose.marinho@arm.com>

system-arm: change system/arm/aarch64_bootloader/boot.S copyright

The aarch64 boot loader was distributed using a BSD license that was
using non-standard formatting. Updated the license to match gem5's
canonical license format and removed the separete LICENSE.txt file.

Change-Id: I660b73ca5ddd922763a2b72051c73d539248ebcf
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5728
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11258:9214b39401aa 15-Jul-2015 Karthik Sangaiah <karthik.sangaiah@arm.com>

arm: Bootloader fix for v8 over 16 cores

Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.

10037:5cac77888310 24-Jan-2014 ARM gem5 Developers

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black


/gem5/configs/common/FSConfig.py
/gem5/configs/common/O3_ARM_v7a.py
/gem5/configs/common/Options.py
/gem5/configs/common/cpu2000.py
/gem5/configs/example/fs.py
/gem5/configs/example/se.py
/gem5/ext/libelf/elf_common.h
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/decoder.cc
/gem5/src/arch/arm/decoder.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/branch64.cc
/gem5/src/arch/arm/insts/branch64.hh
/gem5/src/arch/arm/insts/data64.cc
/gem5/src/arch/arm/insts/data64.hh
/gem5/src/arch/arm/insts/fplib.cc
/gem5/src/arch/arm/insts/fplib.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/macromem.hh
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/mem64.hh
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/misc.hh
/gem5/src/arch/arm/insts/misc64.cc
/gem5/src/arch/arm/insts/misc64.hh
/gem5/src/arch/arm/insts/neon64_mem.hh
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/decoder/aarch64.isa
/gem5/src/arch/arm/isa/decoder/arm.isa
/gem5/src/arch/arm/isa/decoder/decoder.isa
/gem5/src/arch/arm/isa/decoder/thumb.isa
/gem5/src/arch/arm/isa/formats/aarch64.isa
/gem5/src/arch/arm/isa/formats/branch.isa
/gem5/src/arch/arm/isa/formats/formats.isa
/gem5/src/arch/arm/isa/formats/fp.isa
/gem5/src/arch/arm/isa/formats/mem.isa
/gem5/src/arch/arm/isa/formats/misc.isa
/gem5/src/arch/arm/isa/formats/neon64.isa
/gem5/src/arch/arm/isa/formats/uncond.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/isa/insts/aarch64.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/branch64.isa
/gem5/src/arch/arm/isa/insts/data.isa
/gem5/src/arch/arm/isa/insts/data64.isa
/gem5/src/arch/arm/isa/insts/div.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/insts/fp64.isa
/gem5/src/arch/arm/isa/insts/insts.isa
/gem5/src/arch/arm/isa/insts/ldr.isa
/gem5/src/arch/arm/isa/insts/ldr64.isa
/gem5/src/arch/arm/isa/insts/m5ops.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/mem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/insts/misc64.isa
/gem5/src/arch/arm/isa/insts/neon.isa
/gem5/src/arch/arm/isa/insts/neon64.isa
/gem5/src/arch/arm/isa/insts/neon64_mem.isa
/gem5/src/arch/arm/isa/insts/str.isa
/gem5/src/arch/arm/isa/insts/str64.isa
/gem5/src/arch/arm/isa/insts/swap.isa
/gem5/src/arch/arm/isa/operands.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/branch64.isa
/gem5/src/arch/arm/isa/templates/data64.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/misc.isa
/gem5/src/arch/arm/isa/templates/misc64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/templates.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/isa/templates/vfp64.isa
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/linux/system.hh
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/miscregs.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/stage2_lookup.hh
/gem5/src/arch/arm/stage2_mmu.cc
/gem5/src/arch/arm/stage2_mmu.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/arm/vtophys.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/SConscript
/gem5/src/dev/arm/generic_timer.cc
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/arm/vgic.hh
/gem5/src/sim/System.py
/gem5/src/sim/process.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
LICENSE.txt
boot.S
makefile
/gem5/util/cpt_upgrader.py
/gem5/util/m5/m5op_arm_A64.S