system-arm: Add ITS node in platforms/vexpress_gem5_v2_base.dtsi

This is aligning sources with DTB autogeneration

Change-Id: Icf369eb85719c91da770398b45645d8b03d8abf3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm,system-arm: missing GICv3 ranges property

This patch adds the device tree "ranges" property to GICv3 for
the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB
auto generation.
This allows the GICv3 ITS to be specified in the device tree.

Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Refactor makefile to create targets with functions

This change simplifies writing targets which has same prefix but
differrent number of CPUs.

Change-Id: I3b7d67a554f5d27714ace6b88c9784ddaa3b34d5
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19989
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Add irq for hypervisor timer in device tree

ARM fast model CPU cannot get timer interrupts without this IRQ setting
in the device tree.

Change-Id: I084c475c04285f4f40eb38a80ddd038207e4764f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Initialize ICC_SRE_EL3 register

Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.

Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Limit number of max PE in GICv3 to 128

This is needed since there is a problem in the memory layout of
VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping
regions when reserving space for 256 PEs.

GICv3 redistributors: 0x2c010000 - 0x30010000
PCI regions: 0x30000000 - 0x40000000

We fix this by cutting down the number of supported PEs to 128

Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Fix dtsi dependencies in Makefile

Making vexpress_gem5_vX.dtsi depend on vexpress_gem5_vX_base.dtsi
does nothing, since vexpress_gem5_vX.dtsi is never built (much in
the same way as there is no point in making a C header depend on
another).

Fix that by making all the .dts depend on both .dtsi's.

Change-Id: I9131e0b1b2e521bb09d14721dec38bf6a2d98583
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Ruben Ayrapetyan <ruben.ayrapetyan@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Add device tree for new VExpress GEM5_V2 platform

Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034
Reviewed-on: https://gem5-review.googlesource.com/c/14275
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Add aarch64 bootloader support for GICv3

Change-Id: If75262709868cc59d320f60273a32397339f1dd5
Signed-off-by: Jairo Balart <jairo.balart@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13435
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1

Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1
platform.

Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2327

system-arm: Update gem5 timer interrupt specification

The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer
interrupts as being edge triggered. Describe the interrupt as being
level triggered to match Juno and FVP.

Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10024
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

system-arm: change system/arm/aarch64_bootloader/boot.S copyright

The aarch64 boot loader was distributed using a BSD license that was
using non-standard formatting. Updated the license to match gem5's
canonical license format and removed the separete LICENSE.txt file.

Change-Id: I660b73ca5ddd922763a2b72051c73d539248ebcf
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5728
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm, config: Add an example ARM big.LITTLE(tm) configuration script

An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Update dts to work with the new HDLCD driver

The dts files in system/arm/dt currently assume that an (unreleased)
gem5-specific virtual encoder is used as a remote endpoint for the
HDLCD. This driver won't be released as a more general virtual encoder
is about to be posted on the Linux DRI devel list and this encoder has
now been merged with gem5's kernel tree. This changeset updates gem5's
dts files to use that encoder.

Change-Id: Ic1a1be728efd31603752fdfba005b6dbdea42e7e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rene De Jong <rene.dejong@arm.com>

arm: Ship Linux device trees with gem5

Ship aarch32 and aarch64 device trees with gem5. We currently ship
device trees as a part of the gem5 Linux kernel repository. This makes
tracking hard since device trees are supposed to be platform dependent
rather than kernel dependent (Linux considers device trees to be a
stable kernel ABI). It also makes code sharing between aarch32 and
aarch64 impossible.

This changeset implements a set of device trees for the new
VExpress_GEM5_V1 platform. The platform is described in a shared file
that is separate from the memory/CPU description. Due to differences
in how secondary CPUs are initialized, aarch32 and aarch64 use
different base files describing CPU nodes and the machine's
compatibility property.

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

arm: Bootloader fix for v8 over 16 cores

Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ARM: Fix issue with with way MPIDR is read to include affinity levels.

The simple_bootloader checks for CPU0 in a manner incompatible with systems
actually using affinity levels -- just looking at MPIDR[7:0]. However, in
future we may wish to use real affinity levels and this method will be in danger
of matching several CPUs with affinity0 = 0.

Match affinity2 == affinity1 == affinity0 == 0 instead.

ARM: Add support for Versatile Express extended memory map

Also clean up how we create boot loader memory a bit.

ARM: Boot loader changes that make it more flexible about load and I/O addrs

Cleanup system directory to fit into modern M5 tree

copyright: update copyright on alpha system files

Fix bug in MDT BITMAP to allow more than 2GB of memory.

Signed-off by Ali Saidi <saidi@eecs.umich.edu>

fix Makefile for new source tree

update our copyrights to the new format

put panic instructions in palcode rather than looping on mchecks.

Add m5op to the build process
use quiesceNs on other CPUs
panic rather than spin on an error

console/Makefile:
Add m5op to the build process
console/dbmentry.S:
use quiesceNs on other CPUs
console/printf.c:
panic rather than spin on an error.

change from bootStrap* to using the cpuStack array for setting up
other processor stacks

Fix console to work on all systems.

console/console.c:
CONS_REM (remote console) doesn't work on Tru64. Use CONS_DZ which
seems to work alright everywhere.

Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/alpha-system
into zed.eecs.umich.edu:/z/benash/bk/alpha-system

console/console.c:
Clean up code.
h/rpb.h:
Update CTB struct.

New console terminal block structure, fix kernel stack pointer.

console/console.c:
Use virtual addresses for kernel stack pointer, use new ctb structure.
h/rpb.h:
Update console terminal block structure.

changes

console/console.c:
fixed bootstrap stack
h/rpb.h:
ctb_term_type instead of ctb_baud

Add missing TSUNAMI ipi code.

console code cleanup

console/console.c:
the go parameter to unixBoot is never used, so get rid of it.
just panic if we return from unixBoot since it's never supposed
to happen.
remove the MAX_CPUS parameter and the bootStrapImpure variable
and just allocate memory as needed. (Can in theory support many
more CPUs.)

pass the location of the m5 backdoor via the m5AlphaAccess variable
only compile one console

console/Makefile:
Now that the location of the m5 backdoor is passed into the
console via the m5AlphaAccess variable, we only need to
compile one console, and don't need to define TLASER or TSUNAMI
console/console.c:
Don't hardcode the location of the AlphaAccess structure, but
rely on m5 to pass in the correct value.
Setup "volatile struct AlphaAccess *m5AlphaAccess" for use and
get rid of the hardcoded usage.

Add tlaser.h, required by platform.S

Major system code cleanup and formatting
remove unused code

console/Makefile:
cleanup Makefile. Remove unneeded -D options
console/console.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename xxm -> m5
rename simos -> m5
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
Major cleanup and formatting
remove unused #ifdef code
remove unused #includes
rename __start -> _start to get rid of warning.
h/cserve.h:
h/dc21164FromGasSources.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/rpb.h:
Major cleanup and formatting
h/ev5_impure.h:
Major cleanup and formatting
remove unused #ifdef code
palcode/Makefile:
cleanup Makefile
remove unused -D options
unify platform_tlaser.S and platform_tsunami.S into platform.S and
generate multiple .o files using various #defines
unify osfpal.S osfpal_cache_copy.S and osfpal_cache_copy_unaligned.S into
osfpal.S and generate multiple .o files using various #defines
palcode/osfpal.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge copy code into this file.
palcode/platform.S:
Major cleanup and formatting
remove unused #defines
remove unused #if code
merge platform code into this file.

HP copyrights

console/Makefile:
Added copyright
added CROSS_COMPILE variable
removed install target
console/console.c:
console/dbmentry.S:
console/paljtokern.S:
console/paljtoslave.S:
console/printf.c:
h/cia.h:
h/cserve.h:
h/dc21164FromGasSources.h:
h/eb164.h:
h/ev5_alpha_defs.h:
h/ev5_defs.h:
h/ev5_impure.h:
h/ev5_osfalpha_defs.h:
h/ev5_paldef.h:
h/fromHudsonMacros.h:
h/fromHudsonOsf.h:
h/lib.h:
h/platform.h:
h/regdefs.h:
h/rpb.h:
palcode/Makefile:
palcode/osfpal.S:
palcode/osfpal_cache_copy.S:
palcode/osfpal_cache_copy_unaligned.S:
palcode/platform_m5.S:
palcode/platform_tlaser.S:
added hp and our copyright

removed tlaserreg.h, rewrote necessary parts
deleted simos.h
deleted tlaserreg.h

palcode/platform_m5.S:
palcode/platform_tlaser.S:
removed tlaserreg.h, rewrote necessary parts

Add support for tsunami with 64 processors and fix some console bugs
I steped on while doing it

console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors

do a better job of always locking printf. We used to only lock on
secondary cpus, this also locks on the primary cpu.
Now the initial print out doesn't get garbled with more than 1 cpu.

Makefile cleanup, no seperate middle preprocessing steps anymore

cleanup makefile and fix platform bug introduced in last commit

palcode/Makefile:
Cleanup make file, no more ugly preprocessing steps
palcode/platform_m5.S:
fix a mistake with m5 platform cleanup from before

update platform code to use PALTemp Whami register to get cpu id
instead of reading register from tsunami chipset, saving an uncached
read

Fix from Adam: Strip the kseg off the physical address in the RPB structure.

changes to make smp work in linux

console/console.c:
Remove Printed SimOS references and replace with M5
Rework the SMP stuff, so we don't trash any stacks, or what we
thought were stacks, but are actually other ppls memory.
console/dbmentry.s:
add a carefully crafted piece of assembly that doesn't use the stack,
so we don't clobber anthing in the time between when we are spinning
and when the OS tells us to go.
palcode/platform_m5.s:
add/fix code for IPI, multiprocessor interrupts (DIR), and initial
bootstrapping of the cpu

changed to generate tlaser and tsunami console code at different
addresses so the uncachable bit is set for tsunami.

console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses

changed the code not to use r11 (specifically) and r8,r9 for good
measure. The rest of the registers I used are touched by the tlaser
platform code so I would guess their are fair game.
Random memory troubles hopefully over.

Copy variables over one at a time rather than copying 4 bytes at a
time. Easiest way to deal with the endian issue.

Rather than using a loop to calculate the interrupt vector, use the ctlz instruction.

Added ALPHA_ACCESS_BASE to get rid of machine_defs.h

erik and I made the the same modification... merged.

Major clean up of alpha system files.

console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file

Deleted a whole bunch of files that we didn't nede in the header
directory

console/dbmentry.s:
console/printf.c:
removed unneeded includes

Setup makefile to compile the 3 flavors of palcode for each platform.

Add copy implementations to palcode.

palcode/osfpal.s:
Add copypal loop copy implementation.

console code now builds on zizzer

console/Makefile:
Updated to build on linux and removed
lots of crud that compiled, disassembled, and then reassembled
console/dbmentry.s:
the assembler didn't like they comments, so I removed them
console/printf.c:
Gcc was very unhappy, so I fixed this line
h/lib.h:
time_t is defined in a std header, and this was causing some problems

palcode updated to deal with interrupts correctly
deleted and then upon realizing we needed them undeleted a bunch of
header files in the palcode dir

console/Makefile:
fixed so it will work with tru64... still haven't got the console to build under linux
palcode/platform_m5.s:
fixed code to "fake" srm console interrupt handling correctly
include serial interrupts

added some comments to palcode and zeroed system type in HWPRB (m5 will fill in)

console/console.c:
0 the system type, let m5 overwrite
palcode/platform_m5.s:
add some comments and make the timer interrupt actually care what CPU it happened on

Change addressing in interrupt code to meet physical addressing requirements

Fixed device I/O interrupt handling

Fix improper shift for loading address

Fix the sys_int_20 handler for doing low priority device interrupts.
Now reads the MISC register to handle interrupts from multiple CPUs

Added platfrom_m5 - Our hacked up tsunami palcode and modified palcode
makefile to that end. Additionally made a change in console to
preserve t7 on call back because linux uses it for the "current"
pointer.

console/Makefile:
Changed makefile back to using gcc and gas rather then trying to
cross-compile for now
console/console.c:
Put code in to save t7 on CallBackFixup() call and changed the
system type to Tsunami
palcode/Makefile:
updated palcode makefile to have targets for tlaser and tsunami

makefiles updated to make use of cross compile tools

console/Makefile:
All tools are variables now
palcode/Makefile:
tool names changed to variables, can build palcode on zizzer

Merge zizzer.eecs.umich.edu:/m5/Bitkeeper/alpha-system
into zizzer.eecs.umich.edu:/y/saidi/alpha-system

Added support for OPEN_CONSOLE and CLOSE_CONSOLE; fixed PUTS bug

Implement GetChar()

console/Makefile:
Quick install target to copy the binary to zizzer

The palcode will now build by simply typing make in this directory.
Most of the changes were to fix broken macros in platfrom_tlaser.s

palcode/Makefile:
Completly new makefile to build palcode
palcode/ev5_alpha_defs.h:
fixed a broken define
palcode/ev5_impure.h:
macro fixes
palcode/platform_srcmax.s:
manual macro expansion of broken macros... this file isn't needed to
build tlaser palcode
palcode/platform_tlaser.s:
lots of fixups to make the code assemble

Implement support for more console environment variables. There
are some default values here, but they can be changed from the
simulator itself. (Search in m5 for boot_osflags)

Get the console code to compile correctly
Add support for some thigns that M5 needs
Make this better support Tru64 v5.1

console/Makefile:
I couldn't figure out the old build system since I was missing
a bunch of tools at the time, so I kinda rewrote it.
console/console.c:
Get the includes right, and make things compile
little bit of cleanup along the way
console/paljtokern.s:
formatting junk
console/printf.c:
Formatting
get const right
h/lib.h:
fiddle with the includes that we need
console/console.c:
Get the BOOTDEVICE_NAME right
Add a bit of support for grabbing console environment variables

Import changeset

ARM: Add code for a simple bootloader for MP boot.