14286:b371c1a1a961 |
18-Sep-2019 |
Gabe Black <gabeblack@google.com> |
python: Don't try to bind a stat group to the NULL simobject.
That is a SimObject like object which is used when a SimObject parameter is purposefully left empty, vs. being accidentally left empty through a typo or accidental ommission.
It doesn't have a getCCObject method, and attempting to use it anyway causes gem5 to crash.
Change-Id: Ie86321fbdbcc41cf88b7009184423acd7b64484b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21059 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14265:464d514d0f6d |
06-Sep-2019 |
Chun-Chen TK Hsu <chunchenhsu@google.com> |
stats: Ignore non-Group objects in stat hierarchy
Some objects, such as SystemC modules, are not a subclass of Stat::Group. Calling the addStatGroup function on them causes errors. This changes ignores those objects that are not Stat::Group in the stat hierarchy.
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Change-Id: I9b62419417b7af7331461fbfaf15e45a4ee2b35f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20680 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14250:f436ee19c7d3 |
06-Sep-2019 |
Gabe Black <gabeblack@google.com> |
python: Make the dot writer handle unconnected Port vector elements.
Change-Id: I5234013716cdcce5fc39e239dc3d92cd1f2b7799 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20699 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14213:6eabb443ab3f |
30-Jul-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add support for listing available formats
Add a command line option to list available stat formats and their documentation.
Change-Id: I7f5f2272d9b0176639f59f2efedb9cab2f7da5b9 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19670 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14209:7efe1c187149 |
22-Apr-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add beta support for HDF5 stat dumps
This changeset add support for stat dumps in the HDF5 file format. HDF5 is a binary data format that represents data in a file-system-like balanced tree. It has native support for N-dimensional arrays and binary data (e.g., frame buffers).
It has the following benefits over traditional text stat files:
* Efficient storage of time series (multiple stat dumps)
* Fast lookup of stats
* Plenty of existing tooling (e.g., Python libraries and graphical viewers)
* File format can be used to store frame buffers together with normal stats.
Drawbacks:
* Large startup cost (single stat dump larger than text equivalent)
* Stat dumps are slower than text
Known limitations:
* Distributions and histograms aren't supported.
HDF5 stat output can be enabled using the 'h5' URL scheme when overriding the stat file name on gem5's command line. The following parameters are supported:
* chunking (unsigned): Number of time steps to pre-allocate (default: 10)
* desc (bool): Output stat descriptions (default: True)
* formulas (bool): Output derived stats (default: True)
Example gem5 command line:
./build/ARM/gem5.opt \ --stats-file="h5://stats.h5?desc=False;formulas=False" \ configs/example/fs.py
Example Python stat consumer that computes IPC: import h5py
f = h5py.File('stats.h5', 'r') group = f['/system/cpu'] for i, c in zip(group['committedInsts'], group['numCycles']): print i, c, i / c
Change-Id: I351c6cbff2fb7bef9012f47876ba227ed288975b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/8121 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> |
14206:9cd30cd80145 |
27-Jun-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add support for partial stat dumps
Add support for partial stat dumps by passing an optional 'root' keyword argument to m5.stats.dump(). Specifying root slightly changes the semantics of the dump command. For legacy reasons, gem5 only allows one stat dump per tick. This is likely a limitation introduced as a hack to prevent automatic dumping at the end of simulation from interfering with explicit dumping from a simulation script. This restriction does not apply when specifying a root. However, these stat dumps will still prevent an additional stat dump in the same tick with an unspecified root.
N.B.: This new API /only/ works for new-style stats that have an explicit hierarchy. Legacy stats will not be dumped if a root is specified.
Change-Id: Idc8ff448b9f70a796427b4a5231e7371485130b4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19369 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14205:197360deaa20 |
26-Jun-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
stats: Add support for hierarchical stats
This change makes the stat system aware of the hierarchical nature of stats. The aim is to achieve the following goals:
* Make the SimObject hierarchy explicit in the stat system (i.e., get rid of name() + ".foo"). This makes stat naming less fragile and makes it possible to implement hierarchical formats like XML/HDF5/JSON in a clean way.
* Make it more convenient to split stats into a separate struct/class that can be bound to a SimObject. This makes the namespace cleaner and makes stat accesses a bit more obvious.
* Make it possible to build groups of stats in C++ that can be used in subcomponents in a SimObject (similar to what we do for checkpoint sections). This makes it easier to structure large components.
* Enable partial stat dumps. Some of our internal users have been asking for this since a full stat dump can be large.
* Enable better stat access from Python.
This changeset implements solves the first three points by introducing a class (Stats::Group) that owns statistics belonging to the same object. SimObjects inherit from Stats::Group since they typically have statistics.
New-style statistics need to be associated with a parent group at instantiation time. Instantiation typically sets the name and the description, other parameters need to be set by overriding Group::regStats() just like with legacy stats. Simple objects with scalar stats can typically avoid implementing regStats() altogether since the stat name and description are both specified in the constructor.
For convenience reasons, statistics groups can be merged into other groups. This means that a SimObject can create a stat struct that inherits from Stats::Group and merge it into the parent group (SimObject). This can make the code cleaner since statistics tracking gets grouped into a single object.
Stat visitors have a new API to expose the group structure. The Output::beginGroup(name) method is called at the beginning of a group and the Output::endGroup() method is called when all stats, and sub-groups, have been visited. Flat formats (e.g., the text format) typically need to maintain a stack to track the full path to a stat.
Legacy, flat, statistics are still supported after applying this change. These stats don't belong to any group and stat visitors will not see a Output::beginGroup(name) call before their corresponding Output::visit() methods are called.
Change-Id: I9025d61dfadeabcc8ecf30813ab2060def455648 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19368 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
14151:1c08ca99b7f2 |
09-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
python: FdtState using interrupt-cells
Change-Id: I37813748f518b442d2b53c2bc4f381edb2e26146 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20050 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14061:bd3e8e7a983d |
04-Jun-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Add support for exporting static class methods from c++
This change adds support for exporting static methods in a c++ SimObject from the coressponsing python wrapper class. This will allow us to define and use c++ methods without the need to instantiate an object of the corresponding class.
Change-Id: Iaf24c1aa6f20feb5c91241f46ec8db005a6a0c0c Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19168 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
14060:84e06ed846ea |
31-Oct-2018 |
Tiago Muck <tiago.muck@arm.com> |
misc: dot_writer fixup
In large configs the tooltip may be greater then the maximum line size graphviz supports when parsing the dot file (typically 16k). Adding '/' causes graphviz to break the string in multiple lines while parsing and works around this limitation.
Change-Id: I16a0030127de4165080de97f5213309eed9fdeca Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19208 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14059:82b702b877df |
13-Jun-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Fix AddrRange legacy ParamValue wrapper
This change fixes a bug that would manifest if a user would instantiate an AddrRange ParamValue using the kwargs 'intlvBits' and 'intlvHighBit' without specifying the optional 'xorHighBit'.
Change-Id: I2091c432234df9cf907d52af6ba7f0cadd8c37a8 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19248 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14052:8e23338327aa |
07-Jun-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Fix cxx_ini_parse for ScopedEnum
Change-Id: I69534bbbc16b2d24a65fa1dee4926f213c3618ef Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19152 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14049:b9aea12fc52c |
26-May-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Add binding for the new AddrRange c++ constructor
Change-Id: I5b3fb59a11d8587a753759310dd3b2748ac13a0b Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19132 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14047:91279ed7ec5e |
26-May-2019 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
base: Extend AddrRange to support more flexible addressing
Previously an AddrRange could express interleaving using a number of consecutive bits and in additional optionally a second number of consecutive bits. The two sets of consecutive bits would be xored and matched against a value to determine if an address is in the AddrRange. For example:
sel[0] = a[8] ^ a[12] sel[1] = a[9] ^ a[13] where sel == intlvMatch
This change extends AddrRange to allow more flexible interleavings with an abritary number of set of bits which do not need be consecutive. For example:
sel[0] = a[8] ^ a[11] ^ a[13] sel[1] = a[15] ^ a[17] ^ a[19] where sel == intlvMatch
Change-Id: I42220a6d5011a31f0560535762a25bfc823c3ebb Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19130 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
13992:05f4102a536f |
31-Oct-2018 |
Tiago Muck <tiago.muck@arm.com> |
misc: Added dot_writer for Ruby's network topology
Change-Id: Ic71ca7bc2eb4174d70afa368bc9cc987f3df89e9 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17548 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13892:0182a0601f66 |
22-Apr-2019 |
Gabe Black <gabeblack@google.com> |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com> |
13891:b92919e5fb16 |
16-Apr-2019 |
Gabe Black <gabeblack@google.com> |
python: Get rid of the VectorPort constructor.
The only thing it was doing beyond calling the parent Port __init__ was to set isVec, and nobody actually looks at that value later.
Change-Id: I567cb583e6f02a6c18504b9bb20dd13b3c934822 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18175 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13890:564dee39e58e |
15-Apr-2019 |
Gabe Black <gabeblack@google.com> |
python: Replace the Master/Slave Ports with Request/Response ports.
These are a little more descriptive and a little less potentially offensive.
Change-Id: I84c30f783f0a4c242cb4f54ab272b6fdf1e9eec7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13871:ab1644706e11 |
16-Apr-2019 |
Gabe Black <gabeblack@google.com> |
python: Generalize the Port.splice function.
Now that the MASTER and SLAVE roles aren't special, the splice function needs to be able to handle arbitrarily role-d peers.
Change-Id: I22a28b7cdcb93f7f370730b7e38b0e6d3500a6a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13870:2536e3a4b58d |
16-Apr-2019 |
Gabe Black <gabeblack@google.com> |
python: Generalize the dot_writer to handle non Master/Slave roles.
Change-Id: I6d93c28e754c0cacacdd5e8885c45bc861135e94 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18169 Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13869:cd9d6b36ded0 |
15-Apr-2019 |
Gabe Black <gabeblack@google.com> |
python: Make Port roles a more generic concept.
A recent change got rid of the strict Master => Slave port relationship which used to be checked in python and instead left the checking up to C++. One major downside to this approach is that it was no longer obvious in the configuration what was supposed to be connected to what, and it still left the arbitrary and misleading MasterPort and SlavePort types in the Ethernet devices which could now connect with each other symmetrically but couldn't actually connect to an arbitrary MasterPort/SlavePort.
This change exposes the base Port and VectorPort types, and makes them accept a "role" parameter in __init__ which used to be set directly by their subclasses. This role can be any string, and will be used later to check for compatiblity and to give a hint as to what can be connected to what in the SimObject definitions.
To make the checks work with arbitrary compatible pairs, the base Port type now has a class method called compat() which accepts a pair of roles which will become mutually compatible, ie any port with the first role will be allowed to connect to any port with the second role, and vice versa. To be self compatible, the same role should be passed in for both parameters.
To maintain compatibility, the MasterPort and SlavePort types are retained, but now they're nothing special and could have been set up in any arbitrary SimObject .py file. The same is true for MasterVectorPort and SlaveVectorPort.
Also, since we can no longer assume that all edges in the dot graph of the config should start with a port with the MASTER role and end with a port with the SLAVE role, Ports now track an is_source property which says whether the arrow head should be surpressed at that end of the edge representing the connection.
Change-Id: Ifcc6faab05e437ad87cd21f0ba613b09cf21c321 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18168 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
13868:b990dd40cc4b |
15-Apr-2019 |
Ciro Santilli <ciro.santilli@arm.com> |
python: fix tracing after Python 3 refactor
gem5.opt --debug-flags ExecAll
was failing with:
ImportError: No module named defines
on Python 2.
Change-Id: I06959d6e0ccb7c661c7c749af3392632dac779f3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18108 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13804:f53a9c35b287 |
20-Mar-2019 |
Isaac Sánchez Barrera <isaac.sanchez@bsc.es> |
base,python: Fix to allow multiple --debug-ignore values.
When adding multiple SimObjects to --debug-ignore, either separating the values with a colon or adding multiple --debug-ignore flags, the previous code only ignored the last SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and `Logger::addIgnore` methods to make the functionality of the flag consistent with its description.
Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
13784:1941dc118243 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary.
Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13783:e9a2fef479e7 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Switch to the new getPort mechanism to connect ports.
This retrieves ports using the getPort method, and connects them using the bind method on the ports themselves. Any smarts as far as what type of peers are allowed to connect or how they connect is left up to the individual bind methods.
Change-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13781:280e5206fd97 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
sim: Add a getPort function to SimObject.
This will retrieve a Port object from a given SimObject (which might not be a MemObject) no matter what flavor of Port it is.
Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13779:acb75141db26 |
06-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Change || to && for MessageBuffers in connectPorts.
The connectPorts function currently checks if *either* of the peers in a port connection are a MessageBuffer, and if so will ignore the connection. This CL changes that || into a && so that *both* of the peers need to be a Ruby types (either a MessageBuffer or Network) for the connection to be ignored. That makes it easier to contain that abnormal behavior to those types instead of having it apply even when other types of port owners are involved.
Unfortunately the number of interesting Ruby types is unbounded, but these are the types with ports as of today. This mechanism will hopefully be replacedall together so this should be a temporary issue.
Change-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13778:318f777400e9 |
14-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Improve how templated SimObject classes are handled.
When setting up a SimObject's Param structure, gem5 will autogenerate a header file which attempts to declare the SimObject's C++ type. It has had at least some level of sophistication there where it would pull off the namespaces ahead of the class name and handle them properly, but it didn't know how to handle templates.
This change improves that handling in two ways. First, it adds a new magical SimObject attribute called 'cxx_template_params' which is used to specify what the template parameters are as a list. For instance, if your SimObject was a template which took an integer constant as its first parameter and a type as its second, this attribute could look like the following:
cxx_template_params = [ 'int FOO', 'class Bar' ]
Importantly, if there are any default values for these template parameters, they should *not* be included here, they should be specified where the class is later defined.
The second new mechanism is to add an internal CxxClass in the SimObject.cxx_param_decl method. This class accepts the class signature in the cxx_class attribute and the cxx_template_params and does two things. First, it strips off namespaces like in the old implementation. Second, it extracts and processes any template arguments attached to the class. If these are constants (as determined by the contents of cxx_template_params), then they are stored verbatim. If they're types, then they're recursively expanded into a CxxClass and stored that way. Note that these are the *values* of the template arguments, where as cxx_template_params lists the *types* and *names* of those arguments. In our earlier example, if cxx_class was:
cxx_class = 'CoolClasses::ClassName<12, Fruit::Apple>'
Then CxxClass would extract the namespace 'CoolClasses', the class name 'ClassName', the argument '12', and the argument 'Fruit::Apple'. That second argument would be expanded into a CxxClass with the namespace 'Fruit' and the class name 'Apple'.
Importantly here, because there were no default arguments given in cxx_template_params, all "hidden" arguments which would fall through to their defaults need to be fully specified in cxx_class.
The CxxClass has a method called declare() which uses the information extracted earlier to output all of the "stuff" necessary for declaring the given class, including opening any containing namespaces and putting template<...> ahead of the actual class declaration with the template parameters specified.
If any of the template arguments are themselves CxxClass instances, then they'll be recursively declared immediately before the current class is.
An alternative solution to this problem might be to include the header file which actually defines the cxx_class type to avoid having to come up with a declaration. Unfortunately this doesn't work since it can set up include loops where the SimObject C++ header file includes the param header to get access to the Param type, but that includes the C++ header to get access to the SimObject type.
This also makes it harder for SimObjects to refer to each other, since they rely on the declaration in the params header files when declaring a member pointer to that type in their own Param structures.
Change-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
13768:0fa3580c1765 |
06-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Simplify connectPorts() around EtherObject/EtherDevice.
EtherDevice now inherits EtherObject and shares the same getEthPort virtual function, so there's no need to treat them separately any more.
Change-Id: Ia6c147fd97fece4a281c296521a7b095f793d32e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17030 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13764:1647bbdc9444 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Teach cxxMethod how to set return_value_policy.
This is passed through to the underlying call to PyBindMethod.
Change-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13763:1adc93bf6a65 |
07-Mar-2019 |
Gabe Black <gabeblack@google.com> |
python: Teach PyBindMethod how to set return_value_policy.
Change-Id: Ia208e43672672556b36f905e8f71dce44b978d22 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13761:cf2082775e86 |
07-Mar-2019 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
python: Fix unknown params and proxy multiplication
One of the recent changes made params not visible anymore: NameError: global name 'params' is not defined This is fixed by adding the proper import statement.
However, the second error makes the multiplication values be assigned to other proxies (that are not even used on the multiplication). A workaround is added to prevent this from happening by extending "*=".
Change-Id: I3ad276a456efff62058672d16caac2b3ad1b326b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13742:9bc48e81b57e |
27-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix issue when Self proxy resolves to a another proxy
The problem occurs when a proxy is being resolved to another proxy that hasn't been resolved yet. The problematic case that was triggering this issues in the VGIC. It was caused by parameters looking a bit like this:
gic = Param.GicV2(Parent.any) some_param = Param.Int(Self.gic.some_param)
When 'some_param' was resolved, it found the 'gic' parameter in Self. However, that parameter hadn't been resolved yet, so the existing code was setting the proxy evaluation context to the unresolved Parent.any proxy without first unproxying it.
It seems like this bug depends on the graph traversal order and I have so far only seen it when compiling gem5 with Python 3.
Change-Id: Iea12cc138765e70bfd6bb776b1efa012364db066 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16004 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13730:2c34d4c9089b |
13-Feb-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
scons: Marshal Python sources using the same Python as gem5
We currently use the Python version used by scons to marshal Python code. This doesn't work when building gem5 with Python 3 support since scons typically runs in Python 2.7. Add a custom marshal helper that links with the same library as gem5 to generate byte code that is guaranteed to work in gem5's Python interpreter.
Change-Id: I665b0f2078726d4c055d74a3e668a580fc613b59 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16422 Reviewed-by: Gabe Black <gabeblack@google.com> |
13724:63e550c8ffe2 |
20-Feb-2019 |
Gabe Black <gabeblack@google.com> |
systemc: Add m5.systemc and m5.tlm python modules.
These will be how systemc and tlm APIs which are not attached to SimObjects will be exposed. This avoids having to artificially attach them to wrapping SimObjects for instance, which is a bit awkward and non-obvious.
The python code which attaches the systemc and tlm modules to the m5 modules lives in src/python/m5/__init__.py, but the modules themselves live in src/systemc/python to keep all the systemc code grouped together. It might be a little confusing to have a small part of the glue that adds those modules in a separate place (__init__.py), but that is, as far as I can tell, unavoidable, and it's better in my opinion to keep the systemc code grouped together than to put it alongside the other python code and __init__.py.
Change-Id: Iecb218daec5e15772152b5ad22b51f43b86c3d4b Reviewed-on: https://gem5-review.googlesource.com/c/16563 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> |
13720:18f5d3990ac9 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Stop using basestring to test for strings
The base class basestring doesn't exist in Python 3. Use string_types from six instead.
Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15998 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> |
13719:74853963ddcf |
25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add Python 3 workarounds for long
Python 3 doesn't have a separate long type. Make long an alias for int where needed to maintain compatibility.
Change-Id: I4c0861302bc3a2fa5226b3041803ef975d29b2fd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15988 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13716:950f9a2ffb78 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix params/proxy import loop
There is a circular dependency between params and proxy at import time. This causes issues for Python 3. Add the imports to the specific methods with the dependencies to make the import happen when the method is executed instead.
Change-Id: I770112fd3c07c395459e204976942bda3dc7236f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15993 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> |
13714:35636064b7a1 |
25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Enforce absolute imports for Python 3 compatibility
Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15983 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
13712:e36f980fdc36 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add fallbacks for packages that have been renamed
Python 3 has restructured some packages. Specifically, __builtin__ has been renamed to builtins and urlparse has been included in urllib.
Change-Id: I81f8f3942471db1043006a36abbad6e5a49e0a43 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15994 Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> |
13711:e796a82c5154 |
27-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix param -> int conversion issues
Python 3 doesn't convert params to integers automatically in range(). Add __index__ to CheckedInt to enable implicit conversions again. Add explicit conversions where necessary.
Change-Id: I2de6c9906d3bb7616f12ada6728b9e4b1928511c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16000 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13709:dd6b7ac5801f |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Make iterator handling Python 3 compatible
Many functions that used to return lists (e.g., dict.items()) now return iterators and their iterator counterparts (e.g., dict.iteritems()) have been removed. Switch calls to the Python 2.7 iterator methods to use the Python 3 equivalent and add explicit list conversions where necessary.
Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15992 Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13708:ddebb8202119 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add missing operators to NumericParamValue
Add missing operators to NumericParamValue and ensure that they are able to work on the underlying value if the right hand side is a param.
Change-Id: I2bd86662aee9891bbd89aed7ebe20b827b5528bd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16001 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13699:2583bda9b2d8 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix Param initialization issue in Python 3
When initializing a param with a SimObject NULL pointer, convert() checks if the 'ptype' attribute has been created and whether the value is NULL. In that case, it assumes that the object is being initizalized as a part of SimObject initialization and defers the conversion. This check is implemented using hasattr() which in turn is implemented using the __getattr__ implementation that asserts because all SimObjects haven't been initialized yet.
Implement the check using a lookup in the object's dictionary instead to prevent the SimObject lookup.
Change-Id: I7367563c4fb71f6d2be541ebdc0be418e9f73d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15990 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13698:bc371875a67c |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Use __name__ instead of func_name for Py3 compat
Change-Id: I62a9685b4bce7e9012bc65309fcafe26135fde6d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15997 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13697:8d4afe1c365e |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add __bool__ helpers in addition to __nonzero__
Python 3 uses __bool__ instead of __nonzero__ when performing a Boolean comparison.
Change-Id: I85185bbe136ecae67346fa23569e24edd7329222 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13696:b303ca652433 |
15-Feb-2019 |
Gabe Black <gabeblack@google.com> |
config: Make parameter conversion handle integers in other bases.
Python's float() function/type can't handle hexadecimal notation, but int() can. Since there are also cases where converting to a float and then back to an int (or long) can cause rounding error, this change splits toFloat and toInteger apart and makes them call a worker function which accepts a conversion function which does the work of converting a numeric string into an actual number.
in the case of toFloat, it still uses the standard float(), and in the case of toInteger it uses a lambda which wraps int(x, 0).
Change-Id: Ic46cf4ae86b7eba6f55d731d1b25e3f84b8bb64c Reviewed-on: https://gem5-review.googlesource.com/c/16504 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13683:7a688f15e7b5 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Remove uses of tuple unpacking in function params
Python 3 doesn't support tuple unpacking in function parameters and lambdas.
Change-Id: I36c72962e33a9ad37145089687834becccc76adb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15991 Reviewed-by: Gabe Black <gabeblack@google.com> |
13682:907a4f6c8435 |
25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Replace deprecated repr syntax
Change-Id: I5f9538cf2ca5ee17c51e7c5388d3aef363fcfa54 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13681:9e8e1a96c423 |
26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Switch from using compare to key in list sort
Python 3 has deprecated the use of a comparison function in favour of a key extraction function.
Change-Id: I4b7eab791ecbdfbf7147f57fdbc7cbe8f1de20dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15995 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13675:afeab32b3655 |
24-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Replace dict.has_key with 'key in dict'
Python 3 has removed dict.has_key in favour of 'key in dict'.
Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13674:45580dbf73a9 |
12-Feb-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add missing defines import
The _check_tracing helper function in main.py depends on defines to check if tracing has been enabled at compile time. This module is imported in main() but not at the module level, which breaks this function.
Change-Id: I26d65a4320da8618e0e552553695884fd2c880e0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16402 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13673:a85a40c48435 |
24-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Replace DictMixin with Mapping / MutableMapping
Python 3 has removed support for DictMixin, so switch to Mapping / MutableMapping in collections which provides the same functionality.
Change-Id: I61fbe366d2c9fc6e01b470f82f49cc02b99dec32 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13672:2969e4d5abf4 |
12-Feb-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Replace orderdict with collections.OrderedDict
Python 2.7 and newer has support for ordered dictionaries in the standard library. Remove this custom class.
Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16362 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13671:b288ca1bcae8 |
24-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Update use of exec to work with Python 3
Python 3 uses 'exec(code, globals)' instead of 'exec code in globals'. Switch to the newer syntax since it is supported by Python 2.7. Also, move check_tracing out of main to work around a bug in Python 2.7.
Change-Id: I6d390160f58783e1b038a572b64cdf3ff09535fa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13670:8a98db5a481f |
24-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Switch to using open instead of file
Python 3 doesn't support the file(name, mode) syntax which has been deprecated in favour of open.
Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15985 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13663:9b64aeabf9a5 |
25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Make exception handling Python 3 safe
Change-Id: I9c2cdfad20deb1ddfa224320cf93f2105d126652 Reviewed-on: https://gem5-review.googlesource.com/c/15980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> |
13621:ae14904aa87b |
28-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Remove getCode() type workaround
Python 2.7 requires a workaround when wrapping exit objects to explicitly convert the return of getCode() to int to not confuse sys.exit. This workaround isn't needed and doesn't work on Python 3 since it doesn't have a separate long integer type.
Change-Id: I57bc3fd8f4699676c046ece8a52baa2796959ffd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15978 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
13594:441bb7a7b2a8 |
02-Jul-2018 |
Nicholas Lindsay <nicholas.lindsay@arm.com> |
python: Always throw TypeError on slave-slave connections
params.py checks the validity of memory port-port connections before they are instantiated in C++. This commit ensures that attempting to connect two slave ports together will cause a TypeError.
Change-Id: Ia7d0a15df28b96c7bf5e568c4f4917d21a19b824 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15896 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13558:2a8d8f64d900 |
24-Dec-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Add support for scoped enums
At the moment gem5 has support for enum params that either generate a unscoped within the Enums namespace or a struct encapsulated enum. The Enums namespace is getting quite big and some params have the same names which results in collisions. This change adds support for the scoped enums.
Change-Id: I930e1cc3b814081627b653939e75d6c43956a334 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15395 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13543:98421d757922 |
11-Jan-2019 |
Gabe Black <gabeblack@google.com> |
config: De-nest the code in Port.splice().
The error checking in that function used an if/else structure where one of the two branches would be the error condition which would cause the function to exit. Because the function would exit if an error was detected, there's no reason to have the non-error condition guarded in the other half of the if.
This change de-nests the non-error cases to make the function simpler and easier to read.
Change-Id: Idedf54e84a178fa5a2a47f96373374152e420cf3 Reviewed-on: https://gem5-review.googlesource.com/c/15516 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13542:5e914b841659 |
11-Jan-2019 |
Gabe Black <gabeblack@google.com> |
config: Fix an error message in Port.splice().
That error message referenced non-existent variables which were likely renamed without updating the error message.
Change-Id: I6878802ef4b83e3fdf75a860d848b8c5e2e8d6c0 Reviewed-on: https://gem5-review.googlesource.com/c/15515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13431:40bbea43ddf7 |
16-Nov-2018 |
Srikant Bharadwaj <srikant.bharadwaj@amd.com> |
sim: Fix data type of ticks per second before passing it to C++
Casts ticks per second value to int before passing it to C++. Python throws an error because of incompatible type because of the recent change.
Change-Id: Ibcaf8c327f1be0dba38763975d389584addd8373 Reviewed-on: https://gem5-review.googlesource.com/c/14375 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
13409:071d5425ce37 |
07-Nov-2018 |
Gabe Black <gabeblack@google.com> |
sim: Push the global frequency management code into C++.
That makes it available when python is left out, and makes it available to c++ code without having to call back into python.
Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2 Reviewed-on: https://gem5-review.googlesource.com/c/14055 Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13356:913658aa619c |
13-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
python: Add utility function to override config parameters
Add a utility method, SimObject.apply_config that can be used to implement SimObject param overrides from the command line. This function provides safe and convenient semantics for CLI assignment:
* The override expression is evaluated in a restricted environment. The only global variables are the child objects and params from the root object.
* Only params can be overridden. For example, calling methods or setting attributes on SimObjects isn't possible.
* Vectors use non-standard list semantics which enable something similar to glob expansion on the shell. For example, setting:
root.system.cpu[0:2].numThreads = 2
will override numThreads for cpu 0 and 1 and:
root.system.cpus[0,2].numThreads = 2
sets it for cpus 0 and 2.
The intention is that the helper method is called to override default values before calling m5.instantiate.
Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799 Reviewed-on: https://gem5-review.googlesource.com/c/12984 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13341:51d9fa5096b4 |
11-Oct-2018 |
Gabe Black <gabeblack@google.com> |
python: Stop conditionally excluding code from pyobject.cc
Now that the Ether* classes are included in all builds, there's no reason to conditionally compile code in pyobject.cc.
Change-Id: If94602af71774b1f090a3344a633207f4b37d308 Reviewed-on: https://gem5-review.googlesource.com/c/13470 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12805:3c900ca6be0a |
02-May-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix call bug in @cxxMethod when override is True
Change-Id: Ifa9efbd329fd01eb13100bc6690e651df2c12294 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11514 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12803:a08f441d4d4c |
27-Apr-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fixup incorrect syntax in PyBind argument handler
Change-Id: Ie81104d89b554795ec1020d5ce4edcf28795eda8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12798:d9fc94b42670 |
22-Jun-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Add support for multiplying proxies to compatible Param
Previously we allowed multiplications between proxy Param and compatible constants (int, long, float). This change extends this functionality and adds support for multiplying with between proxy Param and compatible proxy Param.
Change-Id: I23a083881ae4d770e818895b893534767cd2472d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11510 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12786:e3a5c978e7d1 |
05-Jun-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Use the canonical way of iterating over a dictionary
Instead of using a convoluted getattr call, use the conventional iteritems() interface.
Change-Id: I6d6bbccf865f8a0e8ff0767914157a7460099b09 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10782 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12770:42f6afaab313 |
01-May-2018 |
Gabe Black <gabeblack@google.com> |
sim: Add a SimObject python field which overrides the default c++ base.
The base for the c++ version of python SimObject classes is normally inferred from the c++ version of the python base. There are some specific cases where that isn't desired. This change makes it possible to override the default behavior.
Change-Id: I2438dad767e2f56823bad42b3e6c7714ce97ef79 Reviewed-on: https://gem5-review.googlesource.com/10662 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
12742:a48daf1c7e56 |
01-May-2018 |
Gabe Black <gabeblack@google.com> |
sim: Rename the SimObject cxx_bases field to cxx_extra_bases.
cxx_bases adds in additional c++ base classes beyond those implied by the python SimObject inheritance hierarchy. To imply the fact that these are additional bases, and to disambiguate a future mechanism which changes the implied bases, this flag/field is being renamed from cxx_bases to cxx_extra_bases.
As far as I can tell, this field was only used internally in SimObject.py.
Change-Id: Ie7cc3d0107ff71cc31424d6e20c9a2f430022ab9 Reviewed-on: https://gem5-review.googlesource.com/10661 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12563:8d59ed22ae79 |
06-Mar-2018 |
Gabe Black <gabeblack@google.com> |
scons: Switch from the print statement to the print function.
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files.
Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12469:ea3fefba5a72 |
16-Dec-2015 |
Glenn Bergmans <glenn.bergmans@arm.com> |
arm: DT autogeneration - Device Tree generation methods
This patch adds an extra layer to the pyfdt library such that usage gets easier and device tree nodes can be specified in less code, without limiting original usage. Note to not import both the pyfdt and fdthelper in the same namespace (but generally fdthelper is all you need, because it supplies the same classes even when they are not extended in any way)
Also, this patch lays out the primary functionality for generating a device tree, where every SimObject gets an empty generateDeviceTree method and ArmSystems loop over their children in an effort to merge all the nodes. Devices are implemented in other patches.
Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5962 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12468:b4b8bdb9712a |
16-Dec-2015 |
Glenn Bergmans <glenn.bergmans@arm.com> |
ext: DT autogeneration - Add PyFtd to m5 space
This patch adds pyfdt.py to the m5.ext module. This is used in succeeding patches for generating and editing dtb files and flat device trees for DT autogeneration.
The file is in the m5_root/src/python/m5/ext directory, as opposed to the m5_root/ext, because this library is part of the m5 object space and linking to the m5_root/ext directory from the SConscript file in src/python can not be done reliably. Linking from the root level SConscript is also not an option, because it doesn't have the PySource method defined.
Cloned from: https://github.com/superna9999/pyfdt Commit: accbcd254584c9295a18878d32999d0c7c156f8e Version: 0.3
Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5961 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12334:e0ab29a34764 |
30-Nov-2017 |
Gabe Black <gabeblack@google.com> |
misc: Rename misc.(hh|cc) to logging.(hh|cc)
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.).
Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> |
12302:5771c4c65b23 |
18-Nov-2017 |
Gabe Black <gabeblack@google.com> |
scons: Switch from "guards" to "tags" on source files.
Tags are just arbitrary strings which are attached to source files which mark them as having some property. By default, all source files have the "gem5 lib" tag added to them which marks them as part of the gem5 library, the primary component of the gem5 binary but also a seperable component for use in, for example, system C.
The tags can be completely overridden by setting the "tags" parameter on Source, etc., functions, and can be augmented by setting "add_tags" which are tags that will be added, or alternatively additional tags. It's possible to specify both, in which case the tags will be set to the union of tags and add_tags. add_tags is supposed to be a way to add extra tags to the default without actually overriding the default. Both tags and add_tags can be a list/tuple/etc of tags, or a single string which will be converted into a set internally.
Other existing tags include: 1. "python" for files that need or are used with python and are excluded when the --without-python option is set 2. "main" for the file(s) which implement the gem5 binary's main function. 3. The name of a unit test to group its files together. 4. Tags which group source files for partial linking.
By grouping the "tags" into a single parameter instead of taking all extra parameters as tags, the extra parameters can, in the future, be passed to the underlying scons environment. Also, the tags are either present or not. With guards, they could be present and True, present and False, or not present at all.
Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2 Reviewed-on: https://gem5-review.googlesource.com/5822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12253:6e1d5605e82e |
10-Nov-2017 |
Gabe Black <gabeblack@google.com> |
config: Add an Energy param type.
This type expects values in joules (J).
Change-Id: I77a3a4f1c19443f573d5fe7a84d5abd954ce1603 Reviewed-on: https://gem5-review.googlesource.com/5625 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12252:981c156ecdde |
10-Nov-2017 |
Gabe Black <gabeblack@google.com> |
config: Export the "Current" param type from m5.params.
This type was defined, but it was never added to __all__.
Change-Id: I5414829a9562790416f5ceab71af01503d142903 Reviewed-on: https://gem5-review.googlesource.com/5624 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12251:5c3d3a1db483 |
10-Nov-2017 |
Gabe Black <gabeblack@google.com> |
util: Add a "toEnergy" function to the convert module.
Change-Id: I7299af0e2a6ce9bd2272d6ccb898997336e95e51 Reviewed-on: https://gem5-review.googlesource.com/5623 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12250:d69d0f27049d |
10-Nov-2017 |
Gabe Black <gabeblack@google.com> |
config: Simplify the definitions of the Voltage and Current params.
These had a lot of code which duplicated what was already in the Float param value class. Also, printing into the ini file with "%f" forces python to truncate values which require more precision than the fixed float format supports.
Change-Id: Iad9623b71a31d17b69c184082585dcbb881eaa20 Reviewed-on: https://gem5-review.googlesource.com/5622 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12247:c627617910e8 |
10-Nov-2017 |
Gabe Black <gabeblack@google.com> |
util: Simplify/consolidate the python conversion module.
The python conversion module was really repetitive and fragmented, where some types of conversions use common code, and some use hand written case statements which did something very similar. Also, some types like Voltage could only handle V and mV but no other scaling prefix.
This change restructures the module to centralize a lot of the unit handling code into toFloat, and makes the various other functions use it.
Change-Id: Ic8529203cc226c9b551b8535a444e3f2f25ad1eb Reviewed-on: https://gem5-review.googlesource.com/5621 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12202:e193ae9884e5 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
util: Make dot_writer ignore NULL simobjects.
Also centralize the code which iterates over the parameters of a simnode's children, and remove a copy/paste block of code in the DVFS block of code.
Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d Reviewed-on: https://gem5-review.googlesource.com/4849 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12200:d805bc7859b2 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Add a get_config_as_dict to the NullSimObject class.
Change-Id: I1ba6f6b196b7dfa790d1baaa23640bb3ed73f450 Reviewed-on: https://gem5-review.googlesource.com/4847 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12199:f21e7e704ffd |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Don't add the NULL SimObject as a child of other SimObjects.
Change-Id: Ibdc48af8e5a461077f75d781cfd8191586c54115 Reviewed-on: https://gem5-review.googlesource.com/4846 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12197:5e4f0d7da198 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Give the NullSimObject singleton a _name.
The name is 'Null', and is what __str__ returns.
Change-Id: I113f52496f5e9133b8d03206289b719fda003582 Reviewed-on: https://gem5-review.googlesource.com/4845 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12196:4c1449b32810 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Add a NullSimObject.descendants function.
Null simobjects don't have any descendants.
Change-Id: Ia43a99056709f422c9c817c017912d23d689fb1e Reviewed-on: https://gem5-review.googlesource.com/4844 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12195:9c4bcb804f81 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Add a clear_parent function to NullSimObject.
Change-Id: I3842176f147997105fcc62aaf9cb93b9896708be Reviewed-on: https://gem5-review.googlesource.com/4843 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12194:742ec08ee956 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Check the SimObjectVector.has_parent function to use the "any" function.
The existing code was essentially doing the same thing, but in a more roundabout and obscure way. One difference between the two versions is that I believe this will stop as soon as it encounters an element without a parent, where the original version would call has_parent() on all the elements regardless.
Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695 Reviewed-on: https://gem5-review.googlesource.com/4842 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12193:ae90e2b82531 |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Only consider non-NULL elements in SimObjectVector.has_parent.
NullSimObject doesn't have a has_parent function, and it's not clear what its return value should be if one were added. The appropriate value seems to depend on why some other bit of code is checking if there's a parent in the first place.
In SimObjectVector, the has_parent function is checking whether all of its elements have a parent. In this particular case, the most reasonable thing to do seems to be to just skip those elements.
Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8 Reviewed-on: https://gem5-review.googlesource.com/4841 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12192:23f2cd72a63e |
25-Sep-2017 |
Gabe Black <gabeblack@google.com> |
sim: Add a set_parent to NullSimObject which does nothing.
This lets attempts to set_parent on NullSimObject fall away harmlessly without having to add a bunch of checks whenever set_parent is called.
Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11 Reviewed-on: https://gem5-review.googlesource.com/4840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> |
12172:33b5ccf51d7f |
31-Jul-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Make GlobalExitEvent.getCode() return an int
PyBind normally casts integers returned from the C to long in Python. This is normally fine since long in most cases behaves just like an int. However, when passing the return value from getcode() to sys.exit, unexpected behavior ensues. Due to the way the function is defined, any type other than int (with the exception of None) will be treated as an error and be equivalent to sys.exit(1).
Since we frequently use the sys.exit(event.getCode()) pattern, we need to ensure that the function returns an integer. This change adds an explicit type conversion to a Python integer in the wrapper code.
Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jose Marinho <jose.marinho@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4280 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joe.gross@amd.com> |
12050:d42eab4e6323 |
23-Mar-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
python: Fix unproxing of VectorParams
Previously proxy vector parameters would resolve correctly only for Parent.all. Any other proxy such as Parent.any, or exact ones such as Parent.addr_range would resolve to a *vector* of the right value resulting into a vector of a vector. For example if we set:
DirectoryController0.addr_range = [0x100000-0x1fffff, 0x200000-0x2fffff] DirectoryMemory0.addr_range = Parent.addr_range
where DirectoryController0 is the parent SimObject of DirectoryMemory0 after unproxying the Parent.addr_range VectorParam we would get
DirectoryMemory0.addr_range = [[0x100000-0x1fffff, 0x200000-0x2fffff]]
This change unifies handling of all three proxies to the same correct unproxy mechanism.
Change-Id: Ie5107f69f58eb700b3e1b92c55210e0d53e6788d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2901 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12041:52b3b120dbc0 |
10-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix PyEvent reference counting bug
The current implementation of reference counting for PyEvents only partially works. The native object is currently kept alive while it is in the event queue. However, if the Python object goes out of scope, the Python side of this object is garbage collected which leaves a "dangling" native object. This results in confusing error messages where PyBind is unable to find the Python implementation of an event when it is triggered.
Implement reference counting using the generalized reference counting API instead.
Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3222 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12036:634fbd07bc88 |
09-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Prevent Python wrappers from deleting SimObjects
The PyBind wrappers could potentially delete SimObjects if they don't have any references. This is not desirable since there could be pointers to such objects within the C++ world. This problem doesn't normally occur since Python typically holds a pointer to the root node as long as the simulator is running.
Prevent SimObject and Param deletion by using a PyBind-prescribed unique_ptr with a dummy deleter as the pointer wrapper for the Python world.
Change-Id: Ied14602c9ee69a083a69c5dae1b5fcf8efb4548a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3224 Reviewed-by: Gabe Black <gabeblack@google.com> |
12035:7b8e1b36875d |
10-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix weird memory issue in wrapped AddrRange vectors
There is a weird issue with the PyBind wrapper of vector<AddrRange>. Assigning new values to a param that is a vector of AddrRange sometimes results in an out-of-bounds memory access.
We work around this issue by treating AddrRange vectors as opaque types. This slightly changes the semantics of the wrapper since Python now manipulates the real object rather than a copy that has been converted to a list.
Change-Id: Ie027c06e7a7262214b43b19a76b24fe4b20426c5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Timothy Hayes <timothy.hayes@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3223 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12033:2e805c6168ce |
18-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Remove unused readline import
The readline module is imported by main.py but doesn't seem to be used.
Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3421 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
12024:4ae7a812176a |
09-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add a helper function to create Python events
Add a helper function, m5.event.create(), to create events from Python. This function takes a callable Python object (e.g., a function) as an argument and optionally a priority as a keyword argument. This function was accidentally dropped from the public API when switching to PyBind.
Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3220 Reviewed-by: Gabe Black <gabeblack@google.com> |
12023:272819f230c0 |
15-May-2017 |
Brandon Potter <brandon.potter@amd.com> |
style: fix line lengths and include ordering
The style checker complains about line length and ordering for these files. This fix should make these two files kosher.
Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d Reviewed-on: https://gem5-review.googlesource.com/3380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
12012:2991b2c2ffe9 |
05-May-2017 |
Gabe Black <gabeblack@google.com> |
misc: Add the --listener-loopback-only command line option.
This option invokes the Listener::loopbackOnly() static function which will make the port listeners bind to the loopback device exclusively and ignore connections on other devices. That prevents external agents like port scanners from disrupting simulations with spurious connections.
Change-Id: I46b22165046792a6f970826c109bdbce7db25c84 Reviewed-on: https://gem5-review.googlesource.com/3082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12011:1279b1d30ccd |
05-May-2017 |
Gabe Black <gabeblack@google.com> |
misc: Expose the listener loopbackOnly function to python.
Change-Id: Ibb405af54a46a93706a6f476b5314491e84be0c8 Reviewed-on: https://gem5-review.googlesource.com/3081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12008:af9e577f8eac |
08-May-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Fix debug flag listing regression
The PyBind11 changes slightly modified gem5's internal debug interfaces. The corresponding change to the public API went missing before the new bindings were merged. This change updates the Python glue to use the new interface.
Change-Id: I3ecca5a3f6c35b99d55126d697371124f81a12dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11991:d3f19484145f |
29-Jan-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Remove SWIG
Remove SWIG-specific Python code.
Change-Id: If1d1b253d84021c9a8f9a64027ea7a94f2336dff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2922 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> |
11988:665cd5f8b52b |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Use PyBind11 instead of SWIG for Python wrappers
Use the PyBind11 wrapping infrastructure instead of SWIG to generate wrappers for functionality that needs to be exported to Python. This has several benefits:
* PyBind11 can be redistributed with gem5, which means that we have full control of the version used. This avoid a large number of hard-to-debug SWIG issues we have seen in the past.
* PyBind11 doesn't rely on a custom C++ parser, instead it relies on wrappers being explicitly declared in C++. The leads to slightly more boiler-plate code in manually created wrappers, but doesn't doesn't increase the overall code size. A big benefit is that this avoids strange compilation errors when SWIG doesn't understand modern language features.
* Unlike SWIG, there is no risk that the wrapper code incorporates incorrect type casts (this has happened on numerous occasions in the past) since these will result in compile-time errors.
As a part of this change, the mechanism to define exported methods has been redesigned slightly. New methods can be exported either by declaring them in the SimObject declaration and decorating them with the cxxMethod decorator or by adding an instance of PyBindMethod/PyBindProperty to the cxx_exports class variable. The decorator has the added benefit of making it possible to add a docstring and naming the method's parameters.
The new wrappers have the following known issues:
* Global events can't be memory managed correctly. This was the case in SWIG as well.
Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2231 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11923:d2f0605ac2af |
28-Nov-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Automatically disable listeners in batch setups
Determine if gem5 is running in a batch environment by checking if STDIN is wired to a TTY or not. If the simulator is running in a batch environment, disable all listeners by default. This behavior can be overridden using the --enable-listeners option.
Change-Id: I404c709135339144216bf08a2769c016c543333c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sean McGoogan <sean.mcgoogan@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2322 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11880:8c369af31b6c |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
base: Refactor logging to make log level selection cleaner
It's currently possible to change the log level in gem5 by tweaking a set of global variables. These variables are currently exposed to Python using SWIG. This mechanism is far from ideal for two reasons: First, changing the log level requires that the Python world enables or disables individual levels. Ideally, this should be a single call where a log level is selected. Second, exporting global variables is poorly supported by most Python frameworks. SWIG puts variables in their own namespace and PyBind doesn't seem to support it at all.
This changeset refactors the logging code to create a more abstract interface. Each log level is associated with an instance of a Logger class. This class contains common functionality, an enable flag, and a verbose flag.
Available LogLevels are described by the LogLevel class. Lower log levels are used for more critical messages (PANIC being level 0) and higher levels for less critical messages. The highest log level that is printed is controlled by calling Logger:setLevel().
Change-Id: I31e44299d242d953197a8e62679250c91d6ef776 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11878:f9e3be6b1634 |
27-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Add a generalized mechanism to configure stats
Add a mechanism to configure the stat output format using a URL-like syntax. This makes it possible to specify both an output format (currently, only text is supported) and override default parameters.
On the Python-side, this is implemented using a helper function (m5.stats.addStatVisitor) that adds a visitor to the list of active stat visitors. The helper function parses a URL-like stat specification to determine the stat output type. Optional parameters can be specified to change how stat visitors behave.
For example, to output stats in text format without stat descriptions:
m5.stats.addStatVisitor("text://stats.txt?desc=False")
From the command line:
gem5.opt --stats-file="text://stats.txt?desc=False"
Internally, the stat framework uses the _url_factory decorator to wrap a Python function with the fn(path, **kwargs) signature in a function that takes a parsed URL as its only argument. The path and keyword arguments are automatically derived from the URL in the wrapper function.
New output formats can be registered in the m5.stats.factories dictionary. This dictionary contains a mapping between format names (URL schemes) and factory methods.
To retain backwards compatibility, the code automatically assumes that the user wants text output if no format has been specified (i.e., when specifying a plain path).
Change-Id: Ic4dce93ab4ead07ffdf71e55a22ba0ae5a143061 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> |
11827:7788325d6855 |
10-Feb-2017 |
Jason Lowe-Power <jason@lowepower.com> |
misc: Add Python.h header to pyevents.hh
Signed-off-by: Jason Lowe-Power <jason@lowepower.com> |
11808:f254d8a17da9 |
07-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
style: Force Python.h to be included before main header
Python's header files set various compiler macros (e.g., _XOPEN_SOURCE) unconditionally. This triggers preprocessor warnings that end up being treated as errors. The Python integration manual [1] strongly recommends that Python.h is included before any system header. The style guide used to mandate that Python.h is included first in any file that needs it. This requirement was changed to always include a source file's main header first, which ended up triggering these errors.
This change updates the style checker to always include Python.h before the main header file.
[1] https://docs.python.org/2/extending/extending.html
Change-Id: Id6a4f7fc64a336a8fd26691a0ca682abeb1d1579 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> |
11802:be62996c95d1 |
26-Jan-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Move native wrappers to the _m5 namespace
Swig wrappers for native objects currently share the _m5.internal name space with Python code. This is undesirable if we ever want to switch from Swig to some other framework for native binding (e.g., PyBind11 or Boost::Python). This changeset moves all of such wrappers to the _m5 namespace, which is now reserved for native code.
Change-Id: I2d2bc12dbc05b57b7c5a75f072e08124413d77f3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11800:54436a1784dc |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include. |
11793:ef606668d247 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes |
11788:342c0eaab188 |
02-Jan-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Don't use Swig to cast stats
Call the stat visitor from the stat itself rather than casting stats in Python. This reduces the number of ways visitors are called.
Change-Id: Ic4d0b7b32e3ab9897b9a34cd22d353f4da62d738 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Joe Gross <joseph.gross@amd.com> |
11787:af41594e9b3c |
02-Jan-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Remove redundant export_method_cxx_predecls
The headers declared in export_method_cxx_predecls are redundant since a SimObject's main header is automatically included.
Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Joe Gross <joseph.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
11766:7c95caf53250 |
19-Dec-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Export periodicStatDump
Some configuration scripts need periodic stat dumps. One of the ways this can be achieved is by using the pariodicStatDump helper function. This function was previously only exported in the internal name space. Export it as a normal function in m5.stat instead.
Change-Id: Ic88bf1fd33042a62ab436d5944d8ed778264ac98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> |
11635:e92bf392bf43 |
15-Sep-2016 |
Curtis Dunham <Curtis.Dunham@arm.com> |
base: eliminate ipython warning
Change-Id: I3e282baeb969b6bb9534813a2f433d68246c0669 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11621:3e9314ddf012 |
13-Sep-2016 |
Michael LeBeane <michael.lebeane@amd.com> |
misc: Remove FullSystem check for networking components Ethernet devices are currently only hooked up if running in FS mode. Much of the Ethernet networking code is generic and can be used to build non-Ethernet device models. Some of these device models do not require a complex driver stack and can be built to use an EmulatedDriver in SE mode. This patch enables etherent interfaces to properly connect regardless of whether the simulation is in FS or SE mode. |
11620:57f21c16adde |
13-Sep-2016 |
Matt Poremba <Matthew.Poremba@amd.com> |
base: Output all AddrRange parameters to config.ini
Currently only 'start' and 'end' of AddrRange are printed in config.ini. This causes address ranges to be overlapping when loading a c++-only config with interleaved addresses using CxxConfigManger. This patch adds prints for the interleave and XOR bits to config.ini such that address ranges are properly setup with cxx config. |
11498:e0cbca57e1e9 |
27-May-2016 |
Akash Bagdia <akash.bagdia@ARM.com> |
power: Allow voltage to be configured via cmd line
--- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) |
11431:871eaaa0ab24 |
06-Apr-2016 |
Sascha Bischoff <sascha.bischoff@arm.com> |
misc: Bail out of DVFS dot if we cannot resolve the domains
This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes.
Minor fixup for 0aeca8f. |
11418:0aeca8f47eac |
15-Dec-2015 |
Sascha Bischoff <sascha.bischoff@arm.com> |
misc: Add secondary dot output for DVFS domains
This patch adds a secondary dot output file which shows the DVFS domains. This has been done separately for now to avoid cluttering the already existing diagram. Due to the way that the clock domains are assigned to components in gem5, this output must be generated after the C++ objects have been instantiated. This further motivates the need to generate this file separately to the current dot output, and not to replace it entirely. |
11412:1f92ce16e171 |
30-Mar-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
misc: Don't build region.py as a PySource
The style refactor change (style: Refactor the style checker as a Python package) moved region.py from src/python/m5/util/ to util/style/. The SConscript update accidentally got lost in that commit. This commit removes region.py from src/python/SConscript.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11403:e8949ea6961f |
30-Mar-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
style: Refactor the style checker as a Python package
Refactor the style checker into a Python module that can be reused by command line tools that integrate with git. In particular:
* Create a style package in util * Move style validators from style.py to the style/validators.py. * Move style verifiers from style.py to the style/verifiers.py. * Move utility functions (sort_includes, region handling, file_types) into the style package * Move generic code from style.py to style/style.py.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> |
11362:04966a265ff9 |
26-Nov-2015 |
Andreas Sandberg <andreas@sandberg.pp.se> |
sim: Add support for forking
This changeset adds forking capabilities to the gem5 python scripts. A fork method is added to simulate.py. This method is responsible for forking the simulator itself, and will direct all output files to a new output directory based on the fork sequence number. The default name of the output directory is the same as the parent with the suffix ".fN" added where N is the fork sequence number. The fork method provides the option to specify if the system should be drained prior to forking, or not. By default the system is drained to ensure that there are no in-flight transactions.
When forking the simulator, the fork method returns the PID of the child process, or returns 0 if running in the child. This is in line with the standard Python forking interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> [andreas.sandberg@arm.com: Updated to comply with modern draining semantics ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11360:40be59176869 |
26-Nov-2015 |
Andreas Sandberg <andreas@sandberg.pp.se> |
sim: Add support for notifying Drainable objects of a fork
When forking a gem5 process, some objects need to clean up resources (mainly file descriptions) shared between the child and the parent of the fork. This changeset adds the notifyFork() method to Drainable, which is called in the child process.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11359:b0b976a1ceda |
27-Nov-2015 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Add support for changing output directories
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11338:5981f61b8936 |
13-Feb-2016 |
Michael LeBeane <Michael.Lebeane@amd.com> |
configs: add command-line option to stop debug output
This patch adds a --debug-end flag to main.py so that debug output can be stoped at a specified tick, while allowing the simulation to continue. It is useful in situations where you would like to produce a trace for a region of interest while still collecting stats for the entire run. This is in contrast to the currently existing --debug-break flag, which terminates the simulation at the tick. |
11321:02e930db812d |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'. |
11320:42ecb523c64a |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'. |
11304:d06e5a6b4b7f |
17-Jan-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: fix redundant --debug-start help string
Just changes the metavar for --debug-start from TIME to TICK in cset 72046b9b3323 and didn't notice that the comment "must be in ticks" is now redundant. |
11299:72046b9b3323 |
17-Jan-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: don't ignore SIG_TRAP
By ignoring SIG_TRAP, using --debug-break <N> when not connected to a debugger becomes a no-op. Apparently this was intended to be a feature, though the rationale is not clear.
If we don't ignore SIG_TRAP, then using --debug-break <N> when not connected to a debugger causes the simulation process to terminate at tick N. This is occasionally useful, e.g., if you just want to collect a trace for a specific window of execution then you can combine this with --debug-start to do exactly that.
In addition to not ignoring the signal, this patch also updates the --debug-break help message and deletes a handful of unprotected calls to Debug::breakpoint() that relied on the prior behavior. |
11263:8dcc6b40f164 |
10-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev: Move network devices to src/dev/net/ |
11231:75c0e4915c05 |
01-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
config: Fix broken SimObject listing
The gem5 option '--list-sim-objects' is supposed to list all available SimObjects and their parameters. It currently chokes on SimObjects with parameters that have an object instance as their default value. This is caused by __str__ in SimObject trying to resolve its complete path. When the path resolution method reaches the parent object (a MetaSimObject since it hasn't been instantiated), it dies with a Python exception.
This changeset adds a guard to stop path resolution if the parent object is a MetaSimObject. |
11228:021524c21cbc |
22-Nov-2015 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
config: Added missing types to JSON/INI Python reader
Added the missing types EthernetAddr and Current to the JSON/INI file reader example configs/example/read_config.py.
Also added __str__ to EthernetAddr to make values appear in the same form in JSON an INI files. |
11161:15492f220f16 |
06-Oct-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: print pid in output header
This information is useful if you have a bunch of simulations running and want to know which one to kill, but you've neglected to take advantage of the previous patch and embed the pid in your output path. |
11153:20bbfe5b2b86 |
30-Sep-2015 |
Curtis Dunham <Curtis.Dunham@arm.com> |
base: remove Trace::enabled flag
The DTRACE() macro tests both Trace::enabled and the specific flag. This change uses the same administrative interface for enabling/disabling tracing, but masks the SimpleFlags settings directly. This eliminates a load for every DTRACE() test, e.g. DPRINTF. |
11021:e8a6637afa4c |
14-Aug-2015 |
Joel Hestness <jthestness@gmail.com> |
ruby: Expose MessageBuffers as SimObjects
Expose MessageBuffers from SLICC controllers as SimObjects that can be manipulated in Python. This patch has numerous benefits: 1) First and foremost, it exposes MessageBuffers as SimObjects that can be manipulated in Python code. This allows parameters to be set and checked in Python code to avoid obfuscating parameters within protocol files. Further, now as SimObjects, MessageBuffer parameters are printed to config output files as a way to track parameters across simulations (e.g. buffer sizes)
2) Cleans up special-case code for responseFromMemory buffers, and aligns their instantiation and use with mandatoryQueue buffers. These two special buffers are the only MessageBuffers that are exposed to components outside of SLICC controllers, and they're both slave ends of these buffers. They should be exposed outside of SLICC in the same way, and this patch does it.
3) Distinguishes buffer-specific parameters from buffer-to-network parameters. Specifically, buffer size, randomization, ordering, recycle latency, and ports are all specific to a MessageBuffer, while the virtual network ID and type are intrinsics of how the buffer is connected to network ports. The former are specified in the Python object, while the latter are specified in the controller *.sm files. Unlike buffer-specific parameters, which may need to change depending on the simulated system structure, buffer-to-network parameters can be specified statically for most or all different simulated systems. |
10912:b99a6662d7c2 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and calling drain()/drainResume() on the SimObjects. This is not ideal when non-SimObjects (e.g., ports) need draining since this means that SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need draining from SimObjects and the Python-side of the simulator to the DrainManager. The DrainManager now maintains a set of all objects that need draining. To reduce the overhead in classes owning non-SimObjects that need draining, objects inheriting from Drainable now automatically register with the DrainManager. If such an object is destroyed, it is automatically unregistered. This means that drain() and drainResume() should never be called directly on a Drainable object.
While implementing the new functionality, the DrainManager has now been made thread safe. In practice, this means that it takes a lock whenever it manipulates the set of Drainable objects since SimObjects in different threads may create Drainable objects dynamically. Similarly, the drain counter is now an atomic_uint, which ensures that it is manipulated correctly when objects signal that they are done draining.
A nice side effect of these changes is that it makes the drain state changes stricter, which the simulation scripts can exploit to avoid redundant drains. |
10911:0ca18446a5bb |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Move mem(Writeback|Invalidate) to SimObject
The memWriteback() and memInvalidate() calls used to live in the Serializable interface. In this series of patches, the Serializable interface will be redesigned to make serialization independent of the object graph and always work on the entire simulator. This means that the Serialization interface won't be useful to perform maintenance of the caches in a sub-graph of the entire SimObject graph. This changeset moves these memory maintenance methods to the SimObject interface instead. |
10909:db1b5b20096f |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Remove redundant drain when changing memory modes
When the Python helper code switches CPU models, it sometimes also needs to change the memory mode of the simulator. When this happens, it accidentally tried to drain the simulator despite having done so already. This changeset removes the redundant drain. |
10905:a6ca6831e775 |
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section.
* Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections).
* The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects.
* Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code. |
10758:74e7b9b5029c |
23-Mar-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
misc: quote args in echoed command line
Currently if there are shell special characters in a command-line argument, you can't copy and paste the echoed command line onto a shell prompt because the characters aren't quoted properly. This patch fixes that problem. |
10676:f6c168692b20 |
03-Feb-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
base: Add XOR-based hashed address interleaving
This patch extends the current address interleaving with basic hashing support. Instead of directly comparing a number of address bits with a matching value, it is now possible to use two independent set of address bits XOR'ed together. This avoids issues where strided address patterns are heavily biased to a subset of the interleaved ranges. |
10668:cefb03a42760 |
03-Feb-2015 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Fix typo in Float param
The Float param was not settable on the command line due to a typo in the class definition in python/m5/params.py. This corrects the typo and allows floats to be set on the command line as intended. |
10661:a0dab21e422f |
23-Dec-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
sim: fix reference counting of PythonEvent
When gem5 is a slave to another simulator and the Python is only used to initialize the configuration (and not perform actual simulation), a "debug start" (--debug-start) event will get freed during or immediately after the initial Python frame's execution rather than remaining in the event queue. This tricky patch fixes the GC issue causing this. |
10584:babb40bd2fc6 |
02-Dec-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Ensure dictionary iteration is sorted by key
This patch adds sorting based on the SimObject name or parameter name for all situations where we iterate over dictionaries. This should ensure a deterministic and consistent order across the host systems and hopefully avoid regression results differing across python versions. |
10532:66451b99f3e6 |
12-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
sim: Sort SimObject descendants and ports
This patch fixes a number of occurences where the sorting order of the objects was implementation defined. |
10524:fff17530cef6 |
06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. |
10476:f058e09b7d69 |
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
sim: EventQueue wakeup on events scheduled outside the event loop
This patch adds a 'wakeup' member function to EventQueue which should be called on an event queue whenever an event is scheduled on the event queue from outside code within the call tree of the gem5 event loop.
This clearly isn't necessary for normal gem5 EventQueue operation but becomes the minimum necessary interface to allow hosting gem5's event loop onto other schedulers where there may be calls into gem5 from external code which schedules events onto an EventQueue between the current time and the time of the next scheduled event.
The use case I have in mind is a SystemC hosting where the event loop is:
while (more events) { wait(time_to_next_event or wakeup) setCurTick service events at this time }
where the 'wait' needs to be woken up if time_to_next_event becomes shorter due to a scheduled event from SystemC arriving in a gem5 object.
Requiring 'wakeup' to be called is a more efficient interface than requiring all gem5 event scheduling actions to affect the host scheduler.
This interface could be located elsewhere, say on another global object, or by being passed by the host scheduler to objects which will schedule such events, but it seems cleanest to put it on EventQueue as it is actually a signal to the queue.
EventQueue::wakeup is called for async_event events on event queue 0 as it's only important that *some* queue be triggered for such events. |
10475:5744891a444b |
16-Oct-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
base: Reimplement the DPRINTF mechanism in a Logger class
This patch adds a Logger class encapsulating dprintf. This allows variants of DPRINTF logging to be constructed and substituted in place of the default behaviour.
The Logger provides a logMessage(when, name, format, ...) member function like Trace::dprintf and a getOstream member function to use a raw ostream for logging.
A class OstreamLogger is provided which generates the customary debugging output with Trace::OstreamLogger::logMessage being the old Trace::dprintf. |
10458:64809024b924 |
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add the ability to read a config file using C++ and Python
This patch adds the ability to load in config.ini files generated from gem5 into another instance of gem5 built without Python configuration support. The intended use case is for configuring gem5 when it is a library embedded in another simulation system.
A parallel config file reader is also provided purely in Python to demonstrate the approach taken and to provided similar functionality for as-yet-unknown use models. The Python configuration file reader can read both .ini and .json files.
C++ configuration file reading:
A command line option has been added for scons to enable C++ configuration file reading: --with-cxx-config
There is an example in util/cxx_config that shows C++ configuration in action. util/cxx_config/README explains how to build the example.
Configuration is achieved by the object CxxConfigManager. It handles reading object descriptions from a CxxConfigFileBase object which wraps a config file reader. The wrapper class CxxIniFile is provided which wraps an IniFile for reading .ini files. Reading .json files from C++ would be possible with a similar wrapper and a JSON parser.
After reading object descriptions, CxxConfigManager creates SimObjectParam-derived objects from the classes in the (generated with this patch) directory build/ARCH/cxx_config
CxxConfigManager can then build SimObjects from those SimObjectParams (in an order dictated by the SimObject-value parameters on other objects) and bind ports of the produced SimObjects.
A minimal set of instantiate-replacing member functions are provided by CxxConfigManager and few of the member functions of SimObject (such as drain) are extended onto CxxConfigManager.
Python configuration file reading (configs/example/read_config.py):
A Python version of the reader is also supplied with a similar interface to CxxConfigFileBase (In Python: ConfigFile) to config file readers.
The Python config file reading will handle both .ini and .json files.
The object construction strategy is slightly different in Python from the C++ reader as you need to avoid objects prematurely becoming the children of other objects when setting parameters.
Port binding also needs to be strictly in the same port-index order as the original instantiation. |
10453:d0365cc3d05f |
16-Oct-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
config: Add a --without-python option to build process
Add the ability to build libgem5 without embedded Python or the ability to configure with Python.
This is a prelude to a patch to allow config.ini files to be loaded into libgem5 using only C++ which would make embedding gem5 within other simulation systems easier.
This adds a few registration interfaces to things which cross between Python and C++. Namely: stats dumping and SimObject resolving |
10436:bdb307e8be54 |
11-Oct-2014 |
Andrew Lukefahr <lukefahr@umich.edu> |
sim: draining bug for fast-forwaring multiple cores fix draining bug where multiple cores hit max_insts_any_thread simultaneously
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10427:26fee6c20087 |
09-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add Current as a parameter type
This patch adds the Python parameter type Current, which is used for the DRAM power modelling (to start with). With this addition we avoid implicit unit assumptions. |
10405:7a618c07e663 |
20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. |
10380:ec1af95a2958 |
20-Sep-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
config: Cleanup .json config file generation
This patch 'completes' .json config files generation by adding in the SimObject references and String-valued parameters not currently printed.
TickParamValues are also changed to print in the same tick-value format as in .ini files.
This allows .json files to describe a system as fully as the .ini files currently do.
This patch adds a new function config_value (which mirrors ini_str) to each ParamValue and to SimObject. This function can then be explicitly changed to give different .json and .ini printing behaviour rather than being written in terms of ini_str. |
10364:c12ec2a0de52 |
09-Sep-2014 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Fix vectorparam command line parsing
Parsing vectorparams from the command was slightly broken in that it wouldn't accept the input that the help message provided to the user and it didn't do the conversion on the second code path used to convert the string input to the actual internal representation. This patch fixes these bugs. |
10355:7565dcd505a4 |
03-Sep-2014 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Add port splicing capability to PortRef class
The new configuration scripts need the ability to splice a simobject between a pair of ports that are already connected. The primary use case is when a CommMonitor needs to be created after the system is configured and then spliced between the pair of ports it will monitor. |
10317:19f5df7ac6a1 |
03-Sep-2014 |
Mitch Hayenga <mitch.hayenga@arm.com> |
config: Change parsing of Addr so hex values work from scripts
When passed from a configuration script with a hexadecimal value (like "0x80000000"), gem5 would error out. This is because it would call "toMemorySize" which requires the argument to end with a size specifier (like 1MB, etc).
This modification makes it so raw hex values can be passed through Addr parameters from the configuration scripts. |
10311:ad9c042dce54 |
01-Sep-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: message buffers: significant changes
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file.
This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines.
The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work. |
10267:ed97f6f2ed7a |
10-Aug-2014 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Add hooks to enable new config sys
This patch adds helper functions to SimObject.py, params.py and simulate.py to enable the new configuration system. Functions like enumerateParams() in SimObject lets the config system auto-generate command line options for simobjects to be modified on the command line.
Params in params.py have __call__() added to their definition to allow the argparse module to use them as a type to check command input is in the proper format. |
10201:30a20d2072c1 |
09-May-2014 |
Andrew Bardsley <Andrew.Bardsley@arm.com> |
cpu: Add flag name printing to StaticInst
This patch adds a the member function StaticInst::printFlags to allow all of an instruction's flags to be printed without using the individual is... member functions or resorting to exposing the 'flags' vector
It also replaces the enum definition StaticInst::Flags with a Python-generated enumeration and adds to the enum generation mechanism in src/python/m5/params.py to allow Enums to be placed in namespaces other than Enums or, alternatively, in wrapper structs allowing them to be inherited by other classes (so populating that class's name-space with the enumeration element names). |
10195:7d4d0cd3f7e5 |
09-May-2014 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Avoid generating a reference to myself for Parent.any
The unproxy code for Parent.any can generate a circular reference in certain situations with classes hierarchies like those in ClockDomain.py. This patch solves this by marking ouself as visited to make sure the search does not resolve to a self-reference. |
10181:6270235e0585 |
09-May-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
scons: Require SWIG >= 2.0.4 and remove vector typemaps
SWIG commit fd666c1 (*) made it unnecessary for gem5 to have these typemaps to handle Vector types.
* https://github.com/swig/swig/commit/fd666c1440628a847793bbe1333c27dfa2f757f0 |
10176:266db8ff9ae8 |
23-Apr-2014 |
Sascha Bischoff <sascha.bischoff@arm.com> |
misc: Proper type check and import for PortRef
Rewriting the type checking around PortRef, which was interacting strangely with other Python scripts.
Tested-by: stephan.diestelhorst@arm.com |
10169:628ed23d37af |
10-Feb-2014 |
Curtis Dunham <Curtis.Dunham@arm.com> |
stats: better error message for uninitialized statistic
As suggested by Nathan Binkert in 2008: http://permalink.gmane.org/gmane.comp.emulators.m5.users/2676 |
10134:c36803905607 |
23-Mar-2014 |
Stan Czerniawski <stan.czerniawski@arm.com> |
misc: Fix -q (quiet) flag
Check the right flag. |
10023:91faf6649de0 |
24-Jan-2014 |
Matt Horsnell <matt.horsnell@ARM.com> |
base: add support for probe points and common probes
The probe patch is motivated by the desire to move analytical and trace code away from functional code. This is achieved by the probe interface which is essentially a glorified observer model.
What this means to users: * add a probe point and a "notify" call at the source of an "event" * add an isolated module, that is being used to carry out *your* analysis (e.g. generate a trace) * register that module as a probe listener Note: an example is given for reference in src/cpu/o3/simple_trace.[hh|cc] and src/cpu/SimpleTrace.py
What is happening under the hood: * every SimObject maintains has a ProbeManager. * during initialization (src/python/m5/simulate.py) first regProbePoints and the regProbeListeners is called on each SimObject. this hooks up the probe point notify calls with the listeners.
FAQs: Why did you develop probe points: * to remove trace, stats gathering, analytical code out of the functional code. * the belief that probes could be generically useful.
What is a probe point: * a probe point is used to notify upon a given event (e.g. cpu commits an instruction)
What is a probe listener: * a class that handles whatever the user wishes to do when they are notified about an event.
What can be passed on notify: * probe points are templates, and so the user can generate probes that pass any type of argument (by const reference) to a listener.
What relationships can be generated (1:1, 1:N, N:M etc): * there isn't a restriction. You can hook probe points and listeners up in a 1:1, 1:N, N:M relationship. They become useful when a number of modules listen to the same probe points. The idea being that you can add a small number of probes into the source code and develop a larger number of useful analysis modules that use information passed by the probes.
Can you give examples: * adding a probe point to the cpu's commit method allows you to build a trace module (outputting assembler), you could re-use this to gather instruction distribution (arithmetic, load/store, conditional, control flow) stats.
Why is the probe interface currently restricted to passing a const reference: * the desire, initially at least, is to allow an interface to observe functionality, but not to change functionality. * of course this can be subverted by const-casting.
What is the performance impact of adding probes: * when nothing is actively listening to the probes they should have a relatively minor impact. Profiling has suggested even with a large number of probes (60) the impact of them (when not active) is very minimal (<1%). |
10019:a14f92150d3f |
24-Jan-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Make the Clock a Tick parameter like Latency/Frequency
This patch makes the Clock a TickParamValue just like Latency/Frequency. There is no longer any need to distinguish it (originally needed to support multiplication). |
10002:11a8fc907e5d |
03-Jan-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
python: provide better error message for wrapped C++ methods
If you successfully export a C++ SimObject method, but try to invoke it from Python before the C++ object is created, you get a confusing error that says the attribute does not exist, making you question whether you successfully exported the method at all. In reality, your only problem is that you're calling the method too soon. This patch enhances the error message to give you a better clue. |
10001:61763318c788 |
03-Jan-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
python: don't die on assignment to cloned object
Updating the SimObject topology of a cloned hierarchy is a little dangerous, in that cloning is a "deep copy" and the clone does not inherit SimObject updates the same way it would inherit scalar variable assignments.
However, because of various SimObject-valued proxy parameters, like 'memories', 'clk_domain', and 'system', it turns out that there are a number of implicit topology changes that happen at instantiation, which means that these changes are impossible to avoid. So in order to make cloning systems useful, this error has to go. Changing it to a warning produces a lot of noise, so it seems best just to delete it. |
9993:bdd606534bdc |
03-Dec-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
sim: reset stats after startup Currently statistics are reset after the initial / checkpoint state has been loaded. But ruby does some checkpoint processing in its startup() function. So the stats need to be reset after the startup() function has been called. This patch moves the class to stats.reset() to achieve this change in functionality. |
9983:2cce74fe359e |
25-Nov-2013 |
Steve Reinhardt <stever@gmail.com>, Nilay Vaish <nilay@cs.wisc.edu>, Ali Saidi <Ali.Saidi@ARM.com> |
sim: simulate with multiple threads and event queues This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize.
The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link.
We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working.
Committed by: Nilay Vaish |
9980:cc02ad629b36 |
14-Nov-2013 |
Steve Reinhardt <steve.reinhardt@amd.com> |
tests: suppress output on switcheroo tests
The output from the switcheroo tests is voluminous and (because it includes timestamps) highly sensitive to minor changes, leading to extremely large updates to the reference outputs. This patch addresses this problem by suppressing output from the tests. An internal parameter can be set to enable the output. Wiring that up to a command-line flag (perhaps even the rudimantary -v/-q options in m5/main.py) is left for future work. |
9960:501c7384a5bc |
01-Nov-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
sim: Clarify the difference between tracing and debugging
This patch changes the name the command-line options related to debug output to all start with "debug" rather than being a mix of that and "trace". It also makes it clear that the breakpoint time is specified in ticks and not in cycles. |
9953:9caba3b84a9b |
31-Oct-2013 |
Geoffrey Blake <geoffrey.blake@arm.com> |
config: Fix handling of parents for simobject vectors
SimObjectVector objects did not provide the same interface to the _parent attribute through get_parent() like a normal SimObject. It also handled assigning a _parent incorrectly if objects in a SimObjectVector were changed post-creation, leading to errors later when the simulator tried to execute. This patch fixes these two omissions. |
9941:d979dddf26a5 |
17-Oct-2013 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Fix ommission of number base in ethernet address param
The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case. |
9940:acc015106ac8 |
17-Oct-2013 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Fix for port references generated multiple times
SimObjects are expected to only generate one port reference per port belonging to them. There is a subtle bug with using "not" here as a VectorPort is seen as not having a reference if it is either None or empty as per Python docs sec 9.9 for Standard operators. Intended behavior is to only check if we have not created the reference. |
9876:b47db5ac7d1c |
18-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
swig: Fix issue with circular import in 2.0.9/2.0.10
This patch fixes an issue which prevented gem5 from running when built using swig 2.0.9 and 2.0.10. The generated event.py tried to import m5.internal which in turn relied on importing event. This patch seems to fix the problem, and so far has not caused any other issues. |
9854:e4a4cdfb1b81 |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
util: Add ini string as tooltip info in dot output
This patch adds the config ini string as a tooltip that can be displayed in most browsers rendering the resulting svg. Certain characters are modified for HTML output.
Tested on chrome and firefox. |
9853:20c07aa9322c |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
util: Add colours to the dot output
This patch is adding a splash of colour to the dot output to make it easier to distinguish objects of different types. As a bonus, the pastel-colour palette also makes the output look like a something from the 21st century. |
9852:16046705aa55 |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
util: Add class name to dot graph and output to svg
This patch adds the class name to the label, creates some more space by increasing the rank separation, and additionally outputs the graph as an editable SVG in addition to the PDF. |
9850:87d6b41749e9 |
04-Sep-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. |
9827:f47274776aa0 |
19-Aug-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set.
A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain.
The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic.
The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. |
9811:52567889c9fc |
18-Jul-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
sim: Make MaxTick in Python match the one in C++
This patch aligns the MaxTick in Python with the one in C++. Thus, both reflect the maximum value that an unsigned 64-bit integer can have. |
9794:0236a478a92d |
27-Jun-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Remove Clock parameter multiplication
This patch removes the multiplication operator support for Clock parameters as this functionality is now achieved by creating derived clock domains.
Nate, this one is for you. |
9737:cc3b8601f582 |
03-Jun-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Make the Python module loader PEP302 compliant
The custom Python loader didn't comply with PEP302 for two reasons:
* Previously, we would overwrite old modules on name conflicts. PEP302 explicitly states that: "If there is an existing module object named 'fullname' in sys.modules, the loader must use that existing module".
* The "__package__" attribute wasn't set. PEP302: "The __package__ attribute must be set."
This changeset addresses both of these issues. |
9554:406fbcf60223 |
19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
9544:1a075d9bc1bc |
19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
x86: Move APIC clock divider to Python
This patch moves the 16x APIC clock divider to the Python code to avoid the post-instantiation modifications to the clock. The x86 APIC was the only object setting the clock after creation time and this required some custom functionality and configuration. With this patch, the clock multiplier is moved to the Python code and the objects are instantiated with the appropriate clock. |
9528:d05714c2ab9c |
15-Feb-2013 |
Sascha Bischoff <sascha.bischoff@arm.com> |
base: Add warn() and inform() to m5.utils for use from python
This patch adds two fuctions to m5.util, warn and inform, which mirror those found in the C++ side of gem5. These are added in addition to the already existing m5.util.panic and m5.util.fatal which already mirror the C++ functionality. This ensures that warning and information messages generated by python are in the same format as those generated by C++.
Occurrences of print "Warning: %s..." % name have been replaced with warn("%s...", name) |
9524:d6ffa982a68b |
15-Feb-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Add a system-global option to bypass caches
Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches.
To make memory mode tests cleaner, the following methods are added to the System class:
* isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed.
The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore. |
9521:1cd02decbfd3 |
15-Feb-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system
m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above.
This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications:
* changeToTiming and changeToAtomic are no longer needed, so they have been removed.
* changeMemoryMode is only used internally, so it is has been renamed to be private.
* switchCpus requires a reference to the system containing the CPUs as its first parameter.
WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus(). |
9512:d367034c7e3c |
10-Feb-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Add support for newer versions of IPython
IPython is used for the interactive gem5 shell if it exists. IPython made API changes in version 0.11. This patch adds support for IPython version 0.11 and above. |
9495:ff4b1bde5f60 |
10-Feb-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Fix broken IPython argument handling
Prior to this changeset, we used to clear sys.argv before entering the IPython shell. This caused some versions of IPython to crash because they assume argv[0] to exist. The correct way of overriding the arguments passed to IPython is to set the argv keyword argument when initializing the shell. |
9450:35d4879ad7c2 |
07-Jan-2013 |
Sascha Bischoff <sascha.bischoff@arm.com> |
stats: Fix swig wrapping for Tick in stats
Tick was not correctly wrapped for the stats system, and therefore it was not possible to configure the stats dumping from the python scripts without defining Ticks as long long. This patch fixes the wrapping of Tick by copying the typemap of uint64_t to Tick. |
9430:a113f27b68bd |
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
cpu: Introduce sanity checks when switching between CPUs
This patch introduces the following sanity checks when switching between CPUs:
* Check that the set of new and old CPUs do not overlap. Having an overlap between the set of new CPUs and the set of old CPUs is currently not supported. Doing such a switch used to result in the following assertion error: BaseCPU::takeOverFrom(BaseCPU*): \ Assertion `!new_itb_port->isConnected()' failed.
* Check that all new CPUs are in the switched out state.
* Check that all old CPUs are in the switched in state. |
9411:22e15f9c3fda |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add interleaving bits to the address ranges
This patch adds support for interleaving bits for the address ranges. What was previously just a start and end address, now has an additional three fields, for the high bit, and number of bits to use for interleaving, and a match value to compare against. If the number of interleaving bits is set to zero it is effectively disabled.
A number of convenience functions are added to the range to enquire about the interleaving, its granularity and the number of stripes it is part of. |
9410:f329e7ec9786 |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Traverse lists when visiting children in all proxy
This patch makes the all proxy traverse any potential list that is encountered in the object hierarchy instead of only looking at children that are SimObjects. An example of where this is useful is when creating a multi-channel memory system as a list of controllers, whilst ensuring that the memories are still visible in the system. |
9356:b279bad40aa3 |
16-Nov-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
sim: have a curTick per eventq This patch adds a _curTick variable to an eventq. This variable is updated whenever an event is serviced in function serviceOne(), or all events upto a particular time are processed in function serviceEvents(). This change helps when there are eventqs that do not make use of curTick for scheduling events. |
9346:7a9b5e0335a6 |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Add drain methods to request additional cleanup operations
This patch adds the following two methods to the Drainable base class:
memWriteback() - Write back all dirty cache lines to memory using functional accesses.
memInvalidate() - Invalidate memory system buffers. Dirty data won't be written back.
Specifying calling memWriteback() after draining will allow us to checkpoint systems with caches. memInvalidate() can be used to drop memory system buffers in preparation for switching to an accelerated CPU model that bypasses the gem5 memory system (e.g., hardware virtualized CPUs).
Note: This patch only adds the methods to Drainable, the code for flushing the TLB and the cache is committed separately. |
9345:b557fcea030d |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Add SWIG interface for Serializable
This changeset adds a SWIG interface for the Serializable class, which fixes a warning when compiling the SWIG interface for the event queue. Currently, the only method exported is the name() method. |
9344:7f966113afd1 |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
python: Rename doDrain()->drain() and make it do the right thing
There is no point in exporting the old drain() method in Simulate.py. It should only be used internally by doDrain(). This patch moves the old drain() method into doDrain() and renames doDrain() to drain(). |
9343:e63c6f279906 |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Reuse the code to change memory mode.
changeToAtomic and changeToTiming both do essentially the same thing, they check the type of their input argument, drain the system, and switch to the desired memory mode. This patch moves all of that code to a separate method (changeMemoryMode) and calls that from both changeToAtomic and changeToTiming. |
9342:6fec8f26e56d |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Move the draining interface into a separate base class
This patch moves the draining interface from SimObject to a separate class that can be used by any object needing draining. However, objects not visible to the Python code (i.e., objects not deriving from SimObject) still depend on their parents informing them when to drain. This patch also gets rid of the CountedDrainEvent (which isn't really an event) and replaces it with a DrainManager. |
9338:97b4a2be1e5b |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it. |
9326:96ae1c545fb5 |
02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming based on the assumption that the system does not need draining when running in atomic mode. This is a false assumption since at least the System class requires the system to be drained before it allows switching of memory modes. This patch reverts that part of the changeset. |
9294:8fb03b13de02 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. |
9280:fda147c035b3 |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Param: Fix proxy traversal to support chained proxies
This patch modifies how proxies are traversed and unproxied to allow chained proxies. The issue that is solved manifested itself when a proxy during its evaluation ended up being hitting another proxy, and the second one got evaluated using the object that was originally used for the first proxy.
For a more tangible example, see the following patch on making the default clock being inherited from the parent. In this patch, the CPU clock is a proxy Parent.clock, which is overridden in the system to be an actual value. This all works fine, but the AlphaLinuxSystem has a boot_cpu_frequency parameter that is Self.cpu[0].clock.frequency. When the latter is evaluated, it all happens relative to the current object of the proxy, i.e. the system. Thus the cpu.clock is evaluated as Parent.clock, but using the system rather than the cpu as the object to enquire. |
9262:547845010c08 |
25-Sep-2012 |
Sascha Bischoff <sascha.bischoff@arm.com> |
Statistics: Add a function to configure periodic stats dumping
This patch adds a function, periodicStatDump(long long period), which will dump and reset the statistics every period. This function is designed to be called from the python configuration scripts. This allows the periodic stats dumping to be configured more easilly at run time.
The period is currently specified as a long long as there are issues passing Tick into the C++ from the python as they have conflicting definitions. If the period is less than curTick, the first occurance occurs at curTick. If the period is set to 0, then the event is descheduled and the stats are not periodically dumped.
Due to issues when resumung from a checkpoint, the StatDump event must be moved forward such that it occues AFTER the current tick. As the function is called from the python, the event is scheduled before the system resumes from the checkpoint. Therefore, the event is moved using the updateEvents() function. This is called from simulate.py once the system has resumed from the checkpoint.
NOTE: It should be noted that this is a fairly temporary patch which re-adds the capability to extract temporal information from the communication monitors. It should not be used at the same time as anything that relies on dumping the statistics based on in simulation events i.e. a context switch. |
9254:f1b35c618252 |
25-Sep-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Move CPU-specific methods from SimObject to the BaseCPU class |
9253:e0d2a8e9f445 |
25-Sep-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Remove SimObject::setMemoryMode
Remove SimObject::setMemoryMode from the main SimObject class since it is only valid for the System class. In addition to removing the method from the C++ sources, this patch also removes getMemoryMode and changeTiming from SimObject.py and updates the simulation code to call the (get|set)MemoryMode method on the System object instead. |
9235:5aa4896ed55a |
19-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
AddrRange: Transition from Range<T> to AddrRange
This patch takes the final plunge and transitions from the templated Range class to the more specific AddrRange. In doing so it changes the obvious Range<Addr> to AddrRange, and also bumps the range_map to be AddrRangeMap.
In addition to the obvious changes, including the removal of redundant includes, this patch also does some house keeping in preparing for the introduction of address interleaving support in the ranges. The Range class is also stripped of all the functionality that is never used. |
9232:3bb99fab80d4 |
19-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
AddrRange: Simplify AddrRange params Python hierarchy
This patch simplifies the Range object hierarchy in preparation for an address range class that also allows striping (e.g. selecting a few bits as matching in addition to the range).
To extend the AddrRange class to an AddrRegion, the first step is to simplify the hierarchy such that we can make it as lean as possible before adding the new functionality. The only class using Range and MetaRange is AddrRange, and the three classes are now collapsed into one. |
9221:4f54b0f229b5 |
12-Sep-2012 |
Joel Hestness <hestness@cs.wisc.edu> |
Standard Switch: Drain the system before switching CPUs When switching from an atomic CPU to any of the timing CPUs, a drain is unnecessary since no events are scheduled in atomic mode. However, when trying to switch CPUs starting with a timing CPU, there may be events scheduled. This change ensures that all events are drained from the system by calling m5.drain before switching CPUs. |
9195:77fd8912c9d4 |
07-Sep-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Remove the unused SimObject::regFormulas method
Simulation objects normally register derived statistics, presumably what regFormulas originally was meant for, in regStats(). This patch removes regRegformulas since there is no need to have a separate method call to register formulas. |
9184:a1a8f137b796 |
07-Sep-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Param: Transition to Cycles for relevant parameters
This patch is a first step to using Cycles as a parameter type. The main affected modules are the CPUs and the Ruby caches. There are definitely plenty more places that are affected, but this patch serves as a starting point to making the transition.
An important part of this patch is to actually enable parameters to be specified as Param.Cycles which involves some changes to params.py. |
9180:ee8d7a51651d |
28-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Clock: Add a Cycles wrapper class and use where applicable
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time.
Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though.
This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles.
In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words.
An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes. |
9100:3caf131d7a95 |
11-Jul-2012 |
Brad Beckmann <Brad.Beckmann@amd.com> |
ruby: changes how Topologies are created
Instead of just passing a list of controllers to the makeTopology function in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer which knows how to make the topology, possibly with some extra state set in the configs/ruby/<protocol>.py file. Thus, we can move all of the files from network/topologies to configs/topologies. A new class BaseTopology is added which all topologies in configs/topologies must inheirit from and follow its API. |
9044:904ddeecc653 |
05-Jun-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
sim: Remove FastAlloc
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe. After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc when running twolf for ARM. |
9042:648b62f95015 |
05-Jun-2012 |
Mitchell Hayenga <Mitchell.Hayenga@ARM.com> |
stats: Provide a mechanism to get a callback when stats are dumped.
This mechanism is useful for dumping output that is correlated with stats dumping, but isn't tracked by the gem5 statistics. |
9017:a20f46ccb9ce |
23-May-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Config: Use the attribute naming and include ports in JSON
This patch changes the organisation of the JSON output slightly to make it easier to traverse and use the files. Most importantly, the hierarchical dictionaries now use keys that correspond to the attribute names also in the case of VectorParams (used to be e.f. "cpu0 cpu1"). It also adds the name and the path to each SimObject directory entry. Before this patch, to get cpu0, you would have to query dict['system']['cpu0 cpu1'][0] and this could be a dict with 'cpu0' : { cpu parameters }. Now you use dict['system']['cpu'][0] and get { cpu parameters } (where one is "name" : "cpu0").
Additionally this patch includes more verbose information about the ports, specifying their role, and using a JSON array rather than a concatenated string for the peer. |
9014:e22ded364548 |
23-May-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Config: Exit with fatal if a port is already connected
This patch turns the existing warning into a fatal, as there should never be any cases where a (non-vector) port is assigned to and then later connected to something else. If this behaviour is allowed, as it used to be, there are cases where the wrong number of C++ ports are created when instantiating objects with VectorPorts (obviously that could be fixed, but the better approach is to simply not allow it). |
8999:6f306dd5cee0 |
10-May-2012 |
Uri Wiener <uri.wiener@arm.com> |
DOT: improved dot-based system visualization Revised system visualization to reflect structure and memory hierarchy. Improved visualization: less congested and cluttered; more colorful. Nodes reflect components; directed edges reflect dirctional relation, from a master port to a slave port. Requires pydot. |
8998:c8bf5a20bc07 |
10-May-2012 |
Uri Wiener <uri.wiener@arm.com> |
DOT: fixed broken code for visualizing configuration using dot
Fixed broken code which visualizes the system configuration by generating a tree from each component's children, starting from root. Requires DOT (hence pydot). |
8986:4cc63185478b |
10-May-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
stats: track if the stats have been enabled and prevent requesting master id
Track the point in the initialization where statistics have been registered. After this point registering new masterIds can no longer work as some SimObjects may have sized stats vectors based on the previous value. If someone tries to register a masterId after this point the simulator executes fatal(). |
8947:217fbc57df05 |
14-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Regression: Add ANSI colours to highlight test status
This patch adds a very basic pretty-printing of the test status (passed or failed) to highlight failing tests even more: green for passed, and red for failed. The printing only uses ANSI it the target output is a tty and supports ANSI colours. Hence, any regression scripts that are outputting to files or sending e-mails etc should still be fine. |
8934:f467d4db555a |
06-Apr-2012 |
Brad Beckmann <Brad.Beckmann@amd.com> |
python: added __nonzero__ function to SimObject Bool params |
8927:bc3a389d1e37 |
05-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Python: Make the All proxy traverse SimObject children as well
This patch changes the behaviour of the All proxy parameter to not only consider the direct children, but also do a pre-order depth-first traversal of the object tree and append all results from the children.
This is used in a later patch to find all the memories in the system, independent of where they are located in the hierarchy. |
8922:17f037ad8918 |
30-Mar-2012 |
William Wang <william.wang@arm.com> |
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again. |
8912:62f60ee68b45 |
21-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Python: Fix a conditional expression that requires Python 2.5
This patch changes a conditional expression to a conventional if/else block, which does not require Python >= 2.5. |
8902:75b524b64c28 |
19-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts). |
8900:7d74a97c525f |
19-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those cases when the port is not connected. |
8860:ccd525e43682 |
29-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1, caused by swig not including cstddef and not using the std:: namespace prefix for ptrdiff_t. There is an old patch, http://reviews.m5sim.org/r/913/ that no longer applies cleanly and this might be re-iterating the same issue.
We work around the problem by always enforcing the inclusion of cstddef in all swig interface declarations, and also by explicitly using std::ptrdiff_t. |
8848:2629f0b99e8d |
20-Feb-2012 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SimObject: make get_config_as_dict() tolerate undefined params
Without this patch, undefined params cause a cryptic KeyError in multidict inside get_config_as_dict(). This patch lets undefined params through get_config_as_dict() so they can once again generate meaningful error messages later on in the configuration process. |
8840:b62d40514d98 |
13-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Pass the ports from Python to C++ using the Swig params
This patch adds basic information about the ports in the parameter classes to be passed from the Python world to the corresponding C++ object. Currently, the only information passed is the number of connected peers, which for a Port is either 0 or 1, and for a VectorPort reflects the size of the VectorPort. The default port of the bus had to be renamed to avoid using the name "default" as a field in the parameter class. It is possible to extend the Swig'ed information further and add e.g. a pair with a description and size. |
8839:eeb293859255 |
13-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port.
Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. |
8795:0909f8ed7aa0 |
07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository. |
8785:ef044a5d7321 |
07-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Remove FULL_SYSTEM from swig. |
8737:770ccf3af571 |
31-Jan-2012 |
Koan-Sin Tan <koansin.tan@gmail.com> |
clang: Enable compiling gem5 using clang 2.9 and 3.0
This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh).
clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places. |
8714:cd48e2802644 |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master. |
8675:fd3f7091a5cf |
10-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
config: Fix json output for Python lt 2.6. |
8669:f02f8c38f6a1 |
09-Jan-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
Config: Fix issue with JSON output |
8666:97d873b8b13e |
09-Jan-2012 |
Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> |
sim: Enable sampling of run-time for code-sections marked using pseudo insts.
This patch adds a mechanism to collect run time samples for specific portions of a benchmark, using work_begin and work_end pseudo instructions.It also enhances the histogram stat to report geometric mean. |
8664:42052d5bb793 |
09-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
config: support outputing a pickle of the configuration tree |
8656:44203702a57a |
09-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
SWIG: Make gem5 compile and link with swig 2.0.4
To make gem5 compile and run with swig 2.0.4 a few minor fixes are necessary, the fail label issues by swig must not be treated as an error by gcc (tested with gcc 4.2.1), and the vector wrappers must have SWIGPY_SLICE_ARG defined which happens in pycontainer.swg, included through std_container.i. By adding the aforementioned include to the vector wrappers everything seems to work. |
8607:5fb918115c07 |
31-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions. |
8605:f825e7a4571c |
30-Oct-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Python: Remove import for random |
8603:690417d95f6d |
28-Oct-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Merged with recent changes. |
8597:45c9f664a365 |
20-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SimObject: add export_method* hooks to export C++ methods to Python
Replace the (broken as of previous changeset) swig_objdecl() method that allowed/forced you to substitute a whole new C++ struct definition for SWIG to wrap with a set of export_method* hooks that let you just declare a set of C++ methods (or other declarations) that get inserted in the auto-generated struct.
Restore the System get/setMemoryMode methods, and use this mechanism to specialize SimObject as well, eliminating teh need for sim_object.i. Needed bits of sim_object.i are moved to the new pyobject.i. Also sucked a little SimObject specialization into cxx_param_decl() allowing us to get rid of src/sim/sim_object_params.hh. Now the generation and wrapping of the base SimObject param struct is more in line with how derived objects are handled. |
8596:e6e22fa77883 |
20-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript file and into methods on the objects being wrapped. - Cleaned up some variable naming and added some comments to make the process a little clearer. - Did a little generated file/module renaming: - vptype_Foo now Foo_vector - init_Foo is now Foo_init This makes it easier to see all the Foo-related files in a sorted directory listing. - Made cxx_predecls and swig_predecls normal SimObject classmethods. - Got rid of swig_objdecls hook, even though this breaks the System objects get/setMemoryMode method exports. Will be fixing this in a future changeset. |
8579:ad3704c8a503 |
22-Sep-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability. Properly compare IpAddress objects (by value and not object identity). Also fix up derived param classes (IpNetmask and IpWithPort) similarly. |
8514:57c96df312a1 |
19-Aug-2011 |
Thomas Grass <Thomas.Grass@ARM.com> |
Stats: Add a sparse histogram stat object. |
8460:3893d9d2c6c2 |
10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
O3: Make sure fetch doesn't go off into the weeds during speculation. |
8459:b8c3c20d0385 |
10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
Config: Add support for a Self.all proxy object |
8453:82fc1267d3bb |
05-Jul-2011 |
Nathan Binkert <nate@binkert.org> |
slicc: cleanup slicc code and make it less verbose |
8452:3f2c329e9046 |
05-Jul-2011 |
Nathan Binkert <nate@binkert.org> |
grammar: better encapsulation of a grammar and parsing This makes it possible to use the grammar multiple times and use the multiple instances concurrently. This makes implementing an include statement as part of a grammar possible. |
8333:c1a07ecb6619 |
02-Jun-2011 |
Nathan Binkert <nate@binkert.org> |
copyright: Add code for finding all copyright blocks and create a COPYING file
The end of the COPYING file was generated with: % python ./util/find_copyrights.py configs src system tests util
Update -C command line option to spit out COPYING file |
8331:aa00cee9abb1 |
02-Jun-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SimObject: allow modules in subclass definitions
In particular, this avoids crashing when you do an import (like "import pdb") inside a SimObject subclass definition. |
8328:03cfd2ecf6bb |
30-May-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Misc: Remove the URL from warnings, fatals, panics, etc. |
8327:dda2a88eb7c4 |
25-May-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Name: Replace M5 with gem5 in a few places it's printed on startup. |
8321:9f34cf472451 |
23-May-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
config: reinstate implicit parenting on parameter assignment Last summer's big rewrite of the initialization code (in particular cset 6efc3672733b) got rid of the implicit parenting that used to occur when an unparented SimObject was assigned as a parameter value to another SimObject. The idea was that the new adoptOrphanParams() step would catch these anyway so it was unnecessary.
Unfortunately it turns out that adoptOrphanParams() has some inherent instability in that the parent that does the adoption depends on the config tree traversal order. Even making this order deterministic (e.g., by traversing children in alphabetical order) can introduce unwanted and unexpected hierarchy changes between similar configs (e.g., when adding a switch_cpu in place of a cpu), causing problems when trying to restore checkpoints across similar configs. The hierarchy created by implicit parenting is more stable and more controllable, so this patch turns that behavior back on.
This patch also cleans up some long-standing holes regarding parenting of SimObjects that are created in class definitions (either in the body of the class, or as default parameters).
To avoid breaking some existing config files, this necessitated changing the error on reparenting children to a warning. This change fixes another bug where attempting to print the prior error message would fail on reparenting SimObjectVectors because they lack a _parent attribute. Some further issues with SimObjectVectors were cleaned up by getting rid of the get_parent() call (which could cause errors with some SimObjectVectors where there was no single parent to return) with has_parent() (since all the uses of get_parent() were just boolean tests anyway).
Finally, since the adoptOrphanParam() step turned out to be so problematic, we now issue a warning when it actually has to do an adoption. Future cleanup of config files will get rid of current warnings. |
8297:d57afdcf38f5 |
12-May-2011 |
Nathan Binkert <nate@binkert.org> |
stats: delete mysql support we can add it back within python in some future changeset |
8296:be7f03723412 |
12-May-2011 |
Nathan Binkert <nate@binkert.org> |
stats: move code that loops over all stats into python |
8295:221013f9fd2f |
12-May-2011 |
Nathan Binkert <nate@binkert.org> |
stats: better expose statistics to python. Build a python list and dict of all stats and expose flags properly. |
8291:a6363c870af6 |
07-May-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
Trace: Remove the options trace-help and trace-flags The options trace-help and trace-flags are no longer required. In there place, the options debug-help and debug-flags have been provided. |
8269:5a9a639ce16f |
04-May-2011 |
Nathan Binkert <nate@binkert.org> |
debug: fix help output |
8253:f2ec56fd42c0 |
28-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
event: fix PythonEvent order of %includes since they matter for this case |
8245:a9d06c894afe |
20-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
fix some build problems from prior changesets |
8239:24406820a7e0 |
19-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
python: different import for dealing with demandimport |
8234:a08c5fb4cd89 |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
python: cleanup python code so stuff doesn't automatically happen at startup this allows things to be overridden at startup (e.g. for tests) |
8232:b28d06a175be |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help |
8229:78bf55f23338 |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes |
8224:75527411e636 |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
region: add a utility class for keeping track of regions of some range
This is basically like the range_map stuff in src/base (range already exists in Python). This code is like a set of ranges. I'm using it to keep track of changed lines in source code, but it could be use to keep track of memory ranges and holes in memory regions. It could also be used in memory allocation type stuff. (Though it's not at all optimized.) |
8223:394cb2dc3f7c |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
SortedDict: add functions for getting ranges of keys, values, items |
8222:95fe5c720cfa |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
python: figure out if the m5.internal package exists even with demandimport |
8219:0e2333b86562 |
13-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
main: separate out interact() so it can be used by other functions |
8153:e641f702653a |
18-Mar-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
swig: get rid of m5.internal.random module (swig/random.i) Thanks to swig this was interfering with the standard Python random module. The only function in that module was seed(), which erroneously called srand48(). Moved the function to m5.internal.core, renamed it seedRandom(), and made it call random_mt.init() instead. |
8126:5138d1e453f1 |
11-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SCons: Stop embedding the mercurial revision into the binary.
This causes a lot of rebuilds that could have otherwise possibly been avoided, and, more annoyingly, a lot of unnecessary rerunning of the regressions. The benefits of having the revision in the output haven't materialized, so this change removes it. |
7974:13692327bb0b |
15-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Info: Clean up some info files.
Get rid of RELEASE_NOTES since we no longer do releases, update some of the information in README, and update the date in LICENSE. |
7823:dac01f14f20f |
08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
7822:fc475ac7d2a4 |
08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: rename StatEvent() function to schedStatEvent(). This follows the style rules and is more descriptive. |
7816:b5003ac75977 |
08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
scons: show sources and targets when building, and colorize output.
I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative.
Somehow Ali talked me into adding colors too, which is a whole 'nother story. |
7811:a8fc35183c10 |
03-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript. |
7808:2844d69d03e2 |
30-Dec-2010 |
Nathan Binkert <nate@binkert.org> |
swig: use <> for system %includes instead of "" |
7802:4a3bddd74f36 |
21-Dec-2010 |
Nathan Binkert <nate@binkert.org> |
stats: allow stats to be reset even if no objects have been instantiated |
7801:f71f9634d809 |
21-Dec-2010 |
Nathan Binkert <nate@binkert.org> |
importer: fix error message |
7798:85e1847726e3 |
20-Dec-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Fix a broken error message in verifyIp. |
7778:6a7207241112 |
23-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Copyright: Add AMD copyright to the param changes I just made. |
7777:369f90d32e2e |
23-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Add parameter types for IP addresses in various forms.
New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately. |
7768:cdb18c1b51ea |
19-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
SCons: Support building without an ISA |
7743:f440cdaf1c2d |
11-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Fix an off by one error and a misleading comment. |
7742:611fe187288e |
11-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
SimObject: Add a comment near clear_child that it's unlikely to be called. |
7738:e2e8ca8d9640 |
09-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
SimObject: Use "self" when calling the clear_child method. |
7689:9d75590d7abe |
22-Sep-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
python: get rid of internal.enums package.
Move generated enums into internal.params, which gets imported into object.params, restoring backward compatibility for scripts that expect to find them there. |
7677:c6e283904437 |
12-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
swig: make all generated files go into the m5.internal package
This is necessary because versions of swig older than 1.3.39 fail to do the right thing and try to do relative imports for everything (even with the package= option to %module). Instead of putting params in the m5.internal.params package, put params in the m5.internal package and make all param modules start with param_. Same thing for m5.internal.enums.
Also, stop importing all generated params into m5.objects. They are not necessary and now with everything using relative imports we wound up with pollution of the namespace (where builtin-range got overridden). |
7675:2221ec64132f |
09-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
scons: Stop building the big monolithic swigged params module kill params.i and create a separate .i for each object (param, enums, etc.) |
7674:8e3734851770 |
09-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
init: don't build files that centralize python and swig code
Instead of putting all object files into m5/object/__init__.py, interrogate the importer to find out what should be imported. Instead of creating a single file that lists all of the embedded python modules, use static object construction to put those objects onto a list. Do something similar for embedded swig (C++) code. |
7673:b28bd1fa9a35 |
09-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
scons: use code_formatter wherever we can in the build system |
7672:d609cd948ca0 |
09-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
code_formatter: make it easier to insert whitespace a newline by just doing "code()". indent() and dedent() now take a "count" parameter to indent/dedent multiple levels. |
7671:146caf930da0 |
09-Sep-2010 |
Nathan Binkert <nate@binkert.org> |
swig: don't override SWIG_name anymore It doesn't appear to be necessary and it is somewhat odd. I'm pretty sure that the package parameter to %module does whatever this might have been before. It's necessary in future revisions anyway. |
7534:c76a14014c27 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
misc: add some AMD copyright notices Meant to add these with the previous batch of csets. |
7532:3f6413fc37a2 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases.
If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.)
If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint.
Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize(). |
7531:f5e86115a07a |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: fold checkpoint restore code into instantiate() The separate restoreCheckpoint() call is gone; just pass the checkpoint dir as an optional arg to instantiate(). This change is a precursor to some more extensive reworking of the startup code. |
7528:6efc3672733b |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: clean up child handling The old code for handling SimObject children was kind of messy, with children stored both in _values and _children, and inconsistent and potentially buggy handling of SimObject vectors. Now children are always stored in _children, and SimObject vectors are consistently handled using the SimObjectVector class.
Also, by deferring the parenting of SimObject-valued parameters until the end (instead of doing it at assignment), we eliminate the hole where one could assign a vector of SimObjects to a parameter then append to that vector, with the appended objects never getting parented properly.
This patch induces small stats changes in tests with data races due to changes in the object creation & initialization order. The new code does object vectors in order and so should be more stable. |
7527:fe90827a663f |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: move iterating over SimObjects into Python. |
7526:4bb5f5207617 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: fail on implicit creation of orphans via ports Orphan SimObjects (not in the config hierarchy) could get created implicitly if they have a port connection to a SimObject that is in the hierarchy. This means that there are objects on the C++ SimObject list (created via the C++ SimObject constructor call) that are unknown to Python and will get skipped if we walk the hierarchy from the Python side (as we are about to do). This patch detects this situation and prints an error message.
Also fix the rubytester config script which happened to rely on this behavior. |
7525:722f2ad014a7 |
17-Aug-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: make Python Root object a singleton Enforce that the Python Root SimObject is instantiated only once. The C++ Root object already panics if more than one is created. This change avoids the need to track what the root object is, since it's available from Root.getInstance() (if it exists). It's now redundant to have the user pass the root object to functions like instantiate(), checkpoint(), and restoreCheckpoint(), so that arg is gone. Users who use configs/common/Simulate.py should not notice. |
7503:37da2c208f5f |
21-Jul-2010 |
Nathan Binkert <nate@binkert.org> |
python: add a sorted dictionary class It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand. |
7502:3ef7ff12c788 |
21-Jul-2010 |
Nathan Binkert <nate@binkert.org> |
python: Add mechanism to override code compiled into the exectuable If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files.
This is a developer feature! |
7500:b543b8e5fcbc |
17-Jul-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SimObject: transparently forward Python attribute refs to C++. This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up. |
7493:81328f5e764a |
06-Jul-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: allow SimObject subclasses to define classmethods (without requiring a leading underscore) Also a little cleanup on type names in SimObject.py. |
7492:acc1fbbef239 |
06-Jul-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
sim: fold StartupCallback into SimObject There used to be a reason to have StartupCallback be a separate object, but not any more. Now it's just confusing. |
7459:da32c2b05648 |
15-Jun-2010 |
Nathan Binkert <nate@binkert.org> |
util: clean up attrdict and import multiattrdict into m5.util |
7458:72af7f65f117 |
15-Jun-2010 |
Nathan Binkert <nate@binkert.org> |
python: use ipython in --interactive if it is available |
7445:dfd04ffc1773 |
03-Jun-2010 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Minor remote GDB cleanup. Expand the help text on the --remote-gdb-port option so people know you can use it to disable remote gdb without reading the source code, and thus don't waste any time trying to add a separate option to do that. Clean up some gdb-related cruft I found while looking for where one would add a gdb disable option, before I found the comment that told me that I didn't need to do that. |
6999:f226c098c393 |
10-Mar-2010 |
Nathan Binkert <nate@binkert.org> |
slicc: have a central mechanism for creating a code_formatter. This makes it easier to add global variables like protocol |
6997:5af4976c17e2 |
28-Feb-2010 |
Nathan Binkert <nate@binkert.org> |
SmartDict: Make SmartDict an attrdict |
6977:039202aafc0d |
23-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
stats: this makes some fixes to AverageStat and AverageVector. Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that. |
6862:3d308cbd1657 |
19-Jan-2010 |
Derek Hower <drh5@cs.wisc.edu> |
merge |
6660:a886774d5ae1 |
23-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
ply grammar: Fixup Tokenizer class so you can get lexer arguments |
6656:69714e675ee2 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
params: small cleanup to param description internals |
6654:4c84e771cca7 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. |
6653:9e27313312e6 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
multiattrdict: make multilevel nesting work properly |
6652:f24b06320444 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
attrdict: add pickle support to attrdict |
6651:9f6b8815d045 |
22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
code_formatter: use __builtin__ which is correct, not __builtins__ |
6502:6c7d9e9b3c83 |
16-Aug-2009 |
Nathan Binkert <nate@binkert.org> |
code_formatter: Add a python class for writing code generator templates |
6501:1b5863aba48c |
16-Aug-2009 |
Nathan Binkert <nate@binkert.org> |
ply: add a base class called Grammar that encapsulates a ply grammar |
6500:ee7587e7c71d |
16-Aug-2009 |
Nathan Binkert <nate@binkert.org> |
orderdict: Use DictMixin and add orderdict to m5.util |
6499:312b22c30c16 |
16-Aug-2009 |
Nathan Binkert <nate@binkert.org> |
python: Make it possible to import the parts of m5 that are pure python |
6278:47e757f289e0 |
02-Jul-2009 |
Nathan Binkert <nate@binkert.org> |
attrdict: correct delattr |
6224:c8f19b4cd6d5 |
01-Jun-2009 |
Nathan Binkert <nate@binkert.org> |
swig: %include Event before PythonEvent so python gets the subclass correct. Before this change, some versions of swig would cause PythonEvent to be derived from object instead of Event |
6216:2f4020838149 |
17-May-2009 |
Nathan Binkert <nate@binkert.org> |
includes: sort includes again |
6214:1ec0ec8933ae |
17-May-2009 |
Nathan Binkert <nate@binkert.org> |
types: Move stuff for global types into src/base/types.hh |
6171:59006a759508 |
11-May-2009 |
Nathan Binkert <nate@binkert.org> |
python: pull out common code from main that processes arguments |
6131:babe6d1f91f7 |
22-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
stats: expose statistics to python |
6126:5f32f9e3c65a |
22-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
stats: remove simplescalar compatibility for printing |
6020:0647c8b31a99 |
06-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Merge ARM into the head. ARM will compile but may not actually work. |
6007:e0344c15e73b |
07-Mar-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Fix up regression execution to better handle tests that end abnormally. E.g., mark aborts due to assertion failures as failed tests, but those that get killed by the user as needing to be rerun, etc. |
6001:00251eb95de7 |
05-Mar-2009 |
Nathan Binkert <nate@binkert.org> |
stats: create an enable phase, and a prepare phase. Enable more or less takes the place of check, but also allows stats to do some other configuration. Prepare moves all of the code that readies a stat for dumping into a separate function in preparation for supporting serialization of certain pieces of statistics data. While we're at it, clean up the visitor code and some of the python code. |
5952:c1ee8282291d |
26-Feb-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
CPA: Add new object for gathering critical path annotations. |
5950:bf32d75419ad |
26-Feb-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Trace: fix the --trace-start option |
5879:e9f9c0f7e5f0 |
18-Feb-2009 |
Nathan Binkert <nate@binkert.org> |
events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. |
5873:67a6ea624776 |
15-Feb-2009 |
Nathan Binkert <nate@binkert.org> |
traceflags: fix --trace-help |
5860:68c52fee5a53 |
04-Feb-2009 |
Nathan Binkert <nate@binkert.org> |
some new files are missing copyright notices |
5824:b88edb9f3333 |
30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
SCons: Fix how we get Mercurial revision information since internals keep changing. |
5822:05ffa2c3c800 |
30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Errors: Print a URL with a hash of the format string to find more information about an error. |
5821:2831ae658bfc |
30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). |
5802:1fb28f526602 |
19-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
python: add fatal() function to the m5 package and use it |
5801:e0850da03cd4 |
19-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
python: Try to isolate the stuff that's in the m5.internal package a bit more. |
5799:0af61da2b66a |
19-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
tracing: panic() if people try to use tracing, but TRACING_ON is not set. Also clean things up so that help strings can more easily be added. Move the help function into trace.py |
5798:edbf23127462 |
19-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
python: Rework how things are imported |
5773:7434b2271b0c |
08-Dec-2008 |
Nathan Binkert <nate@binkert.org> |
output: Change default output directory and files and update tests. |
5767:8e87c0aa1f0b |
06-Dec-2008 |
Nathan Binkert <nate@binkert.org> |
traceflags: Make "All" a valid trace flag. |
5766:37b74394f2f9 |
06-Dec-2008 |
Nathan Binkert <nate@binkert.org> |
SimObject: change naming of vectors so there are the same numbers of digits. i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100 now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100 |
5752:32ec0a0e41b2 |
17-Nov-2008 |
Steve Reinhardt <Steve.Reinhardt@amd.com> |
Sort trace flags before printing them. |
5738:6ea35903c420 |
10-Nov-2008 |
Nathan Binkert <nate@binkert.org> |
python: Fix the reference counting for python events placed on the eventq. We need to add a reference when an object is put on the C++ queue, and remove a reference when the object is removed from the queue. This was not happening before and caused a memory problem. |
5709:e8849c6e422d |
27-Oct-2008 |
Clint Smullen <cws3k@cs.virginia.edu> |
Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python.
Signed-off By: Ali Saidi |
5696:be57a48fb100 |
14-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
eventq: make python events actually work |
5620:c13b446714ca |
10-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
output: Make panic/fatal/warn more flexible so we can add some new ones. The major thrust of this change is to limit the amount of code duplication surrounding the code for these functions. This code also adds two new message types called info and hack. Info is meant to be less harsh than warn so people don't get confused and start thinking that the simulator is broken. Hack is a way for people to add runtime messages indicating that the simulator just executed a code "hack" that should probably be fixed. The benefit of knowing about these code hacks is that it will let people know what sorts of inaccuracies or potential bugs might be entering their experiments. Finally, I've added some flags to turn on and off these message types so command line options can change them. |
5618:1abb23c038d5 |
10-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
jobfile: Add support for dictionaries as jobfile options. If the same dictionary option is seen in several options, those dictionaries are composed. If you define the same dictionary key in multiple options, the system flags an error. Also, clean up the jobfile code so that it is more debuggable. |
5617:04b9d1e7ef2c |
10-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
python: Add a utility for nested attribute dicts. Change attrdict so that attributes that begin with an underscore don't go into the dict. |
5610:0e1e9c186769 |
10-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
SimObjects: Clean up handling of C++ namespaces. Make them easier to express by only having the cxx_type parameter which has the full namespace name, and drop the cxx_namespace thing. Add support for multiple levels of namespace. |
5606:6da7a58b0bc8 |
09-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. |
5605:b194a80157e2 |
09-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
eventq: Major API change for the Event and EventQueue structures.
Since the early days of M5, an event needed to know which event queue it was on, and that data was required at the time of construction of the event object. In the future parallelized M5, this sort of requirement does not work well since the proper event queue will not always be known at the time of construction of an event. Now, events are created, and the EventQueue itself has the schedule function, e.g. eventq->schedule(event, when). To simplify the syntax, I created a class called EventManager which holds a pointer to an EventQueue and provides the schedule interface that is a proxy for the EventQueue. The intent is that objects that frequently schedule events can be derived from EventManager and then they have the schedule interface. SimObject and Port are examples of objects that will become EventManagers. The end result is that any SimObject can just call schedule(event, when) and it will just call that SimObject's eventq->schedule function. Of course, some objects may have more than one EventQueue, so this interface might not be perfect for those, but they should be relatively few. |
5604:7c58fc1ec5dc |
09-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
pdb: Try to make pdb work better. I've done a few things here. First, I invoke the script a little bit differently so that pdb doesn't get confused. Second, I've stored the actual filename in the module's __file__ so that pdb can find the source file on your machine. |
5586:d27058799d3a |
06-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
python: cleanup options parsing stuff so that it properly deals with defaults. While we're at it, make it possible to run main.py in a somewhat standalone mode again so that we can test things without compiling. |
5578:db6756431717 |
30-Sep-2008 |
Steve Reinhardt <Steve.Reinhardt@amd.com> |
Make overriding port assignments in Python work, and print better error messages when it doesn't. |
5543:3af77710f397 |
10-Sep-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
5528:10a17e8a6d35 |
04-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Make time format in 'started' line same as 'compiled'. Also make -B output consistent with normal header, and only include actual build options. |
5527:cdcfaac59d70 |
04-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Get rid of outputStream... wasn't really being used (except for warn()) and new -r/-e options make it not worth fixing. |
5524:e5fbd38bc828 |
04-Aug-2008 |
Steve Reinhardt <stever@gmail.com> |
Add -r/-e options to redirect stdout/stderr. Better than using shell since it automatically uses -d directory for output files (creating it as needed). |
5523:6279e78a2df2 |
03-Aug-2008 |
Nathan Binkert <nate@binkert.org> |
sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. |
5522:e56c3d89be79 |
03-Aug-2008 |
Nathan Binkert <nate@binkert.org> |
libm5: Create a libm5 static library for embedding m5.
This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code.
Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main.
The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. |
5517:3ad997252dd2 |
31-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
scons: Get rid of generate.py in the build system. I decided that separating some of the scons code into generate.py was just a bad idea because it caused the dependency system to get all messed up. If separation is the right way to go in the future, we should probably use the sconscript mechanism, not the mechanism that I just removed. |
5512:755fcaf7a4cf |
23-Jul-2008 |
Michael Adler <Michael.Adler@intel.com> |
RemoteGDB: add an m5 command line option for setting or disabling remote gdb. |
5492:ebec0a848220 |
24-Jun-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
Checkpoinging/SWIG: Undo part of changeset 5464 since it broke checkpointing. |
5488:c8571e8ce7b6 |
18-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
imported patch sim_object_params.diff |
5475:7c18f61da616 |
16-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
params: Prevent people from setting attributes on vector params. |
5474:a9b2504432d1 |
15-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
add compile flags to m5 |
5473:47c5168d092c |
15-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
Command line option to print out List of SimObjects and their parameters |
5472:5df361e08b81 |
15-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
main: add .m5/options.py processing. This file is processed before arguments are parsed so that they can change the default options for various config parameters. |
5471:576aa675d4e5 |
15-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
Add .m5 configuration directory |
5470:ad060d1f1037 |
15-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
python: Separate the options parsing stuff. Remove options parsing stuff from main.py so things are a bit more obvious. |
5469:42719798884a |
14-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
params: Fix the memory bandwidth parameter |
5468:786868ff3058 |
14-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
params: Fix floating point parameters |
5467:6d9df90d70d7 |
14-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
python: Move various utility classes into a new m5.util package so they're all in the same place. This also involves having just one jobfile.py and moving it into the utils directory to avoid duplication. Lots of improvements to the utility as well. |
5464:7eb7f0f5e79f |
14-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
Fix various SWIG warnings |
5462:52960521706f |
14-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
scons: proper fix for hg version stuff |
5461:943f436efe9b |
13-Jun-2008 |
Nathan Binkert <nate@binkert.org> |
scons: fix program_info.cc generation |
5456:9e1f352d6761 |
13-Jun-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
HG: Add compiled hg revision and date to the standard M5 output. |
5454:4b1261c2af58 |
12-Jun-2008 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Allow nested namespaces in cxx_namespace |
5451:01b4c909afc6 |
12-Jun-2008 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Remove an unnecessary include. |
5346:5e0130aed888 |
11-Feb-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
Update copyright dates |
5244:bf32c57328f5 |
12-Nov-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Params: Fix check for cycles in the configuration and clarify the comments/error message. |
5219:e93a04703f56 |
08-Nov-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Python: Allow a range to be a python tuple/list. |
5214:1ac44b6c87ec |
04-Nov-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
TraceFlags: Fix off-by-one error with number of traceflags. |
5202:ff56fa8c2091 |
31-Oct-2007 |
Steve Reinhardt <stever@gmail.com> |
String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). |
5192:582e583f8e7e |
31-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Traceflags: Add SCons function to created a traceflag instead of having one file with them all. |
5054:aaee8b6e8c43 |
04-Sep-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Serialization: Fix unserialization of object pointers |
5053:a650784c9896 |
04-Sep-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Config: Remove some ini file code that no longer works |
5037:f7af52292c45 |
30-Aug-2007 |
Miles Kaufmann <milesck@eecs.umich.edu> |
python: Write configuration file without reassigning sys.stdout.
Using print >>ini_file syntax instead of reassigning sys.stdout allows the python debugger to be used. |
5034:6186ef720dd4 |
30-Aug-2007 |
Miles Kaufmann <milesck@eecs.umich.edu> |
params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) |
5033:2a48ab2b86d5 |
30-Aug-2007 |
Miles Kaufmann <milesck@eecs.umich.edu> |
python: Eliminate the Python use of eval() and frame manipulation |
4983:e7435e741d90 |
17-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Ports: Only try to do EthPort stuff in full system. |
4981:33fabf3473a5 |
16-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Devices: Make EtherInts connect in the same way memory ports currently do. |
4974:851c67c711a4 |
13-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: make the DictImporter's unload() work in any context. import sys since sys may not be defined in whatever context the DictImporter is used. Also reset self.installed after an unload since the same DictImporter could be used again |
4946:fa62733fca2d |
04-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
switching: Remove the drain and resume code from the switching code. This allows us to change memory modes as well. Clean up the code while we're at it. |
4945:6f40bdb0ba9f |
04-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: use the enum values in the memory mode changing code |
4944:9b2ea9a59700 |
04-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
swig: %include all of the enums to get all of the definitions. (instead of %import) |
4942:1b82683f85d4 |
04-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: provide access to stats |
4859:97c7749896a6 |
03-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: Improve support for python calling back to C++ member functions. Add support for declaring SimObjects to swig so their members can be wrapped. Make sim_object.i only contain declarations for SimObject. Create system.i to contain declarations for System. Update python code to properly call the C++ given the new changes. |
4852:8361145d7121 |
02-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: fix m5.build_env variable. As it is now, some objects will get the incorrect value depending where they were defined. |
4851:af527e8042bd |
02-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
python: need to import objects to make some calls work |
4850:434e8d79de49 |
02-Aug-2007 |
Nathan Binkert <nate@binkert.org> |
main: expose the build information as a simple command line parameter |
4762:c94e103c83ad |
24-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. |
4621:0468bff29088 |
28-May-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Merge vm1.(none):/home/stever/bk/newmem-head into vm1.(none):/home/stever/bk/newmem-cache2 |
4553:fac59b75a87d |
10-Jun-2007 |
Nathan Binkert <binkertn@umich.edu> |
Add a function to get a SimObject's memory mode and rework the set memory mode code to only go through the change if it is necessary |
4501:b5f473594687 |
31-May-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
src/cpu/simple/base.cc: Hand merge |
4486:aaeb03a8a6e1 |
27-May-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
4467:cb5715e021ca |
19-May-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. |
4447:fe29baffee6d |
11-May-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move full CPU sim object stuff into the encumbered directory |
4446:9f5df8033a44 |
11-May-2007 |
Nathan Binkert <binkertn@umich.edu> |
Float should have a c++ param type |
4444:0648bdc8d1c9 |
10-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs
configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs |
4439:a251d5d9ba57 |
10-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add/update parameters for bus bridge |
4432:5e55857abb01 |
07-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
fix partial writes with a functional memory hack figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier |
4386:c25aed9fabc4 |
18-Apr-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move the turbolaser python simobject stuff into the encumbered directory |
4382:b35e75e1b890 |
13-Apr-2007 |
Nathan Binkert <binkertn@umich.edu> |
Completely re-work how the scons framework incorporates swig and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. |
4380:1cbb5d3e4288 |
12-Apr-2007 |
Nathan Binkert <binkertn@umich.edu> |
Fix NextEthernetAddr. unproxy() needs to return a new object otherwise all instances will use the same value. This fix is more or less unique to NextEthernetAddr because its use of the proxy stuff is a bit different than everything else. |
4379:69a44bfdcaf7 |
12-Apr-2007 |
Nathan Binkert <binkertn@umich.edu> |
Add a scons hack to force symlinks to the swig .i files to be created |
4303:74c6f9ed49ac |
29-Mar-2007 |
Kevin Lim <ktlim@umich.edu> |
Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond.
Remove this hack once the caches eventually get fixed. |
4283:1812e4119208 |
26-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
first bit of life from the intel gigabit model |
4202:f7a05daec670 |
11-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. |
4174:fd48d7929d5c |
07-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Cleanup |
4168:846a831f6c0b |
06-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Python parameters types need analogous C++ types |
4167:ce5d0f62f13b |
06-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. |
4165:7382285a50e7 |
05-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Python atexit handlers are called in reverse order. Fix things so the stats dump happens last. |
4126:0bb1fc1236a0 |
03-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Do the default argument stuff in python |
4123:9c80390ea1bb |
03-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Factor code out of main.cc and main.i into a bunch of files so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. |
4104:10b99ef0a7ff |
03-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Add Iob and remove the fake device
configs/common/FSConfig.py: add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy |
4103:785279436bdd |
03-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore |
4094:1950ef76ddf9 |
22-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the ConsoleListener SimObject and just fold the relevant code directly into the SimConsole object. Now, you can easily turn off the listen port by just specifying 0 as the port. |
4087:ad2f343e3d45 |
21-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Fix tracing so it starts right away if --trace-start is not specified. |
4086:80530ac5adef |
21-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Automatically generate m5/internal/__init__.py and swig/init.cc based on the swig modules that we have |
4081:80f1e833d118 |
18-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the stand alone ParamContext since all of the relevant stuff has now been moved to python. |
4080:ff61e45c6ff3 |
18-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the Serialize and IntervalStats Param contexts since they're no longer used |
4078:3f73f808bbd4 |
18-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. |
4074:f2c4afa8cd46 |
17-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Default to tracing being disabled in C++, it will be turned on in python. Fix the trace start code so it actually starts when it is suppsed to. Make the Exec tracing stuff obey the trace enabled flag. |
4073:62f6ab072e2e |
17-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Pass an exception from a python event through the event queue back into python so we don't just silently ignore those errors |
4059:e9cef915589f |
13-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Make mulitple consoles work and be distinguishable from each other
src/dev/alpha/tsunamireg.h: get rid of things that aren't really tsunami registers src/dev/platform.hh: src/dev/uart.cc: the uart pointer isn't used anymore src/dev/simconsole.cc: make the simconsole print something more useful to distinguish between various consoles in a single system src/dev/uart8250.hh: put the needed uart defines in here rather than including them from tsunamireg src/python/m5/objects/T1000.py: add a console to the T1000 config for the hypervisor |
4054:3d617b3be4fa |
13-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Merge all of the execution trace configuration stuff into the traceflags infrastructure. InstExec is now just Exec and all of the command line options are now trace options. |
4053:ee914b22709e |
13-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Rearrange traceflags.py so that the file generation only happens if the script is invoked as main. This allows us to import traceflags.py if we just want the list of available flags. Embed traceflags.py into the zipfile so it can be accessed from the python side of things. With this, print an error on invalid flags and add --trace-help option that will print out the list of trace flags that are compiled in. If a flag is prefixed with a '-', now that flag will be disabled. |
4046:ef34b290091e |
10-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Clean up tracing stuff more, get rid of the trace log since its not all that useful. Fix a few bugs with python/C++ integration. |
4045:43eb54e807d1 |
09-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the Random context and add the support directly to python. We don't currently use randomness much, so I didn't go too far, but in the future, we may want to actually expose the random number values themselves to python. For now, I'll at least let you seed it. While we're at it, clean up a clearly bad way for generating random doubles. |
4044:204fd77bae19 |
09-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Clean up from my last commit to the trace stuff. |
4042:dbd98b2264ed |
09-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the Trace ParamContext and give python direct access to enabling/disabling tracing. Command line is unchanged except for the removal of --trace-cycle since it's not so clear what that means. |
4007:8c3bfad8bb92 |
31-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
make sparc fs less chatty
src/SConscript: strip doesn't take a src and dest in solaris |
3934:ca2aa5d36115 |
25-Jan-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move time forward to Jan 1, 2009 and update stats |
3932:62e915bb6704 |
25-Jan-2007 |
Nathan Binkert <binkertn@umich.edu> |
Instead of passing an int to represent time between python and C++ pass the tuple of python's struct_time and interpret that. Fixes a problem where the local timezone leaked into the time calculation. Also fix things so that the unix, python, and RTC data sheets all get the right time. Provide both years since 1900 and BCD two digit year. Put the date back at 1/1/2006 for now. |
3914:e83101d984d5 |
21-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add dumb time of day device |
3898:42a529d97cf2 |
09-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add memory mapped disk device
configs/common/FSConfig.py: src/python/m5/objects/T1000.py: add configuration for memory mapped disk src/dev/sparc/SConscript: add memory mapped disk to sconscript |
3887:4a565b35bdee |
03-Jan-2007 |
Nathan Binkert <binkertn@umich.edu> |
set __name__ in the root m5 script to __m5_main__ so we can tell if the script is run from m5 as the m5 script |
3885:fd4067a5b903 |
03-Jan-2007 |
Nathan Binkert <binkertn@umich.edu> |
Add 'Time' as a parameter type that can accept various formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit |
3881:f06ef65cd746 |
27-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48
src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too |
3878:e8321e132c25 |
29-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
Formatting |
3872:f05270fc838c |
22-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
Fix copyright |
3871:a6ef81a18107 |
22-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
Expose the C++ event queue to python via the python function m5.internal.event.create(). It takes a python object and a Tick and calls process() when the Tick occurs. |
3869:14fa2366b6a9 |
21-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
Create a wrapper function to more easily add swig stuff to the build |
3868:5a58b399e883 |
21-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
move the swig initialization calls from src/sim/main.cc to src/python/swig/init.cc so that it's not as easy to forget about it when you add a new swig module. |
3847:44db65eb4084 |
15-Dec-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
small change to eliminate address range overlap. |
3825:9b5e6c4d3ecb |
07-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices |
3814:33bd4ec9d66a |
04-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller |
3812:eaa215123a26 |
30-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it
configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it |
3751:b422ffec62c1 |
22-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it. |
3745:70a265d01c87 |
20-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Add in rom/rams for the nvram, hypervisor description, and partition description. |
3743:2061715f68d1 |
16-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Fixes for SPARC_FS
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. |
3714:5e54b860fd45 |
03-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Support better param conversions to/from numeric subclasses. |
3713:7edf519900b5 |
03-Dec-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Fix help strings on GenRepl params. |
3669:3607aaed36b6 |
16-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Implement current working directory for LiveProcesses |
3663:a07681fab002 |
14-Nov-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update phase param in the .py file for the cpus |
3645:2bf1f7c69254 |
13-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Expose debugBreakCycle through swig and get rid of the Debug param context |
3630:8d12a7309b1e |
14-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Create a stub t1000 platform. |
3624:aaba7e06ece4 |
12-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Create a module called internal where swigged stuff goes. Rename cc_main to internal.main |
3620:f77e7f6ac005 |
12-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Fix Typo |
3617:384e3b1eae06 |
11-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the ParamContext for pseudo instructions and move the parameters to the BaseCPU object. |
3584:8c3cdb2c001c |
09-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together |
3511:8cb26619b6ec |
08-Nov-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
simplify maxtick parsing in both the python and the c++.
configs/common/Simulation.py: simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick. src/python/m5/__init__.py: make a new m5 param called MaxTick. src/sim/host.hh: fix the M5 def. of MaxTick src/sim/main.cc: Simplify the MaxTick/num_cycles parsing within main.cc |
3508:73779d69fa2c |
08-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove mem parameter. Should have been removed earlier.
src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. |
3506:99f86646ba5c |
07-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add code to operate in lockstep with legion
src/python/m5/main.py: add option to operate in lockstep with legion |
3504:1d42c37f776b |
07-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Fix error message. |
3502:1ba705a3754b |
07-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove hack by setting configuration better.
src/dev/isa_fake.cc: src/dev/isa_fake.hh: No need for specialized init() function any more. src/python/m5/objects/Tsunami.py: Override responder when set by user. This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder. |
3499:597f3f6c9775 |
06-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
src/SConscript: remove pcifake and tsunami fake from sconscript src/dev/isa_fake.cc: src/dev/isa_fake.hh: combine badaddr and isa fake into one src/python/m5/objects/Pci.py: remove pcifake src/python/m5/objects/Tsunami.py: make badaddr derive from isafake |
3489:a90b0ecd17a5 |
02-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change.
src/mem/bus.cc: src/mem/bus.hh: Bus now will be setup with a default responder, unless the user overrides it. This default responder should return BadAddress if no matching port is found. src/python/m5/objects/Bus.py: Bus now has a default responder for FS mode if the user doesn't override it. It returns BadAddress if no matching port is found. src/python/m5/objects/Tsunami.py: Add bad address device. Also record when the user has specified their own default responder. |
3342:19e716ad518e |
20-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Use fixPacket function everywhere. Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read.
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device |
3325:55e7e009b618 |
23-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok. |
3321:d9080c4da915 |
18-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method.
src/python/m5/SimObject.py: how did i not commit this already? the other way doesn't seem to work. |
3318:9b2cea73b235 |
20-Oct-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
still working on getting past initialization |
3315:f15ce6434ab0 |
18-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get rid of obsolete in-cache copy support. |
3312:dbaec4804adf |
18-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now). |
3262:5f96609a30ef |
11-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Make Memtester able to test atomic as well src/mem/bus.cc: src/mem/bus.hh: Handle atomic snoops properly for cache->cache transfers src/mem/cache/cache_impl.hh: Debug output. Clean up memleak in atomic mode. Set hitLatency. Still need to send back reasonable number for atomic return value. src/mem/packet.cc: Add command strings for new commands src/python/m5/objects/MemTest.py: Add param to test atomic memory. |
3223:a2b6fa575c05 |
08-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Clean up configs.
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. |
3203:81c29f9756cf |
11-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
System not global object, need to preface it with objects. |
3202:c095cfd0da96 |
11-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py: now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode. src/sim/main.cc: need this conversion now. src/sim/sim_object.hh: put the enum back into SimObject. src/sim/system.hh: memoryMode is now a part of SimObject, need the ::'s |
3196:8eb90bc29df8 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Make memtest work with 8 memtesters
src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system |
3187:7eefad0aed11 |
09-Oct-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Update the Memtester, commit a config file/test for it.
src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description |
3179:c86dfc93984b |
08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Fixes for Port proxies and proxy parameters. |
3170:37fd1e73f836 |
08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation.
src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. |
3167:8c2a0a0d4ed5 |
08-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
bus changes
src/mem/bus.cc: src/mem/bus.hh: minor fix and some formatting changes src/python/m5/objects/Bus.py: changed bits to bytes |
3156:2e6fc95d9ccf |
05-Oct-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets. |
3131:60738ee4e547 |
02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Oops, forgot to assign the option to the param context. |
3130:c21875853a2d |
02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem |
3127:c56885d6dc6d |
02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Add in ability to start a trace at a specific cycle. |
3126:756092c6383c |
02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext. |
3125:febd811bccc6 |
30-Sep-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zamp:./local/clean/o3-merge/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. |
3119:6c93a7460ecf |
02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Be sure to set progress interval. |
3116:0841c1571b81 |
18-Sep-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add boiler plate intel nic code
src/SConscript: add intel nic to sconscript src/dev/pcidev.cc: fix bug with subsystemid value src/python/m5/objects/Ethernet.py: add intel nic to ethernet.py src/python/m5/objects/Ide.py: src/python/m5/objects/Pci.py: Move config_latency into pci where it belogs |
3112:76b70de314b6 |
15-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer.eecs.umich.edu:/bk/newmem into ewok.(none):/home/gblack/m5/newmem |
3109:c3956807347f |
08-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add support for assigning lists of ports or proxies to VectorPorts. Includes support for printing readable VectorPort and Proxy names (via __str__). |
3107:b88d1ff63b19 |
07-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Try to make unproxy order more deterministic. |
3105:993f1abefd67 |
06-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Enable proxies (Self/Parent) for specifying ports. Significant revamp of Port code. Some cleanup of SimObject code too, particularly to make the SimObject and MetaSimObject implementations of __setattr__ more consistent. Unproxy code split out of print_ini().
src/python/m5/multidict.py: Make get() return None by default, to match semantics of built-in dictionary objects. |
3103:330ec058b026 |
05-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Print ports in config.ini as well. |
3102:225b76c8ac68 |
04-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
More Python hacking to deal with config.py split and resulting recursive import trickiness. |
3101:6cce868ddaa6 |
04-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Split config.py into multiple files. Some tweaking to deal with mutually recursive imports. |
3100:fdd6113d7226 |
04-Sep-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
config.py: Import of changes for auto-generation of C++ param structs from my old m5 working directory. This code is *broken* because pieces need to be shuffled around to satisfy name dependencies, but that really messes up the diff, so I want to make an intermediate commit here.
src/python/m5/config.py: Import of changes for auto-generation of C++ param structs from my old m5 working directory. This code is *broken* because pieces need to be shuffled around to satisfy name dependencies, but that really messes up the diff, so I want to make an intermediate commit here. |
3092:7ed45e2f407e |
31-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Tweak proxy resolution error message. |
3066:254e37051d65 |
03-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Added uid, euid, gid, egid, pid and ppid parameters to a live process. |
3051:b4f73000973b |
21-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Merge zizzer:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py: Merge duplicate change |
3041:8d690c7c2efc |
18-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Update reference outputs |
3035:116f2f8e515b |
17-Aug-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add default range to PhysicalMemory |
3020:a33d8709d348 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Minor regression fixes.
src/python/m5/objects/BaseCPU.py: bug fix tests/SConscript: fix up diff ignore strings to reflect changes in m5 output |
3017:972510aadad0 |
16-Aug-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Fix the caches not working in the regression
src/python/m5/objects/BaseCPU.py: Make mem parameter a MemObject, not just a PhysicalMemory Fix a reference not using self tests/configs/simple-atomic.py: Set the mem paramter tests/configs/simple-timing.py: Set the mem parameter |
3012:1d5e18f6a100 |
16-Aug-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Fix Physical Memory to allow memory sizes bigger than 128MB. Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses causes a simulator segfault.
src/SConscript: Add dram.cc to sconscript src/mem/physical.cc: src/mem/physical.hh: Add params struct to physical memory, use params, make latency function be virtual src/python/m5/objects/PhysicalMemory.py: Add DRAMMemory python class |
3005:ceb86e85d62d |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Finish test clean-up & reorg.
configs/common/FSConfig.py: Add default Machine() param configs/example/fs.py: configs/example/se.py: make it work again src/python/m5/objects/BaseCPU.py: Make mem PhysicalMemory so that a Parent.any proxy works well src/sim/process.cc: Increase default stack size so we don't get an 'increasing stack' message on 'hello world' tests/SConscript: Add full list of current configs. tests/configs/simple-atomic.py: tests/configs/simple-timing.py: don't need SEConfig anymore tests/quick/00.hello/test.py: tests/quick/20.eio-short/test.py: fix tests/run.py: move configs to separate dir |
2998:1d5ea4e433f5 |
16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
More restructuring of regression tests. Moving work back to zizzer...
configs/common/FSConfig.py: configs/test/fs.py: Move CPU connections out of makeLinuxAlphaSystem() src/python/m5/objects/BaseCPU.py: Create default TLBs in full system. Move utility cache functions here. src/python/m5/objects/O3CPU.py: Add _mem_ports tests/run.py: Add binpath() Change maxtick default to 'forever' tests/simple-atomic.py: Use connectmemPorts() tests/simple-timing.py: Fix up. |
2973:56dea3a9d279 |
11-Aug-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Started adding a system to output data after every instruction.
src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. |
2969:d2f8f9a23082 |
27-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Clean up some more config stuff.
configs/common/FSConfig.py: Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself. configs/test/fs.py: Update for changed code. src/python/m5/__init__.py: Put makeList into m5. |
2967:8a4b45041da9 |
27-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Output the command line.
src/python/m5/main.py: Output the command line being used. |
2960:147f62dbf5a1 |
27-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Need config read/write latency. |
2946:015472193926 |
05-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem.head |
2943:eb2b70e6116b |
18-Jul-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Merge m5.eecs.umich.edu:/bk/newmem into ewok.(none):/home/gblack/m5/newmem |
2932:eba74420a01c |
21-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Minor functionality updates.
SConstruct: Include an option to specify the CPUs being tested. src/cpu/SConscript: Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker. src/python/m5/objects/O3CPU.py: Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used. tests/SConscript: Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on. |
2930:51a61690c402 |
19-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Minor changes to reflect state used for regression stats.
src/cpu/checker/cpu.hh: Don't count checker's instructions towards total instructions committed. src/python/m5/objects/Root.py: Set default clock to 1 THz. |
2923:db8a876258df |
14-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/fs.py: configs/test/test.py: SCCS merged |
2922:654ef3d30b61 |
14-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Minor updates.
src/python/m5/config.py: Formatting. src/python/m5/main.py: Slightly more useful output when you don't enter in a valid script file. |
2916:1f89faaf188c |
12-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/Tsunami.py: Push more default options to the Python object level as they are rarely changed. |
2913:33fa7c41acb3 |
19-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Change the device latency here to a latency rather than a Tick
src/python/m5/objects/Device.py: src/python/m5/objects/Pci.py: Change the default here to a latency rather than a Tick |
2908:40f7a0a75c1a |
13-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
src/python/m5/main.py: merge two help fixes |
2904:1722b7c77d91 |
13-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Fix help message printing. Might need to clean up the handling of the sys.exit() call, as right now it prints out "None" at the end (not sure why).
src/python/m5/main.py: Fix help message printing. |
2903:6129559a40f2 |
13-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
fix help when no arguments are passed to m5 |
2902:695d4683916e |
13-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add system.mem_mode = ['timing', 'atomic'] update scripts acordingly
configs/test/SysPaths.py: new syspaths from nate, this one allows you to set script, binary, and disk paths like system.dir = 'aouaou' in your script configs/test/fs.py: update for system mem_mode Put small checkpoint example Make clock 1THz configs/test/test.py: src/arch/alpha/freebsd/system.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/system.cc: src/arch/alpha/tru64/system.cc: src/arch/sparc/system.cc: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: update for system mem_mode src/dev/io_device.cc: Use time returned from sendAtomic to delay |
2901:f9a45473ab55 |
12-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
memory mode information now contained in system object States are now running, draining, or drained. memory state information moved into system object system parameter is not fs only for cpus Implement drain() support in devices Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: Since se mode has a system, allow access to it Verify that the atomic cpu is connected to an atomic system on resume src/cpu/simple/base.cc: Since se mode has a system, allow access to it src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system Since se mode has a system, allow access to it Verify that the timing cpu is connected to an timing system on resume src/dev/ide_disk.cc: src/dev/io_device.cc: src/dev/io_device.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: src/dev/sinic.cc: src/dev/sinic.hh: Implement drain() support in devices src/python/m5/config.py: Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times src/python/m5/objects/BaseCPU.py: move system parameter out of fs to everyone src/sim/sim_object.cc: src/sim/sim_object.hh: States are now running, draining, or drained. memory state information moved into system object src/sim/system.cc: src/sim/system.hh: memory mode information now contained in system object |
2899:d0df86790961 |
12-Jul-2006 |
Nathan Binkert <binkertn@umich.edu> |
Add --pdb
src/python/m5/main.py: Add a command line option to invoke pdb on your script |
2891:85ce5705650b |
12-Jul-2006 |
Nathan Binkert <binkertn@umich.edu> |
Fix __file__ for scripts
src/python/m5/main.py: set __file__ to the script, not the m5 binary. |
2890:e9a860453062 |
11-Jul-2006 |
Nathan Binkert <binkertn@umich.edu> |
Fix option parsing.
src/python/m5/main.py: Don't allow interspersed arguments, it messes things up |
2889:9e367e03d656 |
10-Jul-2006 |
Nathan Binkert <binkertn@umich.edu> |
Migrate most of main() and and all option parsing to python
configs/test/fs.py: configs/test/test.py: update for the new way that m5 deals with options src/python/SConscript: Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the python stuff. src/python/m5/__init__.py: redo the way options work. Move them all to main.py src/sim/main.cc: Migrate more functionality for main() into python. Namely option parsing src/python/m5/attrdict.py: A dictionary object that overrides attribute access to do item access. src/python/m5/main.py: The new location for M5's option parsing, and the main() routine to set up the simulation. |
2873:1377a68cd00e |
10-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Add parameters for backwards and forwards sizes for time buffers.
src/base/timebuf.hh: Add a function to return the size of the time buffer. |
2872:ab3083fa35a7 |
07-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Support for recent port changes.
src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/python/m5/objects/OzoneCPU.py: Support Ron's recent port changes. src/cpu/ozone/lw_back_end_impl.hh: Support Ron's recent port changes. Also support handling faults in SE. |
2871:7ed5c9ef3eb6 |
07-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. |
2868:6a7e69fa92d3 |
07-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
src/sim/main.cc: src/sim/serialize.cc: src/sim/serialize.hh: Take in the directory name when checkpointing. |
2865:ce65e5ab786f |
06-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Be sure to call resume after restoring from a checkpoint. |
2860:843426871cbc |
06-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Fixes for draining.
src/cpu/simple/timing.cc: Update for changed return values. src/python/m5/__init__.py: Loop in order to make sure all objects are really drained. Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).
The only case we know every object is actually drained is if they all return immediately that they are drained. |
2846:89fbe74d8ea8 |
06-Jul-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Add default responder to bus Update configuration for new default responder on bus Update to devices to handle their own pci config space without pciconfigall Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt Remove pciconfigspace from pci devices, and py files Add calcConfigAddr that returns address for config space based on bus/dev/function + offset
configs/test/fs.py: Update configuration for new default responder on bus src/dev/ide_ctrl.cc: src/dev/ide_ctrl.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: Update to handle it's own pci config space without pciconfigall src/dev/io_device.cc: src/dev/io_device.hh: change naming for pio port break out recvTiming into two functions to reuse code src/dev/pciconfigall.cc: src/dev/pciconfigall.hh: removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for src/dev/pcireg.h: add a max size for PCI config space (per PCI spec) src/dev/platform.cc: src/dev/platform.hh: remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt src/dev/sinic.cc: remove pciconfigspace as it's no longer a needed parameter src/dev/tsunami.cc: src/dev/tsunami.hh: src/dev/tsunami_pchip.cc: src/dev/tsunami_pchip.hh: add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec) src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: add idea of default responder to bus src/python/m5/objects/Pci.py: add config port for pci devices add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec) |
2845:18e6dde158f0 |
05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem |
2842:feca0c70f45d |
06-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Change the return value of drain. False means the object wasn't able to drain yet.
src/python/m5/config.py: Invert the return value. src/sim/sim_object.cc: Invert the return value of drain. src/sim/sim_object.hh: Change the return value of drain. |
2839:d5dd8a3cdea0 |
05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Rename quiesce to drain to avoid confusion with the pseudo instruction.
src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/python/m5/__init__.py: src/python/m5/config.py: src/sim/main.cc: src/sim/sim_events.cc: src/sim/sim_events.hh: src/sim/sim_object.cc: src/sim/sim_object.hh: Rename quiesce to drain. |
2836:c8f549058964 |
05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. |
2831:0a42b294727c |
02-Jul-2006 |
Korey Sewell <ksewell@umich.edu> |
Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Edit Test3 for newmem
src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter.
Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class |
2828:6f7429218c08 |
30-Jun-2006 |
Korey Sewell <ksewell@umich.edu> |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 |
2826:d20db4a6f7d1 |
30-Jun-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
First pass, now compiles with current head of tree. Compile and initialization work, still working on functionality.
src/mem/cache/base_cache.cc: Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects. Also, all packets have to have data or the delete fails. src/mem/cache/cache.hh: Fix function prototypes so overloading works src/mem/cache/cache_impl.hh: fix functions to match virtual base class src/mem/cache/miss/miss_queue.cc: Packets havve to have data, or delete fails src/python/m5/objects/BaseCache.py: Update for newmem |
2820:7fde0b0f8f78 |
05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Add some different parameters. The main change is that the writeback count is now limited so that it doesn't overflow the buffer.
src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_params.hh: Add in dispatchWidth, wbWidth, wbDepth parameters. wbDepth is the number of cycles of wbWidth instructions that can be buffered. src/cpu/o3/iew.hh: Include separate parameter for dispatch width. Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed. The IQ must make sure with the IEW stage that it can issue instructions prior to issuing. src/cpu/o3/iew_impl.hh: Include separate parameter for dispatch width. Also limit the number of outstanding writebacks so the writeback buffer isn't overflowed. src/cpu/o3/inst_queue_impl.hh: IQ needs to check with the IEW to make sure it can issue instructions, and increments the IEW wb counter each time there is an outstanding instruction that will writeback. src/cpu/o3/lsq_unit_impl.hh: Be sure to decrement the writeback counter if there's a squashed load that returned. src/python/m5/objects/AlphaO3CPU.py: Change the parameters to include dispatch width, writeback width, and writeback depth. |
2817:273f7fb94f83 |
30-Jun-2006 |
Korey Sewell <ksewell@umich.edu> |
Make O3CPU model independent of the ISA
Use O3CPU when building instead of AlphaO3CPU.
I could use some better python magic in the cpu_models.py file!
AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model...
Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl |
2797:b5f26b4eacef |
29-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Add in support for quiescing the system, taking checkpoints, restoring from checkpoints, changing memory modes, and switching CPUs.
Key new functions that can be called on the m5 object at the python interpreter: doQuiesce(root) - A helper function that quiesces the object passed in and all of its children. resume(root) - Another helper function that tells the object and all of its children that the quiesce is over. checkpoint(root) - Takes a checkpoint of the system. Checkpoint directory must be set before hand. setCheckpointDir(name) - Sets the checkpoint directory. restoreCheckpoint(root) - Restores the values from the checkpoint located in the checkpoint directory. changeToAtomic(system) - Changes the system and all of its children to atomic memory mode. changeToTiming(system) - Changes the system and all of its children to timing memory mode. switchCpus(list) - Takes in a list of tuples, where each tuple is a pair of (old CPU, new CPU). Quiesces the old CPUs, and then switches over to the new CPUs.
src/SConscript: Remove serializer, replaced by python code. src/python/m5/__init__.py: Updates to support quiescing, checkpointing, changing memory modes, and switching CPUs. src/python/m5/config.py: Several functions defined on the SimObject for quiescing, changing timing modes, and switching CPUs src/sim/main.cc: Add some extra functions that are exported to python through SWIG. src/sim/serialize.cc: Change serialization around a bit. Now it is controlled through Python, so there's no need for SerializeEvents or SerializeParams.
Also add in a new unserializeAll() function that loads a checkpoint and handles unserializing all objects. src/sim/serialize.hh: Add unserializeAll function and a setCheckpointName function. src/sim/sim_events.cc: Add process() function for CountedQuiesceEvent, which calls exitSimLoop() once its counter reaches 0. src/sim/sim_events.hh: Add in a CountedQuiesceEvent, which is used when the system is preparing to quiesce. Any objects that can't be quiesced immediately are given a pointer to a CountedQuiesceEvent. The event has its counter set via Python, and as objects finish quiescing they call process() on the event. Eventually the event causes the simulation to stop once all objects have quiesced. src/sim/sim_object.cc: Add a few functions for quiescing, checkpointing, and changing memory modes. src/sim/sim_object.hh: Add a state variable to all SimObjects that tracks both the timing mode of the object and the quiesce state of the object. Currently this isn't serialized, and I'm not sure it needs to be so long as the timing mode starts up the same after a checkpoint. |
2795:a51d5bbcbe41 |
25-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Make OzoneCPU work again in SE/FS.
src/cpu/ozone/cpu.hh: Fixes to get OzoneCPU working in SE/FS again. src/cpu/ozone/cpu_impl.hh: Be sure to set up ports properly. src/cpu/ozone/front_end.hh: Allow port to be created without specifying its name at the beginning. src/cpu/ozone/front_end_impl.hh: Setup port properly, also only use checker if it's enabled. src/cpu/ozone/lw_back_end_impl.hh: Be sure to initialize variables. src/cpu/ozone/lw_lsq.hh: Handle locked flag for UP systems. src/cpu/ozone/lw_lsq_impl.hh: Initialize all variables. src/python/m5/objects/OzoneCPU.py: Fix up config. |
2781:b689ee340f27 |
17-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge |
2769:04c9a7db403f |
17-Jun-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem |
2767:d2e5e9a18fe5 |
17-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Change options back to just being flags instead of taking in a True/False value.
src/python/m5/__init__.py: Change up options. Now setting the flag enables/disables, each of which is the opposite of the default values found in the Python class. |
2763:c3741c707d53 |
17-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Rename SWIG "main" module to "cc_main" so it's clear from the Python side that this is the interface to C++.
src/SConscript: main_wrap.cc -> cc_main_wrap.cc src/python/SConscript: src/python/m5/__init__.py: src/sim/main.cc: s/main/cc_main/ src/python/m5/config.py: s/main/cc_main/ Also directly import cc_main so we don't need to put the "m5." in front all the time. |
2762:470f9e55fe54 |
17-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add --outdir option. Didn't call it "-d" since that's already being used for "detailed cpu". Needed to add extra function for user script to pass parsed options back to m5 module.
configs/test/fs.py: configs/test/test.py: Call setStandardOptions(). src/python/m5/__init__.py: Add --outdir option. Add setStandardOptions() so user script can pass parsed options back to m5 module. src/sim/main.cc: Add SWIG-wrappable function to set output dir. |
2759:d6b4f091d9dd |
16-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Add in some of the commonly used Trace/ExeTrace/Debug options.
src/python/m5/__init__.py: Add in some of the commonly used Trace/ExeTrace/Debug options. Not terribly clean but it works. |
2757:58e3a66e72f7 |
16-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge |
2740:1c2058745499 |
15-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get Port stuff working with full-system scripts. Key was adding support for cloning port references (trickier than it sounds). Got rid of class/instance thing and go back to instance cloning... still don't allow changing SimObject parameters/children after a class (instance) has been subclassed or instantiated (or cloned), which should avoid bizarre unintended behavior.
configs/test/fs.py: Add ".port" to busses to get a port reference. Get rid of commented-out code. src/python/m5/__init__.py: resolveSimObject should call getCCObject() instead of createCCObject() to avoid cycles in recursively creating objects. src/python/m5/config.py: Get rid of class/instance thing and go back to instance cloning. Deep copy has to happen only on instance cloning then (and not on subclassing). Add getCCObject() method to force creation of C++ SimObject without recursively creating its children. Add support for cloning port references (trickier than it sounds). Also clean up some very obsolete comments. src/python/m5/objects/Bridge.py: src/python/m5/objects/Device.py: Add ports. |
2739:977887750573 |
13-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Merge zizzer:/bk/newmem into vm1.(none):/home/stever/bk/newmem |
2738:5d7a31c7fa29 |
13-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Move SimObject creation and Port connection loops into Python. Add Port and VectorPort objects and support for specifying port connections via assignment. The whole C++ ConfigNode hierarchy is gone now, as are C++ Connector objects.
configs/test/fs.py: configs/test/test.py: Rewrite for new port connector syntax. src/SConscript: Remove unneeded files: - mem/connector.* - sim/config* src/dev/io_device.hh: src/mem/bridge.cc: src/mem/bridge.hh: src/mem/bus.cc: src/mem/bus.hh: src/mem/mem_object.hh: src/mem/physical.cc: src/mem/physical.hh: Allow getPort() to take an optional index to support vector ports (eventually). src/python/m5/__init__.py: Move SimObject construction and port connection operations into Python (with C++ calls). src/python/m5/config.py: Move SimObject construction and port connection operations into Python (with C++ calls). Add support for declaring and connecting MemObject ports in Python. src/python/m5/objects/Bus.py: src/python/m5/objects/PhysicalMemory.py: Add port declaration. src/sim/builder.cc: src/sim/builder.hh: src/sim/serialize.cc: src/sim/serialize.hh: ConfigNodes are gone; builder just gets the name of a .ini file section now. src/sim/main.cc: Move SimObject construction and port connection operations into Python (with C++ calls). Split remaining initialization operations into two parts, loadIniFile() and finalInit(). src/sim/param.cc: src/sim/param.hh: SimObject resolution done globally in Python now (not via ConfigNode hierarchy). src/sim/sim_object.cc: Remove unneeded #include. |
2736:98dcdc08884d |
16-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
src/SConscript: Split off FuncUnits from old FUPool so I'm not including encumbered code. This was all written by Steve Raasch so it's safe to include in the main tree. src/cpu/o3/fu_pool.cc: Include the func unit file that's not in the encumbered directory. |
2733:e0eac8fc5774 |
16-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. |
2728:0ee8b52d302b |
13-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Add in a few global options. Feel free to rename them, they're just the first thing that came to mind.
src/python/m5/__init__.py: Add in a few global options. |
2716:b9114064d77a |
11-Jun-2006 |
Nathan Binkert <binkertn@umich.edu> |
Merge iceaxe.:/Volumes/work/research/m5/head into iceaxe.:/Volumes/work/research/m5/merge
src/cpu/simple/base.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: hand merge |
2714:baa3445b7b9e |
11-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add some utility functions to ease handling SimObjects and sequences of SimObjects in a uniform manner. |
2712:aa0891b4a110 |
10-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Don't allow SimObject-valued class params to be set after the class has been instantiated or subclassed. This is one of the main situations that leads to confusing results.
configs/test/fs.py: Clean up to avoid modifying BaseCPU after it's been subclassed. |
2711:2cbc3999ec58 |
10-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Only allow SimObject classes to be instantiated (no cloning!). Provide a makeClass() method to generate a new class using a SimObject instance as a template. All instantiation, subclassing, and class generation is done recursively using "deep copy"-style memoization to maintain object relationships in the face of multiple references to shared objects/classes.
src/python/m5/multidict.py: Rename local dict attribute from 'dict' to 'local' for clarity. |
2709:e99eb394a3ea |
09-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Fix up imports in Ozone objects/*.py files.
src/python/m5/objects/FUPool.py: src/python/m5/objects/OzoneCPU.py: src/python/m5/objects/SimpleOzoneCPU.py: Fix up imports (m5 namespace no longer includes m5.config). |
2708:c4157b162e7b |
09-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Merge vm1.(none):/home/stever/bk/newmem into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py: src/sim/syscall_emul.cc: Hand merge. |
2678:1f86b91dc3bb |
05-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses.
src/cpu/base_dyn_inst.cc: Delete the allocated data in destructor. src/cpu/base_dyn_inst.hh: Only copy the addresses if the translation succeeded. src/cpu/o3/alpha_cpu.hh: Return actual translating port. Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes. src/cpu/o3/alpha_cpu_impl.hh: Pass in memobject to the thread state in SE mode. src/cpu/o3/commit_impl.hh: Initialize all variables. src/cpu/o3/decode_impl.hh: Handle early resolution of branches properly. src/cpu/o3/fetch.hh: Switch structure back to requests. src/cpu/o3/fetch_impl.hh: Initialize all variables, create/delete requests properly. src/cpu/o3/lsq_unit.hh: Include sender state along with the packet. Also include a more generic writeback event that's only used for stores forwarding data to loads. src/cpu/o3/lsq_unit_impl.hh: Redo writeback code to support the response path of the memory system. src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit_impl.hh: Wrap variables in #ifdefs. src/cpu/o3/store_set.cc: Include to get panic() function. src/cpu/o3/thread_state.hh: Create with MemObject as well. src/cpu/thread_state.hh: Have a translating port in the thread state object. src/python/m5/objects/AlphaFullCPU.py: Mem parameter no longer needed. |
2677:af874b8d437c |
05-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Same fix for -P option as Steve's previous fix. |
2674:6d4afef73a20 |
04-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
src/cpu/checker/o3_cpu_builder.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/thread_state.hh: Hand merge. |
2673:1324330df0c5 |
05-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Fix --var=val arg handling. |
2669:f2b336e89d2a |
02-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Fixes to get compiling to work. This is mainly fixing up some includes; changing functions within the XCs; changing MemReqPtrs to Requests or Packets where appropriate.
Currently the O3 and Ozone CPUs do not work in the new memory system; I still need to fix up the ports to work and handle responses properly. This check-in is so that the merge between m5 and newmem is no longer outstanding.
src/SConscript: Need to include FU Pool for new CPU model. I'll try to figure out a cleaner way to handle this in the future. src/base/traceflags.py: Include new traces flags, fix up merge mess up. src/cpu/SConscript: Include the base_dyn_inst.cc as one of othe sources. Don't compile the Ozone CPU for now. src/cpu/base.cc: Remove an extra } from the merge. src/cpu/base_dyn_inst.cc: Fixes to make compiling work. Don't instantiate the OzoneCPU for now. src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/btb.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/sat_counter.hh: src/cpu/op_class.hh: src/cpu/ozone/cpu.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/checker/o3_cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/mem/request.hh: src/cpu/o3/fu_pool.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/dyn_inst.cc: src/cpu/ozone/dyn_inst.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/ozone_impl.hh: src/cpu/ozone/thread_state.hh: Fixes to get compiling to work. src/cpu/o3/alpha_cpu.hh: Fixes to get compiling to work. Float reg accessors have changed, as well as MemReqPtrs to RequestPtrs. src/cpu/o3/alpha_dyn_inst_impl.hh: Fixes to get compiling to work. Pass in the packet to the completeAcc function. Fix up syscall function. |
2667:fe64b8353b1c |
09-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG.
SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. |
2665:a124942bacb8 |
31-May-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Updated Authors from bk prs info |
2655:da93a2088efa |
30-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Link in Python interpreter. Use embedded zip archive to carry Python code instead of homegrown embedded string/file mechanism. Do argument parsing in Python instead of C++.
SConstruct: Add Python interpreter include path & library. Define two new simple builders which copy & concatenate files, respectively, for use by the Python embedded zipfile code. src/SConscript: Encapsulate environment creation in a function. Add code to append Python zip archive to final executable. Eliminate references to obsolete files. src/python/SConscript: Rewrite to generate embedded zip archive of Python code (replacing old "embedded string" mechanism). src/python/m5/__init__.py: Move main arg-parsing loop here (out of C++ main()). src/python/m5/config.py: Minor fix (version incompatibility?). src/sim/main.cc: Invoke embedded Python interpreter to parse args and generate config.ini, replacing C++ arg parsing code. |
2654:9559cfa91b9d |
30-May-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges. |
2632:1bb2f91485ea |
22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure. |