History log of /gem5/src/mem/ruby/network/simple/
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14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/learning_gem5/part3/MSI-cache.sm
/gem5/src/learning_gem5/part3/SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
Switch.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_RfO.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/ruby/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone.slicc
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level.slicc
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level.slicc
/gem5/src/mem/ruby/protocol/MI_example-cache.sm
/gem5/src/mem/ruby/protocol/MI_example-dir.sm
/gem5/src/mem/ruby/protocol/MI_example-dma.sm
/gem5/src/mem/ruby/protocol/MI_example-msg.sm
/gem5/src/mem/ruby/protocol/MI_example.slicc
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/ruby/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer.slicc
/gem5/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Defines.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/ruby/protocol/SConscript
/gem5/src/mem/ruby/protocol/SConsopts
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
13709:dd6b7ac5801f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/storage/Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
SimpleLink.py
SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
12492:4e76959883a6 05-Feb-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>


/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.hh
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/hmc_controller.hh
/gem5/src/mem/ruby/common/BoolVec.hh
/gem5/src/mem/ruby/common/IntVec.hh
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/garnet2.0/CommonTypes.hh
/gem5/src/mem/ruby/network/garnet2.0/Credit.hh
/gem5/src/mem/ruby/network/garnet2.0/CreditLink.hh
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.hh
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/Router.hh
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
/gem5/src/mem/ruby/network/garnet2.0/flit.hh
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.hh
SimpleLink.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/simple_mem.hh
11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
Switch.cc
Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11664:2365e9e396f7 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.

11663:cf870cd20cfc 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.

11523:81332eb10367 06-Jun-2016 David Guillen Fandos <david.guillen@arm.com>

stats: Fixing regStats function for some SimObjects

Fixing an issue with regStats not calling the parent class method
for most SimObjects in Gem5. This causes issues if one adds new
stats in the base class (since they are never initialized properly!).

Change-Id: Iebc5aa66f58816ef4295dc8e48a357558d76a77c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11430:bd1c6789c33f 07-Apr-2016 Andreas Sandberg <andreas.sandberg@arm.com>

Revert to 74c1e6513bd0 (sim: Thermal support for Linux)

11422:4f749e00b667 18-Nov-2014 Akash Bagdia <akash.bagdia@ARM.com>

power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.

11321:02e930db812d 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.


/gem5/src/arch/alpha/process.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/kvm/arm_cpu.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/generic/tlb.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/types.hh
/gem5/src/base/atomicio.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/fenv.c
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/pred/bpred_unit.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/arm/flash_device.cc
/gem5/src/dev/arm/ufs_device.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
PerfectSwitch.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/stack_dist_calc.cc
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/syscall_emul.hh
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/tests/test-progs/mwait/mwait.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/tlm/main.cc
/gem5/util/tlm/sc_mm.cc
/gem5/util/tlm/sc_port.cc
/gem5/util/tlm/sc_target.cc
11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/fault_model/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
SimpleLink.cc
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.py
/gem5/src/mem/slicc/ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11171:60d4dfa3241a 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

Not required since functional reads cannot rely on messages that are inflight.

11124:5d38dc2f7d66 24-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11113:5a2e1b1b5c43 16-Sep-2015 Joe Gross <joe.gross@amd.com>

ruby: fix message buffer init order

The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.

11111:6da33e720481 16-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer, timer table: significant changes

This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby. These structures would no longer
maintain pointers to clock objects. Functions in these structures have been
changed to take as input current time in Tick. Similarly, these structures
will not operate on Cycle valued latencies for different operations. The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions. These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby. The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes. This object would be used for
scheduling events. The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system. That change led to introduction
of clock objects that replaced the global clock object. It never crossed my
mind that having clock object pointers is not a good design. And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.


/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBuffer.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
PerfectSwitch.cc
SimpleNetwork.py
Switch.cc
Throttle.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/ObjDeclAST.py
/gem5/src/mem/slicc/ast/PeekStatementAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11108:6342ddf6d733 16-Sep-2015 David Hashe <david.hashe@amd.com>

ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.


/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
SimpleNetwork.cc
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11093:8049ffff6d68 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer(). This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.

11092:a51ef09e3a78 12-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events. A follow on patch removes the consumer class. So the
PerfectSwitch needs some EventManager object to schedule events on its own.

11064:386a5200e298 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: drop member m_in_use

This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.

Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/FuncDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11047:dcf729f0bbfa 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: refactor code

Drops an unused variable and marks three variables as const.

11037:91d6a2d95cf8 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: simple network: store Switch* in PerfectSwitch and Throttle

11036:3de670f298b1 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove unused functionalRead() function.

11035:690ecdba9324 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: perfect switch: refactor code

Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer().

11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

10920:58fbfddff18d 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.

10919:80069a602c83 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

10918:dd3ab1f109ad 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.

10917:c38f28fad4c3 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: remove extra whitespace and correct misspelled words

10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10370:4466307b8a2a 15-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: revert some of the changes from ad9c042dce54
The changeset ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.

10348:c91b23c72d5e 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use the global Mersenne twister throughout

This patch tidies up random number generation to ensure that it is
done consistently throughout the code base. In essence this involves a
clean-up of Ruby, and some code simplifications in the traffic
generator.

As part of this patch a bunch of skewed distributions (off-by-one etc)
have been fixed.

Note that a single global random number generator is used, and that
the object instantiation order will impact the behaviour (the sequence
of numbers will be unaffected, but if module A calles random before
module B then they would obviously see a different outcome). The
dependency on the instantiation order is true in any case due to the
execution-model of gem5, so we leave it as is. Also note that the
global ranom generator is not thread safe at this point.

Regressions using the memtest, TrafficGen or any Ruby tester are
affected and will be updated accordingly.

10312:08f4deeb5b48 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: PerfectSwitch: moves code to a per vnet helper function
This patch moves code from the wakeup() function to a operateVnet().
The aim is to improve the readiblity of the code.

10311:ad9c042dce54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.


/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
10303:71e0934af9f1 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move getNumNodes() to base class
All the implementations were doing the same things.

10301:44839e8febbd 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.


/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/buffers/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBufferNode.cc
/gem5/src/mem/ruby/network/MessageBufferNode.hh
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
PerfectSwitch.cc
SimpleNetwork.cc
Switch.cc
Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/structures/SparseMemory.cc
/gem5/src/mem/ruby/structures/SparseMemory.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/structures/WireBuffer.hh
/gem5/src/mem/ruby/structures/WireBuffer.py
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BankedArray.cc
/gem5/src/mem/ruby/system/BankedArray.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/Type.py
10226:056363356d15 23-May-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.

10082:70f350b13ec0 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move message buffers to base network class.

10076:f81d94b53661 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes unused code.

10074:0e013fa647ac 20-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffer: removes some unecessary functions.

9866:94dac7d7bb88 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

ruby: Statically allocate stats in SimpleNetwork, Switch, Throttle

The previous changeset (9863:9483739f83ee) used STL vector containers to
dynamically allocate stats in the Ruby SimpleNetwork, Switch and Throttle. For
gcc versions before at least 4.6.3, this causes the standard vector allocator
to call Stats copy constructors (a no-no, since stats should be allocated in
the body of each SimObject instance). Since the size of these stats arrays is
known at compile time (NOTE: after code generation), this patch changes their
allocation to be static rather than using an STL vector.

9863:9483739f83ee 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: convert to gem5 style stats

9859:1bd310386038 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: removes reset functionality

9858:f2417ecf5cc9 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: shorten variable names

9799:5aed42e54180 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: remove reconfiguration code
This code seems not to be of any use now. There is no path in the simulator
that allows for reconfiguring the network. A better approach would be to
take a checkpoint and start the simulation from the checkpoint with the new
configuration.

9593:9441ca79f3c8 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move routers from topology to network

9554:406fbcf60223 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

9508:dde110931867 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

9506:f5335ac67f41 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles in garnet fixed and flexible


/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
Throttle.hh
9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
PerfectSwitch.cc
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9496:28d88a0fda74 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.

9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.


/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
PerfectSwitch.cc
PerfectSwitch.hh
Switch.cc
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
9389:8f8c911ab5a7 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix missing cxx_header in Switch

This patch addresses a warning related to the swig interface
generation for the Switch class. The cxx_header is now specified
correctly, and the header in question has got a few includes added to
make it all compile.

9354:7691ec6b173b 10-Nov-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: support functional accesses in garnet flexible network

9338:97b4a2be1e5b 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.


/gem5/src/SConscript
/gem5/src/arch/alpha/AlphaInterrupts.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmInterrupts.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/mips/MipsInterrupts.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerInterrupts.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/sparc/SparcInterrupts.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/bios/ACPI.py
/gem5/src/arch/x86/bios/E820.py
/gem5/src/arch/x86/bios/IntelMP.py
/gem5/src/arch/x86/bios/SMBios.py
/gem5/src/base/CPA.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/ExeTracer.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntelTrace.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/LegionTrace.py
/gem5/src/cpu/NativeTrace.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/inorder/InOrderTrace.py
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/CopyEngine.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Terminal.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/realview.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/sparc/T1000.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/X86IntPin.py
/gem5/src/dev/x86/speaker.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SimpleDRAM.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/iic_repl/Repl.py
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
SimpleLink.py
SimpleNetwork.py
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/BaseTLB.py
/gem5/src/sim/ClockedObject.py
/gem5/src/sim/InstTracer.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/System.py
9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


/gem5/configs/example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/network/Network.hh
PerfectSwitch.cc
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
9275:ef43e69c837a 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: makes some members non-static
This patch makes some of the members (profiler, network, memory vector)
of ruby system non-static.

9274:ba635023d4bb 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Consumer.cc
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
PerfectSwitch.cc
Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9117:49116b947194 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.


/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
9116:9171e26543fa 12-Jul-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove some unused stuff from SLICC files

8645:89929730804b 31-Dec-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Shuffle some of the included files
This patch adds and removes included files from some of the files so as to
organize remove some false dependencies and include some files directly
instead of transitively.

8608:02d7ac5fb855 03-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.


/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.hh
Throttle.cc
Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
8530:3aaa99208a84 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused code

8492:1ad244a20877 08-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.

8485:7a9a7f2a3d46 03-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove files and includes not in use

8308:79cf09f5a234 18-May-2011 Tushar Krishna <tushar@csail.mit.edu>

slicc: added vnet_type field to identify response vnets from others

Identifying response vnets versus other vnets will allow garnet to
determine which vnets will carry data packets, and which will carry
ctrl packets, and use appropriate buffer sizes (since data packets are larger
than ctrl packets). This in turn allows the orion power model to accurately
estimate buffer power.

8266:66a3187a6714 02-May-2011 Korey Sewell <ksewell@umich.edu>

ruby: dbg: use system ticks instead of cycles

8261:39e42ccddd63 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: adjusted default endpoint bandwidth

The simple network's endpoint bandwidth value is used to adjust the overall
bandwidth of the network. Specifically, the ration between endpoint bandwidth
and the MESSAGE_SIZE_MULTIPLIER determines the increase. By setting the value
to 1000, that means the bandwdith factor specified in the links translates to
the link bandwidth in bytes. Previously, it was increasing that value by 10.

This patch will likely require a reset of the ruby regression tester stats.

8259:36987780169e 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: moved network config params

Moved the buffer_size, endpoint_bandwidth, and adaptive_routing params out of
the top-level parent network object and to only those networks that actually
use those parameters.

8258:7c377f5162f8 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

8257:7226aebb77b4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.


/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/network/BasicLink.cc
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/SConscript
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
SimpleNetwork.cc
SimpleNetwork.hh
/gem5/src/mem/ruby/network/topologies/Crossbar.py
/gem5/src/mem/ruby/network/topologies/Mesh.py
/gem5/src/mem/ruby/network/topologies/MeshDirCorners.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
8255:73089f793a0a 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: moved topology to the top network directory

Moved the Topology class to the top network directory because it is shared by
both the simple and Garnet networks.

8254:779d775abc11 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed dated comment in SimpleNetwork

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/debug.cc
/gem5/src/base/debug.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/mysql.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
PerfectSwitch.cc
Throttle.cc
Topology.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/ozone_base_dyn_inst.cc
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/simple_base_dyn_inst.cc
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_device.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
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/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/platform.hh
/gem5/src/dev/ps2.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/terminal.cc
/gem5/src/dev/terminal.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base.cc
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/cacheset.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.cc
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/Register.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.hh
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc
/gem5/src/mem/ruby/network/orion/Clock.cc
/gem5/src/mem/ruby/network/orion/ConfigFile.hh
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh
/gem5/src/mem/ruby/network/orion/FlipFlop.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/OrionConfig.cc
/gem5/src/mem/ruby/network/orion/OrionConfig.hh
/gem5/src/mem/ruby/network/orion/OrionLink.cc
/gem5/src/mem/ruby/network/orion/OrionRouter.cc
/gem5/src/mem/ruby/network/orion/TechParameter.cc
/gem5/src/mem/ruby/network/orion/Wire.cc
/gem5/src/mem/ruby/network/orion/orion.hh
PerfectSwitch.hh
Switch.cc
Throttle.cc
Throttle.hh
Topology.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/inet.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/stats.i
/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8101:2e1ee8ec6266 01-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Fix DPRINTF bugs in PerfectSwitch and MessageBuffer
At a couple of places in PerfectSwitch.cc and MessageBuffer.cc, DPRINTF()
has not been provided with correct number of arguments. The patch fixes these
bugs.

8054:9138d38eccd7 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer

7973:e5550966464a 14-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three loops -

loop on number of virtual networks
loop on number of incoming links
loop till all messages for this (link, network) have been routed

With an 8 processor mesh network and Hammer protocol, about 11-12% of the
was observed to have been spent in this function, which is the highest
amongst all the functions. It was found that the innermost loop is executed
about 45 times per invocation of the wakeup function, when each invocation
of the wakeup function processes just about one message.

The patch tries to do away with the redundant executions of the innermost
loop. Counters have been added for each virtual network that record the
number of messages that need to be routed for that virtual network. The
inner loops are only executed when the number of messages for that particular
virtual network > 0. This does away with almost 80% of the executions of the
innermost loop. The function now consumes about 5-6% of the total execution
time.

7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.


/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/mem/SConscript
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
PerfectSwitch.cc
Throttle.cc
Topology.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
7547:a5ddcb2abfa1 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added consolidated network msg stats

7455:586f99bf0dc4 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of the Map class

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
Topology.cc
Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7056:b66b558578bd 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
PerfectSwitch.cc
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Throttle.cc
Throttle.hh
Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/LiteralExprAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7054:7d6862b80049 31-Mar-2010 Nathan Binkert <nate@binkert.org>

style: another ruby style pass


/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
HierarchicalSwitchTopology.cc
HierarchicalSwitchTopology.hh
PerfectSwitch.cc
PerfectSwitch.hh
PtToPtTopology.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
Topology.cc
Topology.hh
Torus2DTopology.cc
Torus2DTopology.hh
/gem5/src/mem/ruby/network/topologies/Crossbar.py
/gem5/src/mem/ruby/network/topologies/Mesh.py
/gem5/src/mem/ruby/network/topologies/MeshDirCorners.py
/gem5/src/mem/ruby/network/topologies/SConscript
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
7024:30883414ad10 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Finally removed bash code cira. 2001ish!

7020:34a5bdcce1e6 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed the obsolete file specified network files


Network_Files/GarnetFileMaker.py
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
Network_Files/NetworkFileMaker.py
Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
7019:a49fd5febdce 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added copyright to many Ruby *.py files

7002:48a19d52d939 10-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed


/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
PerfectSwitch.cc
PerfectSwitch.hh
Switch.cc
Switch.hh
Topology.cc
Topology.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
6895:5f3d2d3f977e 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added ruby stats print
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.

6891:77451885bb00 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.

6881:5a61a8a9009a 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: connects sm queues to the network

6879:c07cf29b5a33 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Add support for generating topologies in Python.

6876:a658c315512c 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.


/gem5/configs/example/memtest-ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Debug.py
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/config/MESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MOESI_CMP_token.rb
/gem5/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
/gem5/src/mem/ruby/config/MOESI_hammer.rb
/gem5/src/mem/ruby/config/SConscript
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/assert.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/util.rb
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/SConscript
/gem5/src/mem/ruby/network/orion/SConscript
HierarchicalSwitchTopology.hh
PtToPtTopology.hh
SConscript
SimpleNetwork.cc
SimpleNetwork.hh
SimpleNetwork.py
Topology.cc
Topology.hh
Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/profiler/SConscript
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
6875:5eb6e323b595 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: get rid of obsolete, unused CustomTopology class.

6846:60e0df8086f0 17-Sep-2009 Polina Dudnik <pdudnik@cs.wisc.edu>

Functionality migrated to sequencer.

6838:829892ec644c 14-Sep-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed stray printf

6795:394bc95d417b 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed the chip pointer from MessageBuffer
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.

6781:8da9d36fc14a 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added default names to message buffers
Added default names to message buffers created by the simple network.

6762:a22a47e60c21 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby destruction fix.

6493:1fa51760a963 07-Aug-2009 Tushar Krishna <Tushar.Krishna@amd.com>

bug fix for data_msg_size in network/Network.cc

6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
PerfectSwitch.cc
SimpleNetwork.cc
Throttle.cc
Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/Type.cc
6371:a1768b396928 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed dead files

6294:b42cea5e1625 08-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

removed stray debug print

6288:083a6806dd96 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: apply some fixes that were overwritten by the recent ruby import.

6286:40b142645016 06-Jul-2009 Nathan Binkert <nate@binkert.org>

scons: update SCons files for changes in ruby.

6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
CustomTopology.cc
CustomTopology.hh
HierarchicalSwitchTopology.cc
HierarchicalSwitchTopology.hh
PerfectSwitch.cc
PtToPtTopology.cc
PtToPtTopology.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
Topology.cc
Topology.hh
Torus2DTopology.cc
Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/ProcessorInterface.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Driver_Tester.cc
/gem5/src/mem/ruby/tester/Driver_Tester.hh
/gem5/src/mem/ruby/tester/EventQueue_Tester.hh
/gem5/src/mem/ruby/tester/Global_Tester.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
PerfectSwitch.cc
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Throttle.cc
Topology.cc
Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6168:ba6fe02228db 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false

6157:eaf2fd8f54c0 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.

6156:76de2027b8ad 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: clean up a few warnings

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
Topology.cc
Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
6153:0011560d49b0 11-May-2009 Dan Gibson <gibson@cs.wisc.edu>

ruby: remove unnecessary code.

1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.

2) Most of the dependencies on Simics data types and the simics
interface files have been removed.

3) Almost all mention of opal is gone.

4) Huge chunks of LogTM are now gone.

5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).


/gem5/src/mem/gems_common/ioutil/FakeSimicsDataTypes.hh
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
Topology.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
/gem5/src/mem/ruby/simics/interface.cc
/gem5/src/mem/ruby/simics/interface.hh
/gem5/src/mem/ruby/simics/simics_api_dummy.c
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/test_framework.cc
6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_SMP_directory-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_directory.slicc
/gem5/src/mem/protocol/MOESI_SMP_token-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_token.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_m-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_m.slicc
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level.slicc
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/doc/MSI_MOSI_CMP_directory_2level-protocol-description.txt
/gem5/src/mem/protocol/doc/MSI_dir_L1_MOSI_dir_L2_SNUCA_CMP-protocol-description.txt
/gem5/src/mem/protocol/standard_1level_SMP-protocol.sm
/gem5/src/mem/protocol/standard_CMP-protocol.sm
/gem5/src/mem/protocol/standard_SMP-protocol.sm
/gem5/src/mem/ruby/Decomissioning_note
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/README.debugging
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/common/Address.cc
/gem5/src/mem/ruby/common/Address.hh
/gem5/src/mem/ruby/common/BigSet.cc
/gem5/src/mem/ruby/common/BigSet.hh
/gem5/src/mem/ruby/common/Consumer.hh
/gem5/src/mem/ruby/common/DataBlock.cc
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.def
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Driver.cc
/gem5/src/mem/ruby/common/Driver.hh
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/Message.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/NetDest.hh
/gem5/src/mem/ruby/common/OptBigSet.cc
/gem5/src/mem/ruby/common/OptBigSet.hh
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/config.include
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/EventQueue.cc
/gem5/src/mem/ruby/eventqueue/EventQueue.hh
/gem5/src/mem/ruby/eventqueue/EventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/EventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/EventQueue_tester.cc
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
/gem5/src/mem/ruby/interfaces/mf_api.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/SIM_port.hh
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/SIM_power_test.hh
/gem5/src/mem/ruby/network/orion/parm_technology.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_array.hh
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_bus.hh
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_ll.hh
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/orion/power_utils.hh
Network_Files/GarnetFileMaker.py
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
Network_Files/NetworkFileMaker.py
Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
PerfectSwitch.cc
PerfectSwitch.hh
SimpleNetwork.cc
SimpleNetwork.hh
Switch.cc
Switch.hh
Throttle.cc
Throttle.hh
Topology.cc
Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
/gem5/src/mem/ruby/simics/interface.cc
/gem5/src/mem/ruby/simics/interface.hh
/gem5/src/mem/ruby/simics/simics_api_dummy.c
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractProtocol.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/README
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/doc/SLICC_V03.txt
/gem5/src/mem/slicc/doc/tutorial.tex
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh