History log of /gem5/src/mem/ruby/common/
Revision Date Author Comments
(<<< Hide modified files)
(Show modified files >>>)
14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/learning_gem5/part3/MSI-cache.sm
/gem5/src/learning_gem5/part3/SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
MachineID.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_RfO.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/ruby/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone.slicc
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level.slicc
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level.slicc
/gem5/src/mem/ruby/protocol/MI_example-cache.sm
/gem5/src/mem/ruby/protocol/MI_example-dir.sm
/gem5/src/mem/ruby/protocol/MI_example-dma.sm
/gem5/src/mem/ruby/protocol/MI_example-msg.sm
/gem5/src/mem/ruby/protocol/MI_example.slicc
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/ruby/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer.slicc
/gem5/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Defines.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/ruby/protocol/SConscript
/gem5/src/mem/ruby/protocol/SConsopts
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
14037:a1e12c851596 20-Apr-2017 John Alsop <johnathan.alsop@amd.com>

mem-ruby: Enable set size increase

Add NUMBER_BITS_PER_SET environment variable to control
the size of the bitmask in Set.hh (default=64).
Necessary for configs which require >64 instances of a given
machine type. This can be set in the build_opts file, e.g.
by adding the following line:
NUMBER_BITS_PER_SET = <number>

Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18968
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

12697:cd71b966be1e 27-Apr-2018 Tony Gutierrez <anthony.gutierrez@amd.com>

style: fix amd license and style issues

Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5
Reviewed-on: https://gem5-review.googlesource.com/10463
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>


/gem5/configs/example/apu_se.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
IntVec.cc
IntVec.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.hh
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/sim/aux_vector.cc
/gem5/src/sim/aux_vector.hh
/gem5/src/sim/fd_array.cc
/gem5/src/sim/fd_array.hh
/gem5/src/sim/fd_entry.cc
/gem5/src/sim/fd_entry.hh
12492:4e76959883a6 05-Feb-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem: Standardize mem folder header guards

Standardize all header guards in the mem directory according to the most
frequent patterns. In general they have the form:
mem: __FOLDER_TREE_FILE_NAME_HH__
ruby: __FOLDER_TREE_FILENAME_HH__

Change-Id: I983853e292deb302becf151bf0e970057dc24774
Reviewed-on: https://gem5-review.googlesource.com/7881
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>


/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/external_master.hh
/gem5/src/mem/external_slave.hh
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/hmc_controller.hh
BoolVec.hh
IntVec.hh
MachineID.hh
TypeDefines.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/garnet2.0/CommonTypes.hh
/gem5/src/mem/ruby/network/garnet2.0/Credit.hh
/gem5/src/mem/ruby/network/garnet2.0/CreditLink.hh
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.hh
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/Router.hh
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
/gem5/src/mem/ruby/network/garnet2.0/flit.hh
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/SimpleLink.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/simple_mem.hh
12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
/gem5/src/dev/storage/disk_image.cc
/gem5/src/dev/storage/simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
Set.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12133:ca42be3276af 28-Jun-2017 Sean Wilson <spwilson2@wisc.edu>

ruby: Refactor some Event subclasses to lambdas

Change-Id: I9f47a20a869553515a759d9a29c05f6ce4b42d64
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3930
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
Histogram.cc
NetDest.cc
SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11712:70052ef97ce1 21-Nov-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

ruby: add default ctor for MachineID type

not all uses of MachineID initialize its fields, so here we add a default
ctor.

11325:67cc559d513a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: eliminate explicit boolean comparisons

Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<

11307:bd7d06ea90f5 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

mem: write combining for ruby protocols

This patch adds support for write-combining in ruby.

11305:78c1e4f5dfc5 20-Jul-2015 Blake Hechtman <blake.hechtman@amd.com>

mem: misc flags for AMD gpu model

This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.

11210:64c0ebeae224 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added stl vector of ints to be used by SLICC

11208:fa3e56b6e0b6 13-Nov-2015 Joe Gross <joseph.gross@amd.com>

ruby: add BoolVec

The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool

11168:f98eb2da15a4 12-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.


/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/kernel_stats.hh
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/arm/isa_device.hh
/gem5/src/arch/arm/kvm/armv8_cpu.hh
/gem5/src/arch/arm/kvm/base_cpu.hh
/gem5/src/arch/arm/kvm/gic.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/pmu.hh
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/regs/msr.hh
/gem5/src/arch/x86/tlb.hh
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/base/compiler.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/framebuffer.hh
/gem5/src/base/hashmap.hh
/gem5/src/base/inifile.hh
/gem5/src/base/pollevent.hh
/gem5/src/base/random.hh
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/base.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/decode_cache.hh
/gem5/src/cpu/inst_pb_trace.hh
/gem5/src/cpu/kvm/base.hh
/gem5/src/cpu/kvm/x86_cpu.hh
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/pred/bpred_unit.hh
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/exec_context.hh
/gem5/src/cpu/simple/probes/simpoint.hh
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/traffic_gen/traffic_gen.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/alpha/tsunami.hh
/gem5/src/dev/alpha/tsunami_cchip.hh
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.hh
/gem5/src/dev/arm/energy_ctrl.hh
/gem5/src/dev/arm/flash_device.hh
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.hh
/gem5/src/dev/arm/gpu_nomali.hh
/gem5/src/dev/arm/hdlcd.hh
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl011.hh
/gem5/src/dev/arm/pl111.hh
/gem5/src/dev/arm/rtc_pl031.hh
/gem5/src/dev/arm/rv_ctrl.hh
/gem5/src/dev/arm/timer_cpulocal.hh
/gem5/src/dev/arm/timer_sp804.hh
/gem5/src/dev/arm/ufs_device.hh
/gem5/src/dev/arm/vgic.hh
/gem5/src/dev/copy_engine.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/disk_image.hh
/gem5/src/dev/dma_device.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.hh
/gem5/src/dev/i2cbus.hh
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/multi_etherlink.hh
/gem5/src/dev/multi_iface.hh
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pixelpump.hh
/gem5/src/dev/sinic.hh
/gem5/src/dev/sparc/dtod.hh
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/tcp_iface.hh
/gem5/src/dev/uart8250.hh
/gem5/src/dev/virtio/base.hh
/gem5/src/dev/virtio/fs9p.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base_set_assoc.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/coherent_xbar.hh
/gem5/src/mem/comm_monitor.hh
/gem5/src/mem/dram_ctrl.hh
/gem5/src/mem/dramsim2.hh
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/multi_level_page_table.hh
/gem5/src/mem/packet_queue.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.hh
/gem5/src/mem/probes/base.hh
/gem5/src/mem/probes/mem_trace.hh
/gem5/src/mem/probes/stack_dist.hh
Address.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/simple_mem.hh
/gem5/src/mem/snoop_filter.hh
/gem5/src/mem/xbar.hh
/gem5/src/sim/clock_domain.hh
/gem5/src/sim/dvfs_handler.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/fd_entry.hh
/gem5/src/sim/process.hh
/gem5/src/sim/root.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_object.hh
/gem5/src/sim/system.hh
/gem5/src/sim/ticked_object.hh
/gem5/src/sim/voltage_domain.hh
11118:75c1e564a725 18-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.

11108:6342ddf6d733 16-Sep-2015 David Hashe <david.hashe@amd.com>

ruby: rename System.{hh,cc} to RubySystem.{hh,cc}

The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.


Address.cc
DataBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/RubySystem.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
11085:f1fe63d949c0 05-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: reimplement using std::bitset
The current Set data structure is slow and therefore is being reimplemented
using std::bitset. A maximum limit of 64 is being set on the number of
controllers of each type. This means that for simulating a system with more
controllers of a given type, one would need to change the value of the variable
NUMBER_BITS_PER_SET

11061:25b53a7195f7 29-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


/gem5/configs/ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
DataBlock.hh
Histogram.cc
Histogram.hh
SubBlock.cc
SubBlock.hh
TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/FuncDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11042:d34a75cb3646 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: DataBlock: adds a comment

11040:ec668f8466eb 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: SubBlock: refactor code

11031:3815437cb231 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type uint64 and int64

These types are being replaced with uint64_t and int64_t.

11025:4872dbdea907 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system.
This memory system would now use the type Addr that is in use by the
rest of the system.


/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
Address.cc
Address.hh
SubBlock.cc
SubBlock.hh
TypeDefines.hh
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
10920:58fbfddff18d 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_abs_controls with per-RubySystem var

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.

Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.

10919:80069a602c83 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

10918:dd3ab1f109ad 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: replace g_ruby_start with per-RubySystem m_start_cycle

This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.

This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.

10895:287285860dd6 04-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: drop NetworkMessage class

This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.

10808:c1694b4032a6 29-Apr-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: replace long by unsigned long
UBSan complains about negative value being shifted

10563:755b18321206 02-Dec-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Add const getters for write packet data

This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.

10466:73b7549d979e 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Dynamically determine page bytes in memory components

This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.

10348:c91b23c72d5e 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

base: Use the global Mersenne twister throughout

This patch tidies up random number generation to ensure that it is
done consistently throughout the code base. In essence this involves a
clean-up of Ruby, and some code simplifications in the traffic
generator.

As part of this patch a bunch of skewed distributions (off-by-one etc)
have been fixed.

Note that a single global random number generator is used, and that
the object instantiation order will impact the behaviour (the sequence
of numbers will be unaffected, but if module A calles random before
module B then they would obviously see a different outcome). The
dependency on the instantiation order is true in any case due to the
execution-model of gem5, so we leave it as is. Also note that the
global ranom generator is not thread safe at this point.

Regressions using the memtest, TrafficGen or any Ruby tester are
affected and will be updated accordingly.

10318:98771a936b61 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

arch: Cleanup unused ISA traits constants

This patch prunes unused values, and also unifies how the values are
defined (not using an enum for ALPHA), aligning the use of int vs Addr
etc.

The patch also removes the duplication of PageBytes/PageShift and
VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical
values and the latter has been removed.

10314:94b6b28fc968 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove typedef of Index as int64
The Index type defined as typedef int64 does not really provide any help
since in most places we use primitive types instead of Index. Also, the name
Index is very generic that it does not merit being used as a typename.

10302:0e9e99e6369a 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.

10301:44839e8febbd 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.


/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/buffers/SConscript
MachineID.hh
NetDest.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/MessageBufferNode.cc
/gem5/src/mem/ruby/network/MessageBufferNode.hh
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.cc
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/structures/SparseMemory.cc
/gem5/src/mem/ruby/structures/SparseMemory.hh
/gem5/src/mem/ruby/structures/TBETable.hh
/gem5/src/mem/ruby/structures/TimerTable.cc
/gem5/src/mem/ruby/structures/TimerTable.hh
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/structures/WireBuffer.hh
/gem5/src/mem/ruby/structures/WireBuffer.py
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BankedArray.cc
/gem5/src/mem/ruby/system/BankedArray.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/ruby/system/WireBuffer.py
/gem5/src/mem/slicc/symbols/Type.py
10123:e958cdc5c669 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: consumer: avoid accessing wakeup times when waking up
Each consumer object maintains a set of tick values when the object is supposed
to wakeup and do some processing. As of now, the object accesses this set both
when scheduling a wakeup event and when the object actually wakes up. The set
is accessed during wakeup to remove the current tick value from the set. This
functionality is now being moved to the scheduling function where ticks are
removed at a later time.

10115:0e0a0dd558db 17-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove some of the unnecessary code

10086:bd1089db3a88 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove few not required #includes

10005:8c2b0dc16ccd 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for clusters

A cluster over here means a set of controllers that can be accessed only by a
certain set of cores. For example, consider a two level hierarchy. Assume
there are 4 L1 controllers (private) and 2 L2 controllers. We can have two
different hierarchies here:

a. the address space is partitioned between the two L2 controllers. Each L1
controller accesses both the L2 controllers. In this case, each L1 controller
is a cluster initself.

b. both the L2 controllers can cache any address. An L1 controller has access
to only one of the L2 controllers. In this case, each L2 controller
along with the L1 controllers that access it, form a cluster.

This patch allows for each controller to have a cluster ID, which is 0 by
default. By setting the cluster ID properly, one can instantiate hierarchies
with clusters. Note that the coherence protocol might have to be changed as
well.

10004:5d8b72563869 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: some small changes

9995:2df9c3856989 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: declare variables to be unsigned in Address.hh

9773:915be89faf30 25-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: lots of inter-related changes
The patch started of with removing the global variables from the profiler for
profiling the miss latency of requests made to the cache. The corrresponding
histograms have been moved to the Sequencer. These are combined together when
the histograms are printed. Separate histograms are now maintained for
tracking latency of all requests together, of hits only and of misses only.

A particular set of histograms used to use the type GenericMachineType defined
in one of the protocol files. This patch removes this type. Now, everything
that relied on this type would use MachineType instead. To do this, SLICC has
been changed so that multiple machine types can be declared by a controller
in its preamble.

9744:9ab496e12335 09-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove undefined functions in Address class

9670:fa4eedccce17 23-Apr-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: patch checkpoint restore with garnet
Due to recent changes to clocking system in Ruby and the way Ruby restores
state from a checkpoint, garnet was failing to run from a checkpointed state.
The problem is that Ruby resets the time to zero while warming up the caches.
If any component records a local copy of the time (read calls curCycle())
before the simulation has started, then that component will not operate until
that time is reached. In the context of this particular patch, the Garnet
Network class calls curCycle() at multiple places. Any non-operational
component can block in requests in the memory system, which the system
interprets as a deadlock. This patch makes changes so that Garnet can
successfully run from checkpointed state.

It adds a globally visible time at which the actual execution started. This
time is initialized in RubySystem::startup() function. This variable is only
meant for components with in Ruby. This replaces the private variable that
was maintained within Garnet since it is not possible to figure out the
correct time when the value of this variable can be set.

The patch also does away with all cases where curCycle() is called with in
some Ruby component before the system has actually started executing. This
is required due to the quirky manner in which ruby restores from a checkpoint.

9600:34df8f24be7e 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: consumer: avoid using receiver side clock
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.

9586:3c62e3b7f658 15-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: set: corrects csprintf() call introduced by 7d95b650c9b6

9557:8666e81607a6 19-Feb-2013 Andreas Hansson <andreas.hansson@arm.com>

scons: Fix warnings issued by clang 3.2svn (XCode 4.6)

This patch fixes the warnings that clang3.2svn emit due to the "-Wall"
flag. There is one case of an uninitialised value in the ARM neon ISA
description, and then a whole range of unused private fields that are
pruned.

9507:d2ab6d889fc7 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace
Time with Cycles.This patch further replaces Time with Cycles in Sequencer,
Profiler, different protocols and related entities.

Though Time has not been completely removed, the places where it is in use
seem benign as of now.

9499:b03b556a8fbb 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.


/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Consumer.cc
Consumer.hh
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9497:2759161b9d7f 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: modifies histogram add() function
This patch modifies the Histogram class' add() function so that it can add
linear histograms as well. The function assumes that the left end point of
the ranges of the two histograms are the same. It also assumes that when
the ranges of the two histogram are changed to accomodate an element not in
the range, the factor used in changing the range is same for both the
histograms.

This function is then used in removing one of the calls to the global
profiler*. The histograms for recording the delays incurred in processing
different requests are now maintained by the controllers. The profiler
adds these histograms when it needs to print the stats.

9496:28d88a0fda74 10-Feb-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.

9466:23e13ad7091f 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.

In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.


Global.hh
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/structures/Prefetcher.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.py
/gem5/src/mem/slicc/symbols/Type.py
9465:4ae4f3f4b870 14-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.


/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
Consumer.cc
Consumer.hh
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
9362:d7f4abbf52e3 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add functions for computing next stride/page address

9231:cecc64db9b3b 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: eliminate typedef integer_t

9230:33eb3c8a98b9 18-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: avoid using g_system_ptr for event scheduling
This patch removes the use of g_system_ptr for event scheduling. Each consumer
object now needs to specify upfront an EventManager object it would use for
scheduling events. This makes the ruby memory system more amenable for a
multi-threaded simulation.

9209:f9633070689b 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Use uint32_t instead of uint32 everywhere

9208:2451e60d4555 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Use uint8_t instead of uint8 everywhere

9206:f6483789d23a 10-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby System: Convert to Clocked Object
This patch moves Ruby System from being a SimObject to recently introduced
ClockedObject.

9181:42807286d6cb 28-Aug-2012 Jason Power <power.jg@gmail.com>

Ruby: Correct DataBlock =operator
The =operator for the DataBlock class was incorrectly interpreting the class
member m_alloc. This variable stands for whether the assigned memory for the
data block needs to be freed or not by the class itself. It seems that the
=operator interpreted the variable as whether the memory is assigned to the
data block. This wrong interpretation was causing values not to propagate
to RubySystem::m_mem_vec_ptr. This caused major issues with restoring from
checkpoints when using a protocol which verified that the cache data was
consistent with the backing store (i.e. MOESI-hammer).

9171:ae88ecf37145 27-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.


/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
Consumer.cc
Consumer.hh
Global.cc
Global.hh
SConscript
TypeDefines.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/SConscript
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/system/WireBuffer.cc
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/ast/AST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
9138:b4d0bdb52694 01-Aug-2012 Jason Power <powerjg@cs.wisc.edu>

Ruby NetDest: add assert for bad element in netdest

9012:6d64aa6a26af 22-May-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Remove the unused src/mem/ruby/common/Driver.* files.

8946:fb6c89334b86 14-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.

The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:

1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.

2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.

3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.

As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".

8916:7d95b650c9b6 23-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Fix Set::print for 32-bit hosts

This patch fixes a compilation error caused by a length mismatch on
32-bit hosts. The ifdef and sprintf is replaced by a csprintf.

8913:8b223e308b08 22-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Scons: Remove Werror=False in SConscript files

This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.

8650:33a48f15e94a 06-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh
This constant is currently in System.hh, but is only used in Set.hh. It
is being moved to Set.hh to remove this artificial dependence of Set.hh
on System.hh.

8608:02d7ac5fb855 03-Nov-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.

8530:3aaa99208a84 29-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove some unused code

8529:00ca5af1b954 26-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Eliminate modulo op for computing set size.

8492:1ad244a20877 08-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.

8485:7a9a7f2a3d46 03-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Remove files and includes not in use

8351:f897d0483b06 14-Jun-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Correct set LONG_BITS and INDEX_SHIFT in class Set.
The code for Set class was written under the assumption that
std::numeric_limits<long>::digits returns the number of bits used for
data type long, which was presumed to be either 32 or 64. But return value
is actually one less, that is, it is either 31 or 63. The value is now
being incremented by 1 so as to correctly set it.

8232:b28d06a175be 15-Apr-2011 Nathan Binkert <nate@binkert.org>

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help


/gem5/src/SConscript
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/predecoder.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/types.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.hh
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/debug.cc
/gem5/src/base/debug.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/mysql.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/SConscript
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resources/agen_unit.cc
/gem5/src/cpu/inorder/resources/bpred_unit.cc
/gem5/src/cpu/inorder/resources/branch_predictor.cc
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/decode_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/fetch_seq_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/graduation_unit.cc
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/copy_engine.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ethertap.cc
/gem5/src/dev/i8254xGBe.cc
/gem5/src/dev/i8254xGBe.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pcidev.cc
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/terminal.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/system_events.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.cc
/gem5/src/python/m5/debug.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/trace.py
/gem5/src/python/swig/debug.i
/gem5/src/python/swig/trace.i
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/ozone_base_dyn_inst.cc
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/simple_base_dyn_inst.cc
/gem5/src/cpu/ozone/simple_cpu_builder.cc
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/sched_list.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/testers/networktest/networktest.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/alpha/tsunami_io.hh
/gem5/src/dev/alpha/tsunami_pchip.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_device.hh
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/kmi.hh
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/platform.hh
/gem5/src/dev/ps2.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/iob.hh
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/mm_disk.hh
/gem5/src/dev/terminal.cc
/gem5/src/dev/terminal.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/base.cc
/gem5/src/mem/cache/tags/base.hh
/gem5/src/mem/cache/tags/cacheset.hh
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
NetDest.cc
Set.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/Allocator/Arbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.cc
/gem5/src/mem/ruby/network/orion/Allocator/RRArbiter.hh
/gem5/src/mem/ruby/network/orion/Allocator/SWAllocator.cc
/gem5/src/mem/ruby/network/orion/Allocator/VCAllocator.cc
/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
/gem5/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh
/gem5/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc
/gem5/src/mem/ruby/network/orion/Buffer/Register.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.cc
/gem5/src/mem/ruby/network/orion/Buffer/SRAM.hh
/gem5/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc
/gem5/src/mem/ruby/network/orion/Clock.cc
/gem5/src/mem/ruby/network/orion/ConfigFile.hh
/gem5/src/mem/ruby/network/orion/Crossbar/Crossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc
/gem5/src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh
/gem5/src/mem/ruby/network/orion/FlipFlop.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/OrionConfig.cc
/gem5/src/mem/ruby/network/orion/OrionConfig.hh
/gem5/src/mem/ruby/network/orion/OrionLink.cc
/gem5/src/mem/ruby/network/orion/OrionRouter.cc
/gem5/src/mem/ruby/network/orion/TechParameter.cc
/gem5/src/mem/ruby/network/orion/Wire.cc
/gem5/src/mem/ruby/network/orion/orion.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/WireBuffer.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/tport.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/vport.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/inet.i
/gem5/src/python/swig/pyobject.cc
/gem5/src/python/swig/sim_object.i
/gem5/src/python/swig/stats.i
/gem5/src/python/swig/system.i
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/init.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process_impl.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/tlb.cc
/gem5/src/sim/vptr.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/cprintftime.cc
/gem5/src/unittest/initest.cc
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/symtest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/m5.c
/gem5/util/statetrace/arch/amd64/tracechild.cc
/gem5/util/statetrace/arch/amd64/tracechild.hh
/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
/gem5/util/statetrace/arch/i686/tracechild.hh
/gem5/util/statetrace/arch/sparc/tracechild.cc
/gem5/util/statetrace/arch/sparc/tracechild.hh
/gem5/util/statetrace/base/regstate.hh
/gem5/util/statetrace/base/statetrace.cc
/gem5/util/statetrace/base/tracechild.cc
/gem5/util/tap/tap.cc
/gem5/util/term/term.c
8091:04078b1214dd 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Make Address.hh independent of RubySystem
This patch changes Address.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depend on
RubySystem have been moved to Address.cc file.

8090:722a0d28ee83 25-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Make DataBlock.hh independent of RubySystem
This patch changes DataBlock.hh so that it is not dependent on RubySystem.
This dependence seems unecessary. All those functions that depende on
RubySystem have been moved to DataBlock.cc file.

8054:9138d38eccd7 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

ruby: cleaning up RubyQueue and RubyNetwork dprintfs
Overall, continue to progress Ruby debug messages to more of the normal M5
debug message style
- add a name() to the Ruby Throttle & PerfectSwitch objects so that the debug output
isn't littered w/"global:" everywhere.
- clean up messages that print over multiple lines when possible
- clean up duplicate prints in the message buffer

7973:e5550966464a 14-Feb-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Improve Change PerfectSwitch's wakeup function
Currently the wakeup function for the PerfectSwitch contains three loops -

loop on number of virtual networks
loop on number of incoming links
loop till all messages for this (link, network) have been routed

With an 8 processor mesh network and Hammer protocol, about 11-12% of the
was observed to have been spent in this function, which is the highest
amongst all the functions. It was found that the innermost loop is executed
about 45 times per invocation of the wakeup function, when each invocation
of the wakeup function processes just about one message.

The patch tries to do away with the redundant executions of the innermost
loop. Counters have been added for each virtual network that record the
number of messages that need to be routed for that virtual network. The
inner loops are only executed when the number of messages for that particular
virtual network > 0. This does away with almost 80% of the executions of the
innermost loop. The function now consumes about 5-6% of the total execution
time.

7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace

7811:a8fc35183c10 03-Jan-2011 Steve Reinhardt <steve.reinhardt@amd.com>

Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.


/gem5/src/SConscript
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/kernel_stats.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/nativetrace.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/kernel_stats.hh
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/power/faults.hh
/gem5/src/arch/power/insts/branch.hh
/gem5/src/arch/power/insts/condition.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/insts/mem.hh
/gem5/src/arch/power/insts/misc.hh
/gem5/src/arch/power/insts/static_inst.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/isa_traits.hh
/gem5/src/arch/power/locked_mem.hh
/gem5/src/arch/power/microcode_rom.hh
/gem5/src/arch/power/miscregs.hh
/gem5/src/arch/power/mmaped_ipr.hh
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/pagetable.hh
/gem5/src/arch/power/predecoder.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/power/remote_gdb.hh
/gem5/src/arch/power/stacktrace.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/types.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/power/utility.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/kernel_stats.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/nativetrace.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/nativetrace.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/cprintf.hh
/gem5/src/base/hashmap.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/mysql.cc
/gem5/src/base/mysql.hh
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/mysql.hh
/gem5/src/base/stats/mysql_run.hh
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/output.hh
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/stats/types.hh
/gem5/src/base/stats/visit.cc
/gem5/src/base/stats/visit.hh
/gem5/src/base/stl_helpers.hh
/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/varargs.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/nativetrace.hh
/gem5/src/dev/copy_engine_defs.hh
/gem5/src/dev/i8254xGBe_defs.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/x86/cmos.hh
/gem5/src/dev/x86/i8042.hh
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/i8237.hh
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/i8259.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/speaker.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
Address.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/params.py
/gem5/src/python/swig/stats.i
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
7805:f249937228b5 23-Dec-2010 Nilay Vaish<nilay@cs.wisc.edu>

This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh

7793:f6cbeb8712d3 08-Dec-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: remove Ruby asserts for m5.fast

This diff is for changing the way ASSERT is handled in Ruby. m5.fast
compiles out the assert statements by using the macro NDEBUG. Ruby uses the
macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has
been put in its place.

7780:42da07116e12 01-Dec-2010 Nilay Vaish <nilay@cs.wisc.edu>

ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.


/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/mem/SConscript
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/SConsopts
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
Debug.cc
Debug.hh
NetDest.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
7563:406e98960def 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed DirectoryMemory's numa_high_bit configuration

This fix includes the off-by-one bit selection bug for numa mapping.

7454:3a3e8e8cce1b 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream


/gem5/src/base/stl_helpers.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
DataBlock.hh
Histogram.cc
Histogram.hh
NetDest.cc
NetDest.hh
SubBlock.cc
SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
7453:1a5db3dd0f62 11-Jun-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.

7089:9ea24d102d66 01-Jun-2010 Nathan Binkert <nate@binkert.org>

style: clean up ruby's Set class

Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.

There are probably several cases where this class is used, std::bitset
could be used instead.

7056:b66b558578bd 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base

7055:4e24742201d7 02-Apr-2010 Nathan Binkert <nate@binkert.org>

ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.


/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
Address.cc
Address.hh
Driver.hh
NetDest.cc
NetDest.hh
Set.cc
Set.hh
SubBlock.cc
SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/LiteralExprAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7054:7d6862b80049 31-Mar-2010 Nathan Binkert <nate@binkert.org>

style: another ruby style pass


/gem5/src/mem/ruby/SConsopts
Address.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.cc
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.cc
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/network/topologies/Crossbar.py
/gem5/src/mem/ruby/network/topologies/Mesh.py
/gem5/src/mem/ruby/network/topologies/MeshDirCorners.py
/gem5/src/mem/ruby/network/topologies/SConscript
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
7044:8a05ebc9d372 23-Mar-2010 Korey Sewell <ksewell@umich.edu>

m5merge(2): another merge of regression stats

7039:bc0b6ea676b5 22-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: style pass


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Address.cc
Address.hh
Consumer.hh
DataBlock.cc
DataBlock.hh
Debug.cc
Debug.hh
Driver.cc
Driver.hh
Global.cc
Global.hh
Histogram.cc
Histogram.hh
Message.cc
NetDest.cc
NetDest.hh
SConscript
SubBlock.cc
SubBlock.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractProtocol.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/SparseMemory.cc
/gem5/src/mem/ruby/system/SparseMemory.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
7027:46b02e79bf2c 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Adds configurable bit selection for numa mapping

7021:0b3c02da71b3 22-Mar-2010 Tushar Krishna <tushar@csail.mit.edu>

ruby: Fix multiple wakeups in Ruby Eventqueue

Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in
same cycle

7019:a49fd5febdce 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added copyright to many Ruby *.py files

7008:90c097fb76e1 14-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: Fix copyrights on files
Mostly files missed during import or screwed up during import

7002:48a19d52d939 10-Mar-2010 Nathan Binkert <nate@binkert.org>

ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed


/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Address.hh
Consumer.hh
DataBlock.hh
Debug.cc
Debug.hh
Global.hh
Histogram.cc
Histogram.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.cc
/gem5/src/mem/ruby/profiler/MemCntrlProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
6971:12cfde8f819b 10-Feb-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed data block assignment fix

Fixed data block assignment to not delete if not internally allocated.

6899:f8057af86bf7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added the GEMS ruby tester

6896:649e40aad897 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable

6894:fcd9e5ed33f7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed Set.cc bug to allow zero sized sets
This is necessary for example when no dma sequencers are necessary in the
simulated system.

6891:77451885bb00 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.

6876:a658c315512c 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.


/gem5/configs/example/memtest-ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/SConscript
Debug.cc
Debug.hh
Debug.py
SConscript
/gem5/src/mem/ruby/config/MESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MOESI_CMP_token.rb
/gem5/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
/gem5/src/mem/ruby/config/MOESI_hammer.rb
/gem5/src/mem/ruby/config/SConscript
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/assert.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/util.rb
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/SConscript
/gem5/src/mem/ruby/network/orion/SConscript
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SConscript
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/profiler/SConscript
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
6797:7bf0a839c237 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

Resurrection of the CMP token protocol to GEM5

6762:a22a47e60c21 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby destruction fix.

6761:81e9d83f87c0 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby debug print fixes.

6712:b95abe00dd9d 04-Nov-2009 Nathan Binkert <nate@binkert.org>

build: fix compile problems pointed out by gcc 4.4

6631:5437a0eeb822 11-Sep-2009 pdudnik@gmail.com

Object print bug fix

6372:f1a41ea3bbab 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: removed all refs to old RubyConfig


/gem5/src/mem/ruby/buffers/MessageBuffer.cc
Address.hh
NetDest.cc
NetDest.hh
Set.cc
Set.hh
SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/Type.cc
6369:82ac95f4d9f0 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

merge

6367:c4e91b8e3da3 18-Jul-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: better debug print for DataBlock

6357:bd813379f121 15-Jul-2009 pdudnik@gmail.com

Tester update

6355:79464d8a4d2f 13-Jul-2009 pdudnik@gmail.com

1. Got rid of unused functions in DirectoryMemory
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue

Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once

6351:31d19bdd9d85 13-Jul-2009 pdudnik@gmail.com

Minor fixes for compiling

6347:a532849ca78f 13-Jul-2009 Polina pdudnik@gmail.com

Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure

6288:083a6806dd96 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: apply some fixes that were overwritten by the recent ruby import.

6285:ce086eca1ede 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.


/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/standard_1level_CMP-protocol.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
Address.hh
Consumer.hh
DataBlock.cc
DataBlock.hh
Debug.cc
Debug.hh
Driver.hh
Global.hh
Set.cc
SubBlock.cc
SubBlock.hh
TypeDefines.hh
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/config.hh
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/AbstractBloomFilter.hh
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.hh
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.hh
/gem5/src/mem/ruby/filters/GenericBloomFilter.cc
/gem5/src/mem/ruby/filters/GenericBloomFilter.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/libruby.hh
/gem5/src/mem/ruby/libruby_internal.hh
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.cc
/gem5/src/mem/ruby/network/simple/CustomTopology.hh
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.cc
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.cc
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.cc
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/hfa.hh
/gem5/src/mem/ruby/storebuffer/hfatypes.hh
/gem5/src/mem/ruby/storebuffer/interface.cc
/gem5/src/mem/ruby/storebuffer/interface.hh
/gem5/src/mem/ruby/storebuffer/stb_interface.cc
/gem5/src/mem/ruby/storebuffer/stb_interface.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/storebuffer/storebuffer.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryVector.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/ProcessorInterface.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Driver_Tester.cc
/gem5/src/mem/ruby/tester/Driver_Tester.hh
/gem5/src/mem/ruby/tester/EventQueue_Tester.hh
/gem5/src/mem/ruby/tester/Global_Tester.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.cc
/gem5/src/mem/slicc/ast/NewExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6284:a63d1dc4c820 06-Jul-2009 Nathan Binkert <nate@binkert.org>

ruby: replace strings that were missed in original ruby import.


/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
Global.hh
NetDest.cc
NetDest.hh
Set.cc
Set.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.hh
6239:0c808c6d4481 10-Jun-2009 Nathan Binkert <nate@binkert.org>

copyright: I missed some copyrights during ruby integration

6216:2f4020838149 17-May-2009 Nathan Binkert <nate@binkert.org>

includes: sort includes again


/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/predecoder.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/predecoder.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/x86/bios/acpi.hh
/gem5/src/arch/x86/bios/e820.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/intmessage.hh
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/pagetable.hh
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/utility.hh
/gem5/src/arch/x86/x86_traits.hh
/gem5/src/base/cp_annotate.hh
/gem5/src/base/crc.cc
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/intmath.hh
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/res_list.hh
/gem5/src/base/statistics.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inorder/comm.hh
/gem5/src/cpu/inorder/inorder_trace.hh
/gem5/src/cpu/inteltrace.hh
/gem5/src/cpu/legiontrace.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/alpha/backdoor.hh
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/intel_8254_timer.hh
/gem5/src/dev/mips/backdoor.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/x86/intdev.hh
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic_repl/gen.cc
/gem5/src/mem/cache/tags/iic_repl/repl.hh
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
Debug.hh
Global.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/rubymem.cc
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/python/swig/pyobject.hh
/gem5/src/python/swig/sim_object.i
/gem5/src/sim/arguments.hh
/gem5/src/sim/eventq.hh
/gem5/src/sim/init.cc
/gem5/src/sim/insttracer.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/rangemaptest.cc
/gem5/src/unittest/rangemultimaptest.cc
/gem5/util/statetrace/arch/tracechild_amd64.hh
/gem5/util/statetrace/arch/tracechild_i386.hh
/gem5/util/statetrace/arch/tracechild_sparc.hh
6204:b247610d8882 13-May-2009 Nathan Binkert <nate@binkert.org>

ruby: remove random uint typedef and use unsigned

6168:ba6fe02228db 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false

6165:2d26c346f1be 11-May-2009 Daniel Sanchez <sanchezd@stanford.edu>

ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t

6164:29b7b7aba911 11-May-2009 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Check stderr and not stdin before hanging on an assert.

6163:92318648212f 11-May-2009 Polina Dudnik <pdudnik@gmail.com>

ruby: decommission code

1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory

6157:eaf2fd8f54c0 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.

6154:6bb54dcb940e 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Address.cc
Address.hh
BigSet.cc
BigSet.hh
Consumer.hh
DataBlock.cc
DataBlock.hh
Debug.cc
Driver.cc
Driver.hh
Global.cc
Global.hh
Histogram.cc
Histogram.hh
Message.cc
NetDest.cc
NetDest.hh
OptBigSet.cc
OptBigSet.hh
Set.cc
Set.hh
SubBlock.cc
SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.hh
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueueNode.hh
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh
6150:a2ebddfe1a37 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: fold the debugging options into Debug.cc

6149:ff34514cbf37 11-May-2009 Derek Hower <drh5@cs.wisc.edu>

ruby: Renamed Ruby's EventQueue to RubyEventQueue

6148:71a683318799 11-May-2009 Daniel Sanchez <sanchezd@stanford.edu>

ruby: Removed System name clash by renaming ruby's System to RubySystem

6145:15cca6ab723a 11-May-2009 Nathan Binkert <nate@binkert.org>

ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.


/gem5/src/mem/gems_common/Allocator.hh
/gem5/src/mem/gems_common/Map.hh
/gem5/src/mem/gems_common/PrioHeap.hh
/gem5/src/mem/gems_common/RefCnt.hh
/gem5/src/mem/gems_common/RefCnt_tester.cc
/gem5/src/mem/gems_common/RefCountable.hh
/gem5/src/mem/gems_common/Vector.hh
/gem5/src/mem/gems_common/calc_host.sh
/gem5/src/mem/gems_common/ioutil/attrlex.ll
/gem5/src/mem/gems_common/ioutil/attrparse.yy
/gem5/src/mem/gems_common/ioutil/confio.cc
/gem5/src/mem/gems_common/ioutil/confio.hh
/gem5/src/mem/gems_common/ioutil/embedtext.py
/gem5/src/mem/gems_common/ioutil/initvar.cc
/gem5/src/mem/gems_common/ioutil/initvar.hh
/gem5/src/mem/gems_common/ioutil/vardecl.hh
/gem5/src/mem/gems_common/std-includes.hh
/gem5/src/mem/gems_common/util.cc
/gem5/src/mem/gems_common/util.hh
/gem5/src/mem/protocol/LogTM.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory.slicc
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m-mem.sm
/gem5/src/mem/protocol/MESI_CMP_filter_directory_m.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-L2cache.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory-msg.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory.slicc
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m-mem.sm
/gem5/src/mem/protocol/MESI_SCMP_bankdirectory_m.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-perfectDir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory_m-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory_m.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_SMP_directory-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_directory.slicc
/gem5/src/mem/protocol/MOESI_SMP_token-cache.sm
/gem5/src/mem/protocol/MOESI_SMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_SMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_SMP_token.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_1level.slicc
/gem5/src/mem/protocol/MOSI_SMP_bcast_m-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_bcast_m.slicc
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-cache.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-dir.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level-msg.sm
/gem5/src/mem/protocol/MOSI_SMP_directory_1level.slicc
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MSI_MOSI_CMP_directory.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Profiler.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/doc/MSI_MOSI_CMP_directory_2level-protocol-description.txt
/gem5/src/mem/protocol/doc/MSI_dir_L1_MOSI_dir_L2_SNUCA_CMP-protocol-description.txt
/gem5/src/mem/protocol/standard_1level_SMP-protocol.sm
/gem5/src/mem/protocol/standard_CMP-protocol.sm
/gem5/src/mem/protocol/standard_SMP-protocol.sm
/gem5/src/mem/ruby/Decomissioning_note
/gem5/src/mem/ruby/FakeSimicsDataTypes.hh
/gem5/src/mem/ruby/README.debugging
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.cc
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
Address.cc
Address.hh
BigSet.cc
BigSet.hh
Consumer.hh
DataBlock.cc
DataBlock.hh
Debug.cc
Debug.def
Debug.hh
Driver.cc
Driver.hh
Global.cc
Global.hh
Histogram.cc
Histogram.hh
Message.cc
NetDest.cc
NetDest.hh
OptBigSet.cc
OptBigSet.hh
Set.cc
Set.hh
SubBlock.cc
SubBlock.hh
/gem5/src/mem/ruby/config/RubyConfig.cc
/gem5/src/mem/ruby/config/RubyConfig.hh
/gem5/src/mem/ruby/config/config.include
/gem5/src/mem/ruby/config/rubyconfig.defaults
/gem5/src/mem/ruby/config/tester.defaults
/gem5/src/mem/ruby/eventqueue/EventQueue.cc
/gem5/src/mem/ruby/eventqueue/EventQueue.hh
/gem5/src/mem/ruby/eventqueue/EventQueueNode.cc
/gem5/src/mem/ruby/eventqueue/EventQueueNode.hh
/gem5/src/mem/ruby/eventqueue/EventQueue_tester.cc
/gem5/src/mem/ruby/init.cc
/gem5/src/mem/ruby/init.hh
/gem5/src/mem/ruby/interfaces/OpalInterface.cc
/gem5/src/mem/ruby/interfaces/OpalInterface.hh
/gem5/src/mem/ruby/interfaces/mf_api.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/orion/NetworkPower.hh
/gem5/src/mem/ruby/network/orion/SIM_port.hh
/gem5/src/mem/ruby/network/orion/SIM_power.hh
/gem5/src/mem/ruby/network/orion/SIM_power_test.hh
/gem5/src/mem/ruby/network/orion/parm_technology.hh
/gem5/src/mem/ruby/network/orion/power_arbiter.cc
/gem5/src/mem/ruby/network/orion/power_arbiter.hh
/gem5/src/mem/ruby/network/orion/power_array.cc
/gem5/src/mem/ruby/network/orion/power_array.hh
/gem5/src/mem/ruby/network/orion/power_bus.cc
/gem5/src/mem/ruby/network/orion/power_bus.hh
/gem5/src/mem/ruby/network/orion/power_crossbar.cc
/gem5/src/mem/ruby/network/orion/power_crossbar.hh
/gem5/src/mem/ruby/network/orion/power_ll.cc
/gem5/src/mem/ruby/network/orion/power_ll.hh
/gem5/src/mem/ruby/network/orion/power_router_init.cc
/gem5/src/mem/ruby/network/orion/power_router_init.hh
/gem5/src/mem/ruby/network/orion/power_static.cc
/gem5/src/mem/ruby/network/orion/power_static.hh
/gem5/src/mem/ruby/network/orion/power_utils.cc
/gem5/src/mem/ruby/network/orion/power_utils.hh
/gem5/src/mem/ruby/network/simple/Network_Files/GarnetFileMaker.py
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-32_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-1_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-256_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-32_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-1_ProcsPerChip-1_L2Banks-64_Memories-1.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-1_L2Banks-2_Memories-2.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-2_ProcsPerChip-2_L2Banks-2_Memories-2.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-32_ProcsPerChip-32_L2Banks-32_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-1_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-4_ProcsPerChip-4_L2Banks-4_Memories-4.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-7_ProcsPerChip-7_L2Banks-7_Memories-7.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-1_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-4_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-8_ProcsPerChip-8_L2Banks-8_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/NetworkFileMaker.py
/gem5/src/mem/ruby/network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt
/gem5/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/CacheProfiler.cc
/gem5/src/mem/ruby/profiler/CacheProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/profiler/XactProfiler.cc
/gem5/src/mem/ruby/profiler/XactProfiler.hh
/gem5/src/mem/ruby/recorder/CacheRecorder.cc
/gem5/src/mem/ruby/recorder/CacheRecorder.hh
/gem5/src/mem/ruby/recorder/TraceRecord.cc
/gem5/src/mem/ruby/recorder/TraceRecord.hh
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/simics/commands.cc
/gem5/src/mem/ruby/simics/commands.hh
/gem5/src/mem/ruby/simics/interface.cc
/gem5/src/mem/ruby/simics/interface.hh
/gem5/src/mem/ruby/simics/simics_api_dummy.c
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractChip.cc
/gem5/src/mem/ruby/slicc_interface/AbstractChip.hh
/gem5/src/mem/ruby/slicc_interface/AbstractProtocol.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_includes.hh
/gem5/src/mem/ruby/system/AbstractBloomFilter.hh
/gem5/src/mem/ruby/system/AbstractMemOrCache.hh
/gem5/src/mem/ruby/system/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/system/BlockBloomFilter.cc
/gem5/src/mem/ruby/system/BlockBloomFilter.hh
/gem5/src/mem/ruby/system/BulkBloomFilter.cc
/gem5/src/mem/ruby/system/BulkBloomFilter.hh
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/GenericBloomFilter.cc
/gem5/src/mem/ruby/system/GenericBloomFilter.hh
/gem5/src/mem/ruby/system/H3BloomFilter.cc
/gem5/src/mem/ruby/system/H3BloomFilter.hh
/gem5/src/mem/ruby/system/LRUPolicy.hh
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/system/LSB_CountingBloomFilter.hh
/gem5/src/mem/ruby/system/MachineID.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryNode.cc
/gem5/src/mem/ruby/system/MemoryNode.hh
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/system/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/system/MultiGrainBloomFilter.hh
/gem5/src/mem/ruby/system/NodeID.hh
/gem5/src/mem/ruby/system/NodePersistentTable.cc
/gem5/src/mem/ruby/system/NodePersistentTable.hh
/gem5/src/mem/ruby/system/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/system/NonCountingBloomFilter.hh
/gem5/src/mem/ruby/system/PerfectCacheMemory.hh
/gem5/src/mem/ruby/system/PersistentArbiter.cc
/gem5/src/mem/ruby/system/PersistentArbiter.hh
/gem5/src/mem/ruby/system/PersistentTable.cc
/gem5/src/mem/ruby/system/PersistentTable.hh
/gem5/src/mem/ruby/system/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/StoreBuffer.cc
/gem5/src/mem/ruby/system/StoreBuffer.hh
/gem5/src/mem/ruby/system/StoreCache.cc
/gem5/src/mem/ruby/system/StoreCache.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/ruby/system/TBETable.hh
/gem5/src/mem/ruby/system/TimerTable.cc
/gem5/src/mem/ruby/system/TimerTable.hh
/gem5/src/mem/ruby/tester/BarrierGenerator.cc
/gem5/src/mem/ruby/tester/BarrierGenerator.hh
/gem5/src/mem/ruby/tester/Check.cc
/gem5/src/mem/ruby/tester/Check.hh
/gem5/src/mem/ruby/tester/CheckTable.cc
/gem5/src/mem/ruby/tester/CheckTable.hh
/gem5/src/mem/ruby/tester/DetermGETXGenerator.cc
/gem5/src/mem/ruby/tester/DetermGETXGenerator.hh
/gem5/src/mem/ruby/tester/DetermInvGenerator.cc
/gem5/src/mem/ruby/tester/DetermInvGenerator.hh
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.cc
/gem5/src/mem/ruby/tester/DetermSeriesGETSGenerator.hh
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.hh
/gem5/src/mem/ruby/tester/Instruction.cc
/gem5/src/mem/ruby/tester/Instruction.hh
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.hh
/gem5/src/mem/ruby/tester/RequestGenerator.cc
/gem5/src/mem/ruby/tester/RequestGenerator.hh
/gem5/src/mem/ruby/tester/SpecifiedGenerator.cc
/gem5/src/mem/ruby/tester/SpecifiedGenerator.hh
/gem5/src/mem/ruby/tester/SyntheticDriver.cc
/gem5/src/mem/ruby/tester/SyntheticDriver.hh
/gem5/src/mem/ruby/tester/Tester.cc
/gem5/src/mem/ruby/tester/Tester.hh
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactAbortRequestGenerator.hh
/gem5/src/mem/ruby/tester/XactRequestGenerator.cc
/gem5/src/mem/ruby/tester/XactRequestGenerator.hh
/gem5/src/mem/ruby/tester/main.cc
/gem5/src/mem/ruby/tester/main.hh
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/ruby/tester/test_framework.hh
/gem5/src/mem/slicc/README
/gem5/src/mem/slicc/ast/AST.cc
/gem5/src/mem/slicc/ast/AST.hh
/gem5/src/mem/slicc/ast/ASTs.hh
/gem5/src/mem/slicc/ast/ActionDeclAST.cc
/gem5/src/mem/slicc/ast/ActionDeclAST.hh
/gem5/src/mem/slicc/ast/AssignStatementAST.cc
/gem5/src/mem/slicc/ast/AssignStatementAST.hh
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.cc
/gem5/src/mem/slicc/ast/CheckAllocateStatementAST.hh
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.cc
/gem5/src/mem/slicc/ast/CheckStopSlotsStatementAST.hh
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.cc
/gem5/src/mem/slicc/ast/ChipComponentAccessAST.hh
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.cc
/gem5/src/mem/slicc/ast/CopyHeadStatementAST.hh
/gem5/src/mem/slicc/ast/DeclAST.cc
/gem5/src/mem/slicc/ast/DeclAST.hh
/gem5/src/mem/slicc/ast/DeclListAST.cc
/gem5/src/mem/slicc/ast/DeclListAST.hh
/gem5/src/mem/slicc/ast/EnqueueStatementAST.cc
/gem5/src/mem/slicc/ast/EnqueueStatementAST.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.cc
/gem5/src/mem/slicc/ast/EnumDeclAST.hh
/gem5/src/mem/slicc/ast/EnumExprAST.cc
/gem5/src/mem/slicc/ast/EnumExprAST.hh
/gem5/src/mem/slicc/ast/ExprAST.cc
/gem5/src/mem/slicc/ast/ExprAST.hh
/gem5/src/mem/slicc/ast/ExprStatementAST.cc
/gem5/src/mem/slicc/ast/ExprStatementAST.hh
/gem5/src/mem/slicc/ast/FormalParamAST.cc
/gem5/src/mem/slicc/ast/FormalParamAST.hh
/gem5/src/mem/slicc/ast/FuncCallExprAST.cc
/gem5/src/mem/slicc/ast/FuncCallExprAST.hh
/gem5/src/mem/slicc/ast/FuncDeclAST.cc
/gem5/src/mem/slicc/ast/FuncDeclAST.hh
/gem5/src/mem/slicc/ast/IfStatementAST.cc
/gem5/src/mem/slicc/ast/IfStatementAST.hh
/gem5/src/mem/slicc/ast/InPortDeclAST.cc
/gem5/src/mem/slicc/ast/InPortDeclAST.hh
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.cc
/gem5/src/mem/slicc/ast/InfixOperatorExprAST.hh
/gem5/src/mem/slicc/ast/LiteralExprAST.cc
/gem5/src/mem/slicc/ast/LiteralExprAST.hh
/gem5/src/mem/slicc/ast/Location.cc
/gem5/src/mem/slicc/ast/Location.hh
/gem5/src/mem/slicc/ast/MachineAST.cc
/gem5/src/mem/slicc/ast/MachineAST.hh
/gem5/src/mem/slicc/ast/MemberExprAST.cc
/gem5/src/mem/slicc/ast/MemberExprAST.hh
/gem5/src/mem/slicc/ast/MethodCallExprAST.cc
/gem5/src/mem/slicc/ast/MethodCallExprAST.hh
/gem5/src/mem/slicc/ast/ObjDeclAST.cc
/gem5/src/mem/slicc/ast/ObjDeclAST.hh
/gem5/src/mem/slicc/ast/OutPortDeclAST.cc
/gem5/src/mem/slicc/ast/OutPortDeclAST.hh
/gem5/src/mem/slicc/ast/PairAST.cc
/gem5/src/mem/slicc/ast/PairAST.hh
/gem5/src/mem/slicc/ast/PairListAST.cc
/gem5/src/mem/slicc/ast/PairListAST.hh
/gem5/src/mem/slicc/ast/PeekStatementAST.cc
/gem5/src/mem/slicc/ast/PeekStatementAST.hh
/gem5/src/mem/slicc/ast/ReturnStatementAST.cc
/gem5/src/mem/slicc/ast/ReturnStatementAST.hh
/gem5/src/mem/slicc/ast/StatementAST.cc
/gem5/src/mem/slicc/ast/StatementAST.hh
/gem5/src/mem/slicc/ast/StatementListAST.cc
/gem5/src/mem/slicc/ast/StatementListAST.hh
/gem5/src/mem/slicc/ast/TransitionDeclAST.cc
/gem5/src/mem/slicc/ast/TransitionDeclAST.hh
/gem5/src/mem/slicc/ast/TypeAST.cc
/gem5/src/mem/slicc/ast/TypeAST.hh
/gem5/src/mem/slicc/ast/TypeDeclAST.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.hh
/gem5/src/mem/slicc/ast/TypeFieldAST.cc
/gem5/src/mem/slicc/ast/TypeFieldAST.hh
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.cc
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMemberAST.hh
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.cc
/gem5/src/mem/slicc/ast/TypeFieldMethodAST.hh
/gem5/src/mem/slicc/ast/VarExprAST.cc
/gem5/src/mem/slicc/ast/VarExprAST.hh
/gem5/src/mem/slicc/doc/SLICC_V03.txt
/gem5/src/mem/slicc/doc/tutorial.tex
/gem5/src/mem/slicc/generator/fileio.cc
/gem5/src/mem/slicc/generator/fileio.hh
/gem5/src/mem/slicc/generator/html_gen.cc
/gem5/src/mem/slicc/generator/html_gen.hh
/gem5/src/mem/slicc/generator/mif_gen.cc
/gem5/src/mem/slicc/generator/mif_gen.hh
/gem5/src/mem/slicc/main.cc
/gem5/src/mem/slicc/main.hh
/gem5/src/mem/slicc/parser/lexer.ll
/gem5/src/mem/slicc/parser/parser.yy
/gem5/src/mem/slicc/slicc_global.hh
/gem5/src/mem/slicc/symbols/Action.hh
/gem5/src/mem/slicc/symbols/Event.hh
/gem5/src/mem/slicc/symbols/Func.cc
/gem5/src/mem/slicc/symbols/Func.hh
/gem5/src/mem/slicc/symbols/State.hh
/gem5/src/mem/slicc/symbols/StateMachine.cc
/gem5/src/mem/slicc/symbols/StateMachine.hh
/gem5/src/mem/slicc/symbols/Symbol.cc
/gem5/src/mem/slicc/symbols/Symbol.hh
/gem5/src/mem/slicc/symbols/SymbolTable.cc
/gem5/src/mem/slicc/symbols/SymbolTable.hh
/gem5/src/mem/slicc/symbols/Transition.cc
/gem5/src/mem/slicc/symbols/Transition.hh
/gem5/src/mem/slicc/symbols/Type.cc
/gem5/src/mem/slicc/symbols/Type.hh
/gem5/src/mem/slicc/symbols/Var.cc
/gem5/src/mem/slicc/symbols/Var.hh