History log of /gem5/src/learning_gem5/part3/
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14184:11ac1337c5e2 16-Aug-2019 Gabe Black <gabeblack@google.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>


/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/rubytest/Check.hh
MSI-cache.sm
SConsopts
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/protocol/Garnet_standalone.slicc
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/protocol/MESI_Three_Level.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MI_example.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/MOESI_hammer.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/RubySlicc_Util.sm
/gem5/src/mem/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/protocol/SConscript
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/MachineID.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/ruby/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_RfO.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/ruby/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/ruby/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-dir.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone-msg.sm
/gem5/src/mem/ruby/protocol/Garnet_standalone.slicc
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Three_Level.slicc
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/ruby/protocol/MESI_Two_Level.slicc
/gem5/src/mem/ruby/protocol/MI_example-cache.sm
/gem5/src/mem/ruby/protocol/MI_example-dir.sm
/gem5/src/mem/ruby/protocol/MI_example-dma.sm
/gem5/src/mem/ruby/protocol/MI_example-msg.sm
/gem5/src/mem/ruby/protocol/MI_example.slicc
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_directory.slicc
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_CMP_token.slicc
/gem5/src/mem/ruby/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/ruby/protocol/MOESI_hammer.slicc
/gem5/src/mem/ruby/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Defines.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/protocol/RubySlicc_Util.sm
/gem5/src/mem/ruby/protocol/RubySlicc_interfaces.slicc
/gem5/src/mem/ruby/protocol/SConscript
/gem5/src/mem/ruby/protocol/SConsopts
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/AbstractEntry.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/PerfectCacheMemory.hh
/gem5/src/mem/ruby/structures/PersistentTable.hh
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/slicc/main.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
12608:27b20e3ea77b 09-Mar-2018 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add a simple Ruby protocol

Adds the MSI protocol from "A Primer on Memory Consistency and Cache
Coherence" by Daniel J. Sorin, Mark D. Hill, and David A. Wood.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

This is meant to be a simple, clean, example of how to make a Ruby
protocol.
Currently, it only works in SE mode.

The next changeset will contain the required configuration files.

Change-Id: If2cc53f5e6b9c6891749f929d872671615a2b4ab
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8942