History log of /gem5/src/dev/storage/
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13981:577196ddd040 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13665:9c7fe3811b88 25-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>


/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmNativeTrace.py
/gem5/src/arch/arm/ArmPMU.py
/gem5/src/arch/arm/ArmSemihosting.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/tracers/TarmacTrace.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/power/PowerTLB.py
/gem5/src/arch/riscv/RiscvSystem.py
/gem5/src/arch/riscv/RiscvTLB.py
/gem5/src/arch/sparc/SparcNativeTrace.py
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86NativeTrace.py
/gem5/src/arch/x86/X86System.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/base/vnc/Vnc.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CPUTracers.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/DummyChecker.py
/gem5/src/cpu/InstPBTrace.py
/gem5/src/cpu/kvm/BaseKvmCPU.py
/gem5/src/cpu/kvm/X86KvmCPU.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/probe/ElasticTrace.py
/gem5/src/cpu/o3/probe/SimpleTrace.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/BaseSimpleCPU.py
/gem5/src/cpu/simple/NonCachingSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/cpu/simple/probes/SimPoint.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/traffic_gen/BaseTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/PyTrafficGen.py
/gem5/src/cpu/testers/traffic_gen/TrafficGen.py
/gem5/src/cpu/trace/TraceCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/Platform.py
/gem5/src/dev/alpha/AlphaBackdoor.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/EnergyCtrl.py
/gem5/src/dev/arm/FlashDevice.py
/gem5/src/dev/arm/Gic.py
/gem5/src/dev/arm/NoMali.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/UFSHostDevice.py
/gem5/src/dev/arm/VirtIOMMIO.py
/gem5/src/dev/i2c/I2C.py
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/net/Ethernet.py
/gem5/src/dev/pci/CopyEngine.py
/gem5/src/dev/pci/PciDevice.py
/gem5/src/dev/pci/PciHost.py
/gem5/src/dev/serial/Terminal.py
/gem5/src/dev/serial/Uart.py
/gem5/src/dev/sparc/T1000.py
Ide.py
/gem5/src/dev/virtio/VirtIO.py
/gem5/src/dev/virtio/VirtIO9P.py
/gem5/src/dev/virtio/VirtIOBlock.py
/gem5/src/dev/virtio/VirtIOConsole.py
/gem5/src/dev/x86/Cmos.py
/gem5/src/dev/x86/I8042.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/I8237.py
/gem5/src/dev/x86/I8254.py
/gem5/src/dev/x86/I8259.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/PcSpeaker.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/learning_gem5/part2/SimpleCache.py
/gem5/src/learning_gem5/part2/SimpleMemobj.py
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/AddrMapper.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/CommMonitor.py
/gem5/src/mem/DRAMCtrl.py
/gem5/src/mem/ExternalMaster.py
/gem5/src/mem/ExternalSlave.py
/gem5/src/mem/HMCController.py
/gem5/src/mem/MemChecker.py
/gem5/src/mem/MemDelay.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/SerialLink.py
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/XBar.py
/gem5/src/mem/cache/Cache.py
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/tags/Tags.py
/gem5/src/mem/probes/MemFootprintProbe.py
/gem5/src/mem/probes/MemTraceProbe.py
/gem5/src/mem/probes/StackDistProbe.py
/gem5/src/mem/qos/QoSMemCtrl.py
/gem5/src/mem/qos/QoSMemSinkCtrl.py
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/simple/SimpleLink.py
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/LRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/structures/RubyPrefetcher.py
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/sim/System.py
/gem5/src/sim/TickedObject.py
/gem5/src/sim/power/MathExprPowerModel.py
/gem5/src/sim/power/ThermalModel.py
13342:1ddb43f47325 12-Oct-2018 Gabe Black <gabeblack@google.com>

dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12895:16e3712d8189 02-Aug-2018 Jason Lowe-Power <jason@lowepower.com>

misc: Appease GCC 8

GCC 8 adds a number of new warnings to -Wall which generate errors.

- Fix memset to 0 for structs by adding casts.
- Fix cast with const when the const was ignored.
- Fix catch a polymorphic type by value

We now compile with GCC 8!

Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

12392:e0dbdf30a2a5 13-Dec-2017 Jason Lowe-Power <jason@lowepower.com>

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>

12334:e0ab29a34764 30-Nov-2017 Gabe Black <gabeblack@google.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>


/gem5/ext/sst/gem5.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/locked_mem.hh
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/pseudo_inst.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/isa_device.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/pseudo_inst.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/generic/tlb.hh
/gem5/src/arch/generic/vec_reg.hh
/gem5/src/arch/hsail/gpu_isa.hh
/gem5/src/arch/mips/decoder.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/pseudo_inst.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/power/interrupts.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/pseudo_inst.hh
/gem5/src/arch/power/utility.cc
/gem5/src/arch/riscv/decoder.hh
/gem5/src/arch/riscv/interrupts.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/locked_mem.hh
/gem5/src/arch/riscv/pagetable.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/pseudo_inst.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/mt.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/pseudo_inst.hh
/gem5/src/arch/sparc/tlb.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/decoder.hh
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/regs/int.hh
/gem5/src/base/SConscript
/gem5/src/base/addr_range.hh
/gem5/src/base/bigint.hh
/gem5/src/base/bmpwriter.cc
/gem5/src/base/circlebuf.hh
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/imgwriter.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/logging.cc
/gem5/src/base/logging.hh
/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/output.cc
/gem5/src/base/pngwriter.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/trie.hh
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/kvm/device.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/btb.hh
/gem5/src/cpu/pred/ltage.cc
/gem5/src/cpu/pred/sat_counter.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/mc146818.hh
/gem5/src/dev/net/dist_iface.hh
/gem5/src/dev/net/etherbus.cc
/gem5/src/dev/net/etherdump.cc
/gem5/src/dev/net/etherint.cc
/gem5/src/dev/net/etherpkt.cc
/gem5/src/dev/net/ethertap.cc
/gem5/src/dev/net/pktfifo.cc
/gem5/src/dev/net/pktfifo.hh
/gem5/src/dev/pci/device.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/serial/serial.cc
/gem5/src/dev/serial/terminal.cc
disk_image.cc
simple_disk.cc
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/write_queue_entry.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/mem_checker.hh
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/mem/ruby/common/Set.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/pybind11/core.cc
/gem5/src/python/pybind11/event.cc
/gem5/src/sim/clocked_object.cc
/gem5/src/sim/drain.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/eventq.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/fd_array.cc
/gem5/src/sim/init.cc
/gem5/src/sim/init_signals.cc
/gem5/src/sim/mathexpr.cc
/gem5/src/sim/microcode_rom.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/stattest.cc
/gem5/util/systemc/sc_module.cc
12201:cef59b44d586 25-Sep-2017 Gabe Black <gabeblack@google.com>

dev: Make the IDE controller handle NULL simobject pointers.

Only panic if there are disks which would actually be connected to it beyond
its limit. Also skip past disks which are set to NULL. This is useful since
it lets you set up disks on different ports of the controller instead of
filling them contiguously.

Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7
Reviewed-on: https://gem5-review.googlesource.com/4848
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12168:39ed94e507ed 07-Aug-2017 Gabe Black <gabeblack@google.com>

dev: Fix an IDE error check.

The error message says an IDE controller can support at most 4 disks, but the
check would fail if there were more than 3 disks.

Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9
Reviewed-on: https://gem5-review.googlesource.com/4460
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12087:0e082672ac6b 07-Jun-2017 Sean Wilson <spwilson2@wisc.edu>

dev: Replace EventWrapper use with EventFunctionWrapper

Change-Id: I6b03cc6f67e76dffb79940431711ae6171901c6a
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

11980:56d16946ed95 24-Apr-2017 Jason Lowe-Power <jason@lowepower.com>

dev: Add ATA command used in recent Linux kernels

Add a case for the ATA command ATAPI_IDENTIFY_DEVICE.
This avoids the panic: Unsupported ATA command when booting a recent Linux
kernel. This was tested on 4.8.13.

Change-Id: Ib297a2c02da0730d8698c59801254dd0f5ee9f7f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/2863
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

11613:7e7157941d70 16-Aug-2016 Andreas Sandberg <andreas.sandberg@arm.com>

dev: Revert 0a316996de76 [dev, sim: Added missing override...]

This changeset reverts the changset "dev, sim: Added missing override
keywords to fix CLANG compilation (OSX)" which was incorrectly rebased.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

11609:0a316996de76 14-Aug-2016 Matteo Andreozzi <Matteo.Andreozzi@arm.com>

dev, sim: Added missing override keywords to fix CLANG compilation (OSX)

Change-Id: Ice5fa11e77d06576eaa42149f5fa340a769d8b01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11522:348411ec525a 06-Jun-2016 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

sim: Call regStats of base-class as well

We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well. For now, these are
empty, but generic stats will be added there.

Patch originally provided by Akash Bagdia at ARM Ltd.

11442:b31738224fb0 12-Apr-2016 Andreas Hansson <andreas.hansson@arm.com>

misc: Appease clang...again

Once again, clang is having issues with recently committed code.

Unfortunately HSAIL_X86 is still broken.

11361:17e33647b5d1 26-Nov-2015 Andreas Sandberg <andreas@sandberg.pp.se>

dev: Add post-fork handling for disk images

This changeset adds support for notifying the disk images that the simulator has
been forked. We need to disable the saving of the CoW disk image from the child
process, and we need to make sure that systems which use a raw disk image are
not allowed to fork to avoid two or more gem5 processes writing to the same disk
image.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

11264:dc389d2d2f79 10-Dec-2015 Andreas Sandberg <andreas.sandberg@arm.com>

dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.