cpu: Fix checker cpu instantiation

This change uses the params as instantiated from the default
constructor to create the checker cpu. If any of these parameters are
invalid for the checker cpu, the simulation will exit with a warning.

Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21079
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>

This change is based on modify the way we move the AtomicOpFunctor*
through gem5 in order to mantain proper ownership of the object and
ensuring its destruction when it is no longer used.

Doing that we fix at the same time a memory leak in Request.hh
where we were assigning a new AtomicOpFunctor* without destroying the
previous one.

This change creates a new type AtomicOpFunctor_ptr as a
std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except
for its only usage when AtomicOpFunc() is called.

Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: reset byte_enable across writeMem calls

data_write_req byteEnable which is used in ARM SVE partial writes was not
being zeroed between writes.

As a result, non-SVE memory write instructions such as STP that followed
SVE memory write instructions could still have the write mask active.

This could lead to wrong simulation behaviour, and to an assertion failure:

src/mem/packet.hh:1211: void Packet::writeData(uint8_t*) const: Assertion
`req->getByteEnable().size() == getSize()' failed. '`

Change-Id: I74b5a82675e9923b0ffdf2c1dd9afb00c91cb204
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20448
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Convert traffic gen to use new stats

Change-Id: Ife690a137c2dcfb6bcc8b22df996c84f0d231618
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19370
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.

No caller uses any of the MasterPort specific properties of these
function's return values, so we can instead return a reference to the
base Port class. This makes it possible for the data and inst ports
to be of any port type, not just gem5 style MasterPorts. This makes
life simpler for, for example, systemc based CPUs which might have TLM
ports.

It also makes it possible for any two CPUs which have compatible ports
to be switched between, as long as the ports they use support being
unbound. Unfortunately that does not include TLM or systemc ports which
are bound permanently.

Change-Id: I98fce5a16d2ef1af051238e929dd96d57a4ac838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20240
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu, mem: Add new getSendFunctional method to the base CPU.

This returns a sendFunctional delegate references which can be used
to send functional accesses directly, or more likely when constructing
a PortProxy subclass. In those cases only the functional capabilities
of those ports are needed so there's no reason to require a full port
which supports all three protocols. Also, this removes the last
remaining use of get(Data|Inst)Port which relies on those returning
a port which supports the gem5 protocols, except the default
implementations of this new function. If a CPU doesn't have
traditional gem5 style ports, it can override this function to
do whatever other behavior is necessary and return its real ports
through get(Data|Inst)Port.

Change-Id: Ide4da81e3bc679662cd85902ba6bd537cce54a53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20237
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Move the instruction port into o3's fetch stage.

That's where it's used, and that avoids having to pass it around using
the top level getInstPort accessor.

Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Move O3's data port into the LSQ.

That's where it's used, and putting it there avoids having to pass
around the port using the top level getDataPort function.

Change-Id: I0dea25d0c5f4bb3f58a6574a8f2b2d242784caf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu, dev, mem: Use the new Port methods.

Use getPeer, takeOverFrom, and << to simplify the use of ports in some
areas.

Change-Id: Idfbda27411b5d6b742f5e4927894302ea6d6a53d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20235
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Move ruby protocols into a directory called ruby_protocol.

Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

In src/cpu/reg_class.hh, numPinnedWrites was unset because the
constructors were not well factored out.

Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Pull more arch specialization to the top of BaseCPU.py.

This simplifies the logic of the CPU python class, and brings us ever
so slightly closer to factoring hardcoded ISA behavior out of non-ISA
specific components.

Change-Id: I7e4511dd4e6076f5c214be5af2a0e33af0142563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19889
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Move some fixed or dummy config information into X86LocalApic.py.

The X86 local APIC doesn't actually use the pio_addr set in the config
and instead computes what address it will respond to based on the
initial ID of the CPU it's attached to. gem5's BasicPioDevice, which
the X86LocalApic class inherits from, does not provide a default value
for that parameter and will complain if *something* isn't set. The
value used, 0x2000000000000000, is a dummy value which is the base of
the region of the physical address space set aside for messages to
local APICs from the CPU and from other local APICs.

Also, the clock for the local APIC's timer is defined to be the bus
clock. The assumption seems to be that this has a 16:1 ratio with the
CPU clock, and I vaguely remember finding that that was more or less
unofficially true, even if it isn't necessary stringently defined to
be that.

Since we were already just assuming that that ratio was correct and
always setting up the local APICs clock that way, we can do that in
the X86LocalApic class definition and remove some special x86 specific
setup that we'd otherwise need for the x86 version of the Interrupt
class. If that's not correct, it can still be overridden somewhere else
in the config.

Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: fix atomic instructions non-speculative

Fix problem with O3 and AMO instructions. At initial stages amo
instruction is considered a type of non-speculative store. After
the instruction has been commited and during the squash step,
acquire_release version of the AMO operation is considered speculative,
that differents results in an assert fault. This fix ensures that AMO
instructions are always considered non-speculative, during early stages
and during squas/removal of the instruction.

Change-Id: Ia0c5fbb9dc44a9991337b57eb759b1ed08e4149e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19815
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: added _amo_op parameter in o3 LSQ

Fix bug with AMO (or RMW) instructions where the amo_op variable
is not being propagated to the LSQ request.

Change-Id: I60c59641d9b497051376f638e27f3c4cc361f615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: Fix the type of the effective mem request size

A memory request size can be larger than 255 bytes (e.g.
SVE with 2048-bit vector length) which could cause overflow
in the 'uint8_t effSize' variable.

Change-Id: I77e0d02a49ea7f81cacfa5be7e4ae40434af3109
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: Fix too strict assert condition in writeback()

The assert() in the LSQ writeback() only allowed ReExec faults.
However, a SplitRequest which completed the translation in
PartialFault state (i.e. any but the very first cacheline
translation failed) may end up here. The assert() condition is
extended accordingly.

The patch also removes the superfluous/unused Complete/Squashed
states from the LSQ request. (The completion of the request is
recorded in the flags still.)

Change-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Add first-/non-faulting load support to Minor and O3

Some architectures allow masking faults of memory load instructions in
some specific circumstances (e.g. first-faulting and non-faulting
loads in Arm SVE). This patch adds support for such loads in the Minor
and O3 CPU models.

Change-Id: I264a81a078f049127779aa834e89f0e693ba0bea
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: isDrained renamed to isCpuDrained

cpu models inheriting from BaseCPU implement a draining checker called
isDrained. This hides the base Drainable::isDrained method and might
create confusion in the reader.
This patch is renaming it to isCpuDrained in order to avoid any
ambiguity

Change-Id: Ie5221da6a4673432c2403996e42d451cae960bbf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Set packet data type for IPR read

This change assigns packet data type to static for IPR read.
Caused by change (e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169),
and has been reported a few times in the mailing list.

Change-Id: I0f02c20a16824e220df876e9e552bbc1c9636f95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19449
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>

cpu-o3: Reset fault status for mem access in pushRequest

Reset the fault status always before translation is initiated in
pushRequest() in the LSQ. This avoids the problem when a strictly
ordered load needs to be re-executed multiple times. If the
translation is delayed at one of those attempts then the
internal panicFault (from the previous execution attempt) can get
fired at commit.

Change-Id: I0c22b2f7afd6e2cb00bc359a4a01042efd2d01d2
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19388
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Additional TrafficGen stats

Additional stats to keep track of read/write latencies and throughput.

Change-Id: I7684cd33cf68fffdef4ca9c3a6db360a0f531c18
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18418
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Limit TrafficGen outstanding reqs

Parameter to limit the number of requests waiting for a response.

Change-Id: I6cf9e8782a06ae978fb66f7c4278f4c9e9980c79
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: TrafficGen as BaseCPU

TrafficGen has additional attributes to behave like a BaseCPU. Python
scripts that expect sim. objects derived from BaseCPU can now be used with
TrafficGen without additional modifications.

Change-Id: Iee848b2ba0ac1851c487b1003da9bd96253d291a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18416
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Iaa68ead7696e0b6ba05b4417d0322e8053e10d30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15495
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Increase LSQ buffer sizes to match max vector length

Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13525
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix rescheduling of progress check events

noRequestEvent needs to be rescheduled on recvRetry, otherwise the timeout
may be triggered even though packets are being eventually sent.
noResponseEvent scheduling is also fixed. This timeout should not be
active when we are not expecting a response.

Change-Id: If9edb75b5b803caf9f99bf41ea3948b15a3f3d71
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18793
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Add support for pinned writes

This patch adds support for pinning registers for a certain number of
consecutive writes. This is only relevant for timing CPU models
(functional-only models are unaffected), and it is primarily needed to
provide a realistic execution model for micro-coded operations whose
microops can write to non-overlapping portions of a destination
register, e.g. vector gather loads. In those cases, this mechanism
can disable renaming for a sequence of consecutive writes, thus making
the resulting execution more efficient: allocating a new physical
register for each microop would introduce a read-modify-write chain of
dependencies, while with these modifications the microops can write
back in parallel.

Please note that this new feature is only leveraged by O3CPU for the
time being.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>

Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13520
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Store the translating proxy with the same pointer in SE or FS mode.

Only one is active at a time, so they can share the same pointer.

Change-Id: Ie4ae1f0ffbf9448f6730f9c7d072bc85d6d423da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18580
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

cpu, sim: Return PortProxy &s from all the proxy accessors.

This is a step towards merging the accessors for SE and FS modes.

Change-Id: I76818ab88b97097ac363e243be9cc1911b283090
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18579
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Added correct return type for ROB::countInsts

- return size_t (unsigned) according to the .size() return type
- fixed typo in doc (source of warning with some compilers)

Change-Id: I48ee2e317cf41011a6fcb5ca45aef67e75329bfa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18948
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove assert causing issues with x86 Linux boot

Change-Id: I5e0b189ced0dd59ac6dbbb2c498c068e132b9b93
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18910
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.

This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.

Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "cpu: fix how a thread starts up in MinorCPU"

This reverts commit 02dafc5498750d9734ba8f2a1608a846f90b71d1.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I0a8098fc71abe5838014e587dbe372b258d8aa9f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18604
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "cpu: stop scheduling suspended threads in MinorCPU"

This reverts commit 6a6668bbc4b038b98eb3ee64ffb034719316afd9.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: I3c16a6478ba44b9d27cdd3d64a710a356999df05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18603
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "cpu: fix branching when thread is suspended in MinorCPU"

This reverts commit e437086341712f1435db655b3527ea29b3311f4e.
The commit was part of a patchset which broke MinorCPU regressions
(switcheroo)

Change-Id: Ib8482034c2402008ccfa552325a8eb31e731b619
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18602
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Move SatCounter to base directory

Saturating counters are used by many objects, not only
the cpu predictors. Therefore, move the class to the
base folder so that it can be more easily used.

Change-Id: I26f799324bdd8720ab8834c72a2002149cee777c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17993
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Revamp saturating counters

Revamp the SatCounter class, improving comments, implementing
increment, decrement and read operators to solve an old todo,
and adding missing error checking.

Change-Id: Ia057c423c90652ebd966b6b91a3471b17800f933
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17992
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Make the indirect predictor into a SimObject

Change-Id: Ice6549773def7d3e944fae450d4a079bc351e2ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15319
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,mem: Add support for partial loads/stores and wide mem. accesses

This changeset adds support for partial (or masked) loads/stores, i.e.
loads/stores that can disable accesses to individual bytes within the
target address range. In addition, this changeset extends the code to
crack memory accesses across most CPU models (TimingSimpleCPU still
TBD), so that arbitrarily wide memory accesses are supported. These
changes are required for supporting ISAs with wide vectors.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>
- Tiago Muck <tiago.muck@arm.com>

Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

cpu: Add a memory access predicate

This changeset introduces a new predicate to guard memory accesses.
The most immediate use for this is to allow proper handling of
predicated-false vector contiguous loads and predicated-false
micro-ops of vector gather loads (added in separate changesets).

Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

cpu: alpha: Delete all occurrances of the simPalCheck function.

This is now handled within the ISA description.

Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18434
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove hwrei from the generic interfaces.

This mechanism is specific to Alpha and doesn't belong sprinkled around
the CPU's generic mechanisms.

Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18432
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: cpu: Track kernel stats using the base ISA agnostic type.

Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.

In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.

Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Get rid of the (read|set)RegOtherThread methods.

These are implemented by MIPS internally now.

Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Include debug flags regardless of whether the ISA is null.

Whether debug flags are available has no interaction with what the ISA
is.

Change-Id: I71d9204f948618831796e6c7a4c16bbebfb1a4fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18428
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu,mem: missing override specifier

Change-Id: I731d3ef021596450ac307461f215760a148bb28a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: O3 switchFreeList checking VecElems instead of FloatRegs

Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.

Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Correctly account for executed instructions in simple cpus

Change-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Removed inconsistency in O3* debug msgs

Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines

Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-mips: added missing override specifier (o3)

Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Added a probe to notify the address of retired instructions

A probe is added to notify the address of each retired instruction.

Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fixed the indirect branch predictor GHR handling

The internal indirect predictor global history was not being updated
properly, resulting in higher than expected miss rates

Also added a parameter to set the size of the indirect predictor GHR

Change-Id: Ibc797816974cba6719da65122801e8919559a003
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reported-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: missing override specifier

Missing specifier of overridden virtual function
declared in sim_object.hh

Removed redundant "virtual" keyword

Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu-kvm: Added informative error message

PerfKvmCounter::attach fails if the user doesn't have privileges to make
the perf_event_open syscall. This is the default privilege setting since
kernel 4.6. I've seen some users in the mailing list resort to running
as root; changing the perf_event_paranoid setting is an alternative.

Change-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Refactor of Physical Register implementation

The implementation of the PhyRegId class is shared between multiple
cpu models. The o3/misc.hh should only be included in o3 models.

This patch removes the dependencies between different model
implementations, allowing to add new O3-like CPU model.

Change-Id: Ibb812517043befe75c48fab3ce9605a0d272870b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Segmentation Fault during O3PipeView execution

During the O3PipeView execution, a potential invalid iterator is used to
Update the instruction storeTick field.

If the store_idx iterator is the first() of the StoreQueue, the
corresponding instruction is removed from the queue, leaving the iterator
invalid and not usable in the TRACING_ON block.

This patch uses the store_inst variable to access (and update) the
instruction tick, instead of the (potential) invalid one.

Change-Id: I671052ef282b9048e5239da8629b89e8afa86bf0
Reviewed-on: https://gem5-review.googlesource.com/c/16322
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix indirect branch history updates

Recent changes to indirect branch predictor interface accesses
non-existent buffers even when indirect predictor is not in use.

Change-Id: I0df9ac4d5f6f3cb63e4d1bd36949c27f7611eef6
Reviewed-on: https://gem5-review.googlesource.com/c/16668
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

python: Fix param -> int conversion issues

Python 3 doesn't convert params to integers automatically in
range(). Add __index__ to CheckedInt to enable implicit conversions
again. Add explicit conversions where necessary.

Change-Id: I2de6c9906d3bb7616f12ada6728b9e4b1928511c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16000
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Add cache read ports limit to LSQ

This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.

Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13517
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Make iterator handling Python 3 compatible

Many functions that used to return lists (e.g., dict.items()) now
return iterators and their iterator counterparts (e.g.,
dict.iteritems()) have been removed. Switch calls to the Python 2.7
iterator methods to use the Python 3 equivalent and add explicit list
conversions where necessary.

Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15992
Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Add ISA* getter in Thread interface

This patch is adding a ISA* getter to the TC interface

Change-Id: Ib8ddc5d8fdd44e782f50a2ad15878a6bcf931e58
Reviewed-on: https://gem5-review.googlesource.com/c/16462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: Fix fast build broken due to unused variable

This fixes fast build for commit 25dc765889d948693995cfa622f001aa94b5364b
(fast build is striping out assertions)

Change-Id: I9536ad58a3d85990b16a1f8c2515f6bf5d3acf71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16463
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Added 8KB and 64KB TAGE-SC-L branch predictor

The original paper of the branch predictor can be found here:
http://www.jilp.org/cbp2016/paper/AndreSeznecLimited.pdf

Change-Id: I684863752407685adaacedebb699205c3559c528
Reviewed-on: https://gem5-review.googlesource.com/c/14855
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Proposal for changing the indirect branch predictor interface

Now the indirect branch predictor handles its own GHR instead of getting
the one from the direction predictor.

Also, now the commit method of the indirect predictor is called for every
pending branch on an update, as the indirect predictors may want to update
their interal structures/histories with the information of each branch.

Change-Id: I7053fbea42a53960a3bc1ba32912cc99c160511e
Reviewed-on: https://gem5-review.googlesource.com/c/15318
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: support atomic memory request type with AtomicOpFunctor

This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU,
MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory
system.

Atomic memory instruction is treated as a special store instruction in
all CPU models.

In simple CPUs, an AMO request with an associated AtomicOpFunctor is
simply sent to L1 dcache.

In MinorCPU, an AMO request bypasses store buffer and waits for any
conflicting store request(s) currently in the store buffer to retire
before the AMO request is sent to the cache. AMO requests are not buffered
in the store buffer, so their effects appear immediately in the cache.

In DerivO3CPU, an AMO request is inserted in the store buffer so that it
is delivered to the cache only after all previous stores are issued to
the cache. Data forwarding between between an outstanding AMO in the
store buffer and a subsequent load is not allowed since the AMO request
does not hold valid data until it's executed in the cache.

This implementation assumes that a target ISA implementation must insert
enough memory fences as micro-ops around an atomic instruction to
enforce a correct order of memory instructions with respect to its
memory consistency model. Without extra memory fences, this implementation
can allow AMOs and other memory instructions that do not conflict
(i.e., not target the same address) to reorder.

This implementation also assumes that atomic instructions execute within
a cache line boundary since the cache for now is not able to execute an
operation on two different cache lines in one single step. Therefore,
ISAs like x86 that require multi-cache-line atomic instructions need to
either use a pair of locking load and unlocking store or change the
cache implementation to guarantee the atomicity of an atomic
instruction.

Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a
Reviewed-on: https://gem5-review.googlesource.com/c/8188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: fix how branching is handled when a thread is suspended in MinorCPU

When a thread is suspended, all instructions after the suspension need
to be discarded since the thread will take a different execution stream
when it wakes up.

To do that, in MinorCPU, whenever a thread gets suspended, we change the
current execution stream by updating the current branch with
BranchData::SuspendThread reason.

Change-Id: I7cdcda22c1cf6e8ac8db8800b7d9ec052433fdf3
Reviewed-on: https://gem5-review.googlesource.com/c/9626
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: stop scheduling suspended threads in all stages of MinorCPU

This patch makes suspended threads non-schedulable in Fetch1, Fetch2,
Decode and Execute stages in MinorCPU.

Change-Id: Ie79857e13b7b782d9c58c32310993a132b609cf9
Reviewed-on: https://gem5-review.googlesource.com/c/9625
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

sim,cpu: make exit_group halt all threads in a group

When a thread calls exit_group, in addition to halting the thread
itself, it needs to halt all other threads in its group (i.e., threads
sharing the same thread group ID). This patch enables threads to do
that.

Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03
Reviewed-on: https://gem5-review.googlesource.com/c/9623
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: fixed how O3 CPU executes an exit system call

When a thread executed an exit syscall in SE mode, the thread context
was removed immediately in the same cycle, which left inflight squash
operations and trap event incomplete. The problem happened when a new
thread was assigned to the CPU later. The new thread started with some
incomplete transactions of the previous thread (e.g., squashing). This
problem could cause incorrect execution flow for the new thread (i.e.,
pc was not reset properly at the exit point), deadlock (i.e., some
stage-to-stage signals were not reset) and incorrect rename map between
logical and physical registers.

This patch adds a new state called 'Halting' to the thread context and
defers removing thread context from a CPU until a trap event initiated
by an exit syscall execution is processed. This patch also makes sure
that the removal of a thread context happens after all inflight
transactions of the to-be-removed thread in the pipeline complete.

Change-Id: If7ef1462fb8864e22b45371ee7ae67e2a5ad38b8
Reviewed-on: https://gem5-review.googlesource.com/c/8184
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: fix how a thread starts up in MinorCPU

When a thread is activated by another thread calling a clone system
call, the child thread's context is initialized in the middle of the
clone system call and before the context is fully initialized.
Therefore, the child thread starts fetching an unitialized PC, which
could lead to a page fault.

This patch adds a pipeline wakeup event that is scheduled later in the
cycle when the thread is activated. This event ensures that the first
fetch only happens after the thread context is fully initialized
(e.g., in case of clone syscall, it is when the parent thread copies
its context over to the child thread).

When a thread first starts or wakes up, input queue to the Fetch2 stage
needs to be drained since the execution flow is likely to change and
previously fetched instructions in the queue may no longer be in the
correct flow. This patch dumps/drains all inputs in the input queue
of a thread context in the Fetch2 stage when the associated thread wakes
up.

Change-Id: Iad970638e435858b7289cd471158cc0afdbbb0e5
Reviewed-on: https://gem5-review.googlesource.com/c/8182
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

misc: added missing override specifier

Added missing specifier for various virtual functions.

Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458
Reviewed-on: https://gem5-review.googlesource.com/c/16103
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Made the Loop Predictor a SimObject

The Loop Predictor implementation is now a SimObject so that other branch
predictors can easily use it (including LTAGE, which is now using it).
It has also been updated with the latest
available loop predictor implementation from Andre Seznec:

http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar

Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57
Reviewed-on: https://gem5-review.googlesource.com/c/15775
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Made TAGE a SimObject that can be used by other predictors

The TAGE implementation is now a SimObject so that other branch predictors
can easily use it. It has also been updated with the latest available TAGE
implementation from Andre Seznec:

http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar

Change-Id: I2251b8b2d7f94124f9955f52b917dc3b064f090e
Reviewed-on: https://gem5-review.googlesource.com/c/15317
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

VecElem code had been introduced in order to simulate change of renaming
for vector registers. Most of the work is happening on the rename_map
switchRenameMode. Change of renaming can happen after a squash in the
pipeline.
This patch is also changing the interface to the ISA part so that
a PCState is used instead of ISA in order to check if rename mode
has changed.

Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15601

cpu: O3 rename using the flatIndex instead of index

This patch is replacing the RegId::index with RegId::flatIndex so that
it provides a valid register number when used by a VecElem register.

Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15600
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix VecElemClass bugs in cpu models

This patch is:

* Adding a missing VecElemClass entry
* Fixing assertion in rename map which was checking the number of free
vector registers rather than free vector element registers
* Fixing assertion in read/setVecElemOperand APIs.
* Using the right register index in SimpleThread
* Using VecElem instead of VecReg on O3 readArchVecElem

Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15598
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Add VecElem entries in MinorCPU Scoreboard

This patch is:
* Increasing the number of bits in the Scoreboard so that
it is keeping track of VecElemClass dependencies.
* Fixing VecElemClass entry in the scoreboard table so that it
correctly uses flatIndex rather than index.

Change-Id: Ie4877e5fe410b1437447adebbe289602a443f7c0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15597
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: O3 LSQ Generalisation

This patch does a large modification of the LSQ in the O3 model. The
main goal of the patch is to remove the 'an operation can be served with
one or two memory requests' assumption that is present in the LSQ
and the instruction with the req, reqLow, reqHigh triplet, and
generalising it to operations that can be addressed with one request,
and operations that require many requests, embodied in the
SingleDataRequest and the SplitDataRequest.

This modification has been done mimicking the minor model to an extent,
shifting the responsibilities of dealing with VtoP translation and
tracking the status and resources from the DynInst to the LSQ via the
LSQRequest. The LSQRequest models the information concerning the
operation, handles the creation of fragments for translation and request
as well as assembling/splitting the data accordingly.

With this modifications, the implementation of vector ISAs, particularly
on the memory side, become more rich, as the new model permits a
dissociation of the ISA characteristics as vector length, from the
microarchitectural characteristics that govern how contiguous loads are
executing, allowing exploration of different LSQ to DL1 bus widths to
understand the tradeoffs in complexity and performance.

Part of the complexities introduced stem from the fact that gem5 keeps a
large amount of metadata regarding, in particular, memory operations,
thus, when an instruction is squashed while some operation as TLB lookup
or cache access is ongoing, when the relevant structure communicates to
the LSQ that the operation is over, it tries to access some pieces of
data that should have died when the instruction is squashed, leading to
asserts, panics, or memory corruption. To ensure the correct behaviour,
the LSQRequest rely on assesing who is their owner, and self-destroying
if they detect their owner is done with the request, and there will be
no subsequent action. For example, in the case of an instruction
squashed whal the TLB is doing a walk to serve the translation, when the
translation is served by the TLB, the LSQRequest detects that the
instruction was squashed, and as the translation is done, no one else
expect to access its information, and therefore, it self-destructs.
Having destroyed the LSQRequest earlier, would lead to wrong behaviour
as the TLB walk may access some fields of it.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>

Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13516
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch: cpu: Stop passing around misc registers by reference.

These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum

The smtCommitPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: I3625f2c08a1ae0c3b0dce7a641c6ae1ce3fd79a5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtROBPolicy a Param.ScopedEnum

The smtROBPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Ie104d055dbbc6e44997ae0c1470de714239be5a3
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtIQPolicy a Param.ScopedEnum

The smtIQPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Ieecf0a19427dd250b0d5ae3d531ab46a37326ae5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15398
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum

The smtLSQPolicy is a parameter in the o3 cpu that can have 3
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: I82041b88bd914c5dc660058d9e3998e3114e7c35
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15397
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum

The smtFetchPolicy is a parameter in the o3 cpu that can have 5
different values. Previously this setting was done through a string
and a parser function would turn it into a c++ enum value. This
changeset turns the string into a python Param.ScopedEnum.

Change-Id: Iafb4b4b27587541185ea912e5ed581bce09695f5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15396
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Fix usage of setArchVecElem

setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic

Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15655
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Stop using unions to store FP registers.

These are now accessed only as integer values.

Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb
Reviewed-on: https://gem5-review.googlesource.com/c/14458
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, cpu: Remove float type accessors.

Use the binary accessors instead.

Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Fixed typos in parameter/stats descriptions

Change-Id: I7b3274a3e37128da35f497da150af08343e97ee6
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14795
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Added parameters to enable/disable features in LTAGE

They are for the following features in the LTAGE loop predictor:
- Hashing for calculating the loop table entry
- Add direction information
- Add speculative iteration number information

Change-Id: I395f4526163ee0d0229d1e87cde2bb046f1dd43a
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14597
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Louis Delhez <ldelhez@ucla.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor

Change 9af1214 added a new ctor to the LSQUnit, however
there is a typo/bug because it sizes the SQEntries
member variable to lqEntries + 1, as opposed to
sqEntries + 1. This change corrects the issue by
using sqEntries.

Change-Id: I19dfaa5c0e335bd7b84343a92034147d7c5d914e
Reviewed-on: https://gem5-review.googlesource.com/c/15015
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base, sim: Add missing destructors

Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.

Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Change raw pointers to STL Containers

This patch changes two members from being raw pointers to being STL
containers. The reason behind, other than cleanlyness and arguable OO
best practices is that containers have more intronspections capabilities
than naked pointers do, as the size is known.

Using STL containers adds little overhead and eases the automation of
process during debugging (gdb).

Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Added new stats to TAGE and LTAGE branch predictors

They are basically used to tell wich component of the predictor is
providing the prediction and whether it is correct or wrong

Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14535
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: split LTAGE implementation into a base TAGE and a derived LTAGE

The new derived LTAGE is equivalent to the original LTAGE implementation
The default values of the TAGE branch predictor match the settings of the
8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf

Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14435
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Made LTAGE parameters configurable

This includes TAGE tag sizes, TAGE table sizes, U counters reset period,
loop predictor associativity, path history size, the USE_ALT_ON_NA size
and the WITHLOOP size

Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fixed useful counter handling in LTAGE

Increased to 2 bits of useful counter per TAGE entry as described in the
LTAGE paper (and made the size configurable)

Changed how the useful counters are incremented/decremented as described
in the LTAGE paper

Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14215
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fixes on the loop predictor part of LTAGE

Fixed the following fields of the loop predictor entries as described on
the LTAGE paper:
- Age counter (it was 3 bits and it should be 8 bits)
- Tag (it was 16 bits and it should be 14 bits). Also some times it used
int variables and some times uint16_t, leading to wrong behaviour
- Confidence counter (it was 2 bits ins some parts of the code and 3 bits
in some other parts. It should be 2 bits)
- Iteration counters (they were 16 bits and they should be 14 bits)
All the new sizes are now configurable

Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14216
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix LTAGE max number of allocations on update

The LTAGE paper states that only one TAGE entry can be
allocated when updating

Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14195
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Added an option for choosing branch predictor type

Added the parameter "--bp-type" to set the branch predictor type
Added the parameter "--list-bp-types" to list all the available branch
predictor types

Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14015
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix the usage of const DynInstPtr

Summary: Usage of const DynInstPtr& when possible and introduction of
move operators to RefCountingPtr.

In many places, scoped references to dynamic instructions do a copy of
the DynInstPtr when a reference would do. This is detrimental to
performance. On top of that, in case there is a need for reference
tracking for debugging, the redundant copies make the process much more
painful than it already is.

Also, from the theoretical point of view, a function/method that
defines a convenience name to access an instruction should not be
considered an owner of the data, i.e., doing a copy and not a reference
is not justified.

On a related topic, C++11 introduces move semantics, and those are
useful when, for example, there is a class modelling a HW structure that
contains a list, and has a getHeadOfList function, to prevent doing a
copy to an internal variable -> update pointer, remove from the list ->
update pointer, return value making a copy to the assined variable ->
update pointer, destroy the returned value -> update pointer.

Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal

The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)

Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fixed PC shifting on LTAGE branch predictor

The PC needs to be shifted according to the instShiftAmt parameter

Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14035
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix MinorCPU executing Crypto Instructions

Crypto instruction classes added to the MinorDefaultFloatSimdFU.

Change-Id: I0cd4aa422bec74285595312a8cf01f5f425a82cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13251
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-arm: AArch32 Crypto AES

This patch implements the AArch32 AES instructions
from the Crypto extension.

Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matt Horsnell <matt.horsnell@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13248
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: AArch32 Crypto SHA

This patch implements the AArch32 secure hashing instructions
from the Crypto extension.

Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13247
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix typo in header guard for Noncaching cpu

Change-Id: If8ec5f5f49e99d4989658273723b943dd8df84c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13144
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

Fix SConstruct for asan build

Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes
some build error when using --with-asan.

Bug: None
Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug

Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7
Reviewed-on: https://gem5-review.googlesource.com/12511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188

cpu: Turn BaseTrafficGen numSuppressed into a stat

This is changing numSuppressed from being a warn only variable into
a Stat so that it is visible at the end of simulation.

Change-Id: I934782e796c898bfc0e773cc88c597a68e403272
Reviewed-on: https://gem5-review.googlesource.com/11849
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Appease GCC 8

GCC 8 adds a number of new warnings to -Wall which generate errors.

- Fix memset to 0 for structs by adding casts.
- Fix cast with const when the const was ignored.
- Fix catch a polymorphic type by value

We now compile with GCC 8!

Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/11949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons,ruby: do not generate unnecessary files

Do not generate garnet tester file or Ruby debug headers without a Ruby
protocol (i.e. PROTOCOL=None). It makes no sense to include these files
into the build when there will be no protocol to utilize them.

Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104
Reviewed-on: https://gem5-review.googlesource.com/8381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Add hash functionality for RegId class

Having a hash function defined within the header will allow all
classes using RegId to use the class as a Key in a STL
unordered_map.

Change-Id: I32fd302a087c74e844dcbfce93fef9d0ed98d6bf
Signed-off-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/11870
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Removed unnecessary file reg_class_impl.hh

Previously, reg_class_impl.hh was added in order to prevent a cyclic
dependency between it and the_isa.hh (See
http://reviews.gem5.org/r/3754). It was determined that this was not
necessary. The two files had almost entirely the same includes, and the
current test-suite including multiple gcc and clang compilers on both
MacOS and Linux successfully built the library with all functionality
moved into the reg_class.hh file.

Change-Id: I0319e187b9eb280726a003951bb1ce315ffe17f5
Signed-off-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/11869
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Warn when (un)serializing a traffic generator

When checkpointing a system with a traffic generator, a warning is
produced so that the user is reminded serialization does not keep all
the traffic generator internal state.

Change-Id: I3c49c912c9ff3a4208f55b2da0a88fc694147280
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11831
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Allow creation of traffic gen from generic SimObjects

This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.

Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-o3: Missing freeing the heads of DepGraph in IQ squashing

Free the squahsed instructions' heads of DepGraph in IQ squashing

In a system with large register file (ex.2048), the number of
DynInst hits the hardcoded limit (1500). This is caused by
missing freeing the heads of DepGraph in IQ. IQ only clears
out the heads when instructions reach writeback stage.
If a instruction is squashed before writeback stage, its head of
dependency graph, which holds the instruction's DynInstPtr,
would not be cleared out. This prevents freeing the DynInst of the
squahsed instruction even after it is committed.

Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3
Reviewed-on: https://gem5-review.googlesource.com/7481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Add a Python-enabled traffic generator

The current traffic generator relies on a configuration file that
describes a small machine to generate stimuli. This configuration file
is usually generated by the gem5 Python configuration. This creates an
unnecessary and fragile step.

This changeset introduces a Python-based trace module. When
instantiated, the module exposes a start method that takes an iterable
object as a parameter (e.g., a generator). The iterable object is
expected to represent a list of generators that will be run one after
the other. For example:

system.tgen = PyTrafficGen()
m5.instantiate()

def trace():
yield system.tgen.createIdle(1000)
yield system.tgen.createExit(0)

system.tgen.start(trace())

Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11518
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Support trace termination in BaseTrafficGen

Make the BaseTrafficGen handle cases where getNextPacket() can't find
a new packet and returns NULL. In that case, assume the generator has
run out of packets and switch to the next generator.

Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11517
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Unify error handling for address generators

Unify error handling and create factory methods for address
generators.

Change-Id: Ic3ab705e1bb58affd498a7db176536ebc721b904
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11516
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Split the traffic generator into two classes

The traffic generator currently assumes that it is always driven from
a configuration file. Split it into a base class (BaseTrafficGen) that
handles basic packet generation and a derived class that implements
the config handling (TrafficGen).

Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11515

cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Fix bug introduced by RequestPtr type change

Missing buffer allocation in mwaitAtomic.

Change-Id: Ifccb6df2427df8b0daac5ee6a99e5cca0b20825e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Prevent suspended TimingSimple CPUs from fetching next instructions

In TimingSimpleCPU model, when a CPU is suspended by a syscall (e.g.,
futex(FUTEX_WAIT)), the CPU waits for another CPU to wake it up
(e.g., FUTEX_WAKE operation). While staying Idle, the suspended CPU
should not try to fetch next instructions after the syscall.

This patch added a status check before a CPU schedule a fetch event
after a fault is handled.

Change-Id: I0cc953135686c9b35afe94942aa1d0b245ec60a2
Reviewed-on: https://gem5-review.googlesource.com/8181
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

cpu: add a new instruction type 'Atomic'

This patch adds a new flag named 'Atomic' to support ISA implementations
that use AtomicOpFunctor to handle atomic instructions instead of a
pair of locking load and unlocking store.

Change-Id: I1fbee6e54432396cb49dfc59ad9006b75812d115
Reviewed-on: https://gem5-review.googlesource.com/8187
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu-minor: Remove redundant thread startup call

Don't call startup() twice on each of the threads.

Change-Id: Ibe3d1f25c4fdff291ee310abb9bcad3b184bab20
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11037

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Substitute pointer to Request with aliased RequestPtr

Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.

Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

cpu: Avoid unnecessary dynamic_pointer_cast in atomic model

In the atomic model a dynamic_pointer_cast is performed at every tick to
check if the fault is a SyscallRetryFault. This was happening even when
there was no generated fault.

Change-Id: I7f4afeffffdf4f988230e05286602d8d9a919c6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10101
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

cpu: Remove ExtMachInst typedefs from the O3 CPU model.

These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.

Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

This doesn't completely hide the ISA specific ExtMachInst type inside
the ISAs since it still gets applied in arch/generic, but it at least
pulls it into the arch directory.

Change-Id: Ic2188d59696530d7ecafdff0785d71867182701d
Reviewed-on: https://gem5-review.googlesource.com/9403
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Stop extracting inst_flags from the machInst.

The instruction representation is already encoded in the trace
protobuf, so there's no reason to encode a part of it again. This is
especially true since this supposedly generic code is extracting the
first 8 bits of the machInst, a totally arbitrary set of bits for most
ISAs. If certain bits within a machine instruction are actually
relevant, the consumer of the trace should be able to interpret the
instruction bytes which are already there and extract the same bits
within the context of whatever ISA they're appropriate for.

Change-Id: Idaebe6a110d7d4812c3d7c434582d5a9470bcec1
Reviewed-on: https://gem5-review.googlesource.com/9401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Use the new asBytes function in the protobuf inst tracer.

Use this function to get the binary representation of the instruction
rather than referencing the ExtMachInst typed machInst member of the
StaticInst directly. ExtMachInst is an ISA specific type and can't
always be straightforwardly squished into a 32 bit integer.

Change-Id: Ic1f74d6d86eb779016677ae45c022939ce3e2b9f
Reviewed-on: https://gem5-review.googlesource.com/7563
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Add a virtual asBytes function to the StaticInst class.

This function takes a pointer to a buffer and the current size of the
buffer as a pass by reference argument. If the size of the buffer is
sufficient, the function stores a binary representation of itself
(generally the ISA defined instruction encoding) in the buffer, and
sets the size argument to how much space it used. This could be used
by ISAs which have two instruction sizes (ARM and thumb, for example).
If the buffer size isn't sufficient, then the size parameter should be
set to what size is required, and then the function should return
without modifying the buffer.

The buffer itself should be aligned to the same standard as memory
returned by new, specifically "The pointer returned shall be suitably
aligned so that it can be converted to a pointer of any complete object
type and then used to access the object or array in the storage
allocated...". This will avoid having to memcpy buffers to avoid
unaligned accesses.

To standardize the representation of the data, it should be stored in
the buffer as little endian. Since most hosts (including ARM and x86
hosts) will be little endian, this will almost always be a no-op.

Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6
Reviewed-on: https://gem5-review.googlesource.com/7562
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

ruby: Make sure addresses print in hex

Added fix in the invalid transition panic and various places in ruby
random tester.

Change-Id: I879264da58369faf7de49d1a28b2da1cb935ef0a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8941
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

scons: Switch from the print statement to the print function.

Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.

Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu-o3: Don't add non-speculative mem barriers to the IQ twice

There are cases where the IEW adds a non-speculative instruction to
the IQ twice. This can happen if an instruction is flagged as
IsMemBarrier and IsNonSpeculative. Avoid adding non-speculative
instructions in the IEW to the IQ by checking if it has been added
already.

Change-Id: Ifcff676a451b57b2406ce00ed8dae19ed399515f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Javier Setoain <javier.setoain@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8374
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: MinorCPU handling IsSquashAfter flag

MinorCPU was not handling IsSquashAfter flagged instructions. The
behaviour was to force a branch (hence enforcing refetching) for
SerializeAfter instructions only. This has now been extended to
SquashAfter in order to correctly support ISB barrier instruction
behaviour.

Change-Id: Ie525b23350b0de121372d3b98b433e36b097d5c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5702
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: DT autogeneration - Generate cpus node

Equips cpu models with a method to generate the cpu node.

Note: even though official documentation requires that CPU ids start
counting from 0 in every cluster, GEM5 requires a globally unique cpu_id.

Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5963
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.

Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

cpu: Make the CPU's TLB parameter a BaseTLB.

This is instead of the architecture specific version.

Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

style: change C/C++ source permissions to noexec

Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).

Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

This constant is, first, a #define, and second only used in one place.

In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.

This change therefore also removes this block of code.

Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.

When a fault happens in fetch in O3, a dummy inst is created to carry
the fault through the pipeline to commit, but conceptually there isn't
actually any instruction since we failed to fetch one.

This change marks the dummy instruction as NotAnInst, and when any
such instruction gets to commit, the fault object associated with it
is invoked and passed a null static inst pointer instead of a pointer
to the dummy inst.

Change-Id: I18d993083406deb625402e06af4ba0d4772ca5a3
Reviewed-on: https://gem5-review.googlesource.com/7124
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Add a NotAnInst flag to the BaseDynInst class.

This flag means that the instruction isn't an actual instruction, it's
just a placeholder to carry a fault down a pipeline, for instance.

Change-Id: I1cc12b068662dbd3d3b089c9941a07b6e88b57e3
Reviewed-on: https://gem5-review.googlesource.com/7123
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu, power: Get rid of the remnants of the EA computation insts.

Get rid of some remnants of a system which was intended to separate
address computation into its own instruction object.

Change-Id: I23f9ffd70fcb89a8ea5bbb934507fb00da9a0b7f
Reviewed-on: https://gem5-review.googlesource.com/7122
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu: "virtualize" the TLB interface.

CPUs have historically instantiated the architecture specific version
of the TLBs to avoid a virtual function call, making them a little bit
more dependent on what the current ISA is. Some simple performance
measurement, the x86 twolf regression on the atomic CPU, shows that
there isn't actually any performance benefit, and if anything the
simulator goes slightly faster (although still within margin of error)
when the TLB functions are virtual.

This change switches everything outside of the architectures themselves
to use the generic BaseTLB type, and then inside the ISA for them to
cast that to their architecture specific type to call into architecture
specific interfaces.

The ARM TLB needed the most adjustment since it was using non-standard
translation function signatures. Specifically, they all took an extra
"type" parameter which defaulted to normal, and translateTiming
returned a Fault. translateTiming actually doesn't need to return a
Fault because everywhere that consumed it just stored it into a
structure which it then deleted(?), and the fault is stored in the
Translation object when the translation is done.

A little more work is needed to fully obviate the arch/tlb.hh header,
so the TheISA::TLB type is still visible outside of the ISAs.
Specifically, the TlbEntry type is used in the generic PageTable which
lives in src/mem.

Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575
Reviewed-on: https://gem5-review.googlesource.com/6921
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu: Use the generic nop static inst instead of decoding the arch version.

This removes a dependence on the ISA.

Change-Id: I01013bc70558f0831327213912bcac11258066a6
Reviewed-on: https://gem5-review.googlesource.com/6824
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Add a pointer to a generic Nop StaticInst.

This can be used whenever generic code needs a filler instruction that
doesn't do anything.

Change-Id: Ib245d3e880a951e229eb315a09ecc7c47e6ae00f
Reviewed-on: https://gem5-review.googlesource.com/6823
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.

Change-Id: I868021a01eb3e7902a4d64283bdfaa93c6d9f964
Reviewed-on: https://gem5-review.googlesource.com/6822
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-tester: Added ExitGen to TrafficGen

Added the ExitGen to the TrafficGenerator which allows an EXIT
state to be added to the TrafficGen configuration file. Entering this
state will cause the simulation to exit immediately. Please note that
if multiple TrafficGen instances have an EXIT state, the first of these
to be encountered will cause the simulation to terminate.

Change-Id: Ieea51f05ffb780771f007787a2b119f79143d0c1
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5723
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

misc: Updates for gcc7.2 for x86

GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
case statments. C++17 adds the [[fallthrough]]; declaration. However,
to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
if that doesn't exist, it defaults to nothing (no older compilers
generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>

arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

Neither of these were used, particularly memAccInst.

Change-Id: I4ac9e44cf624e5de42519d586d7b699f08a2cdfc
Reviewed-on: https://gem5-review.googlesource.com/6601
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

x86,misc: add additional info on faulting X86 instruction, fetched PC

Print faulting instruction for unmapped address panic in faults.cc
and print extra info about corresponding fetched PC in base.cc.

Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f
Reviewed-on: https://gem5-review.googlesource.com/6461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Add support for CMOs in the cpu models

Cache maintenance operations go through the write channel of the
cpu. This changes makes sure that the cpu does not try to fill in the
packet with data.

Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5055
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>