12588:c007da6c777a |
29-Jan-2018 |
Gabe Black <gabeblack@google.com> |
x86: Add bitfields which can gather/scatter bases and limits.
Add bitfields which can gather/scatter base and limit fields within "normal" segment descriptors, and in TSS descriptors which have the same bitfields in the same positions for those two values.
This centralizes the code which manages those bitfields and makes it less likely that a local implementation will be buggy.
Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275 Reviewed-on: https://gem5-review.googlesource.com/7661 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
12334:e0ab29a34764 |
30-Nov-2017 |
Gabe Black <gabeblack@google.com> |
misc: Rename misc.(hh|cc) to logging.(hh|cc)
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.).
Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> |
11324:31ca646c7685 |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others. |
11168:f98eb2da15a4 |
12-Oct-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions. |
10554:fe2e2f06a7c8 |
23-Nov-2014 |
Alexandru Dutu <alexandru.dutu@amd.com> |
x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. |
9921:ee049bfce978 |
15-Oct-2013 |
Yasuko Eckert <yasuko.eckert@amd.com> |
arch/x86: add support for explicit CC register file
Convert condition code registers from being specialized ("pseudo") integer registers to using the recently added CC register class.
Nilay Vaish also contributed to this patch. |
9875:5cfad3486991 |
18-Sep-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
x86: Expose the raw hash map of MSRs
This patch allows the KVM CPU module to initialize it's MSRs by enumerating the MSRs in the gem5 x86 implementation. |
9470:68f7e0bcf4aa |
15-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implement fabs, fchs instructions |
9211:46c3a74952ec |
11-Sep-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: Add a separate register for D flag bit The D flag bit is part of the cc flag bit register currently. But since it is not being used any where in the implementation, it creates an unnecessary dependency. Hence, it is being moved to a separate register. |
9010:7891b96e1526 |
22-May-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
X86: Split Condition Code register This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch. |
8902:75b524b64c28 |
19-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts). |
8582:dd79a696b91c |
23-Sep-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the TLB source and made looking around in that file awkward. This change moves the lookup into its own file to get it out of the way. It also changes it from a switch statement to a hash map which should hopefully be a little more efficient. |
7629:0f0c231e3e97 |
23-Aug-2010 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Create a directory for files that define register indexes.
This is to help tidy up arch/x86. These files should not be used external to the ISA. |