x86: Simplify the implementations of RDTSC and RDTSCP slightly.

These instructions originally read the TSC into t1 and then unpacked it
into eax and edx using a move, a right shift, and then another move.
We can combine the second shift and move. The shift will move the
upper 32 bits into the lower 32 bits, and clear the upper 32 bits to
zero. This has the same effect as moving the lower 32 bits post-shift
into another register, since the upper 32 bits will be cleared to zero
based on x86 partial register access semantics.

Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
Reviewed-on: https://gem5-review.googlesource.com/9044
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Implement the RDTSCP instruction.

This is very similar to RDTSC, except that it requires all younger
instructions to retire before it completes, and it writes the TSC_AUX
MSR into ECX. I've added an mfence as an iniitial microop to ensure
that memory accesses complete before RDTSCP runs, and added an rdval
microop at the end to read the TSC_AUX value into ECX.

Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
Reviewed-on: https://gem5-review.googlesource.com/9043
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Mark the RDTSC instruction as .serialize_before.

Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde
Reviewed-on: https://gem5-review.googlesource.com/9042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: x86 instruction-implementation bug fixes

Added explicit data sizes and an opcode type for correct execution.

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

X86: Fix the Lldt instructions so they load the ldtr and not the tr.

X86: Mark serializing macroops and regular instructions as such.

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix setting the busy bit in the task descriptor in LTR.

X86: Take limitted advantage of the compilers type checking for microop operands.

X86: Explicitly use the right width in a few places that need a 64 bit value.

X86: Implement the save machine status word instruction (SMSW).

X86: Implement the load machine status word instruction (LMSW).

X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

X86: Implement the lldt instruction.

X86: Implement CLTS.

X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.

X86: Do a merge for the zero extension microop.

X86: Implement the LTR instruction.

X86: Implement the swapgs instruction.

X86: Bypass unaligned access support for register addressed MSRs.

X86: Add in some support for the tsc register.

X86: Implement the INVLPG instruction and the TIA microop.

X86: Fix the wrmsr instruction.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the LIDT instruction.

X86: Implement the lgdt instruction.

X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.

X86: Impelement the HLT instruction and fix the "halt" microop.

X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.

X86: Add classes for the actual x86 faults.

Implement UD2 and replace the place holder in the decoder.