arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts

Making the implementation of movntps/movntpd consistent with other
non-temporal instructions. We are ignoring the hint here, and
implementing those instructions as cacheable instructions.

This change adds a warning to let user know about this workaround.
Also, this change add the address check for second part of move.

Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: implement movntps/movntpd SSE insts

These are non-temporal packed SSE stores.

Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466
Reviewed-on: https://gem5-review.googlesource.com/9861
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix problem with movhps instruction

This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.

This fix is needed for the perlbmk spec2k benchmark to run.

X86: Replace "DISPLACEMENT" with disp in movhpd.

Fix problem with the x86 sse movhpd instruction.

The movhpd instruction was writing to the wrong memory offset.

X86: Implement MOVSS.

X86: Implement the instructions that move sign bits.

X86: Implement the MOVDDUP instruction.

X86: Implement many of the media mov instructions.

X86: Use suffixes to differentiate XMM/MMX/GPR operands.

X86: Fix places where movfp was used incorrectly.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.