arch-x86: Adding warning for movnti

We are ignoring the non-temporal hint here, and implementing this
instruction as a cacheable instruction.

This change adds a warning to let user know about this workaround.

Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Fix implicit stack addressing in 64-bit mode

When in 64-bit mode, if the stack is accessed implicitly by an instruction
the alternate address prefix should be ignored if present.

This patch adds an extra flag to the ldstop which signifies when the
address override should be ignored. Then, for all of the affected
instructions, this patch adds two options to the ld and st opcode to use
the current stack addressing mode for all addresses and to ignore the
AddressSizeFlagBit. Finally, this patch updates the x86 TLB to not
truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit
is set.

This fixes a problem when calling __libc_start_main with a binary that is
linked with a recent version of ld. This version of ld uses the address
override prefix (0x67) on the call instruction instead of a nop.

Note: This has not been tested in compatibility mode and only the call
instruction with the address override prefix has been tested.

See [1] page 9 (pdf page 45)

For instructions that are affected see [1] page 519 (pdf page 555).

[1] http://support.amd.com/TechDocs/24594.pdf

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

x86: Fix setting segment bases in real mode.

The data size used for actually writing the base value for the segment was the
default size, but really it should set the entire value without any possible
truncation.

x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.

X86: Replace the stupd microop with a store/update sequence.

X86: Mark serializing macroops and regular instructions as such.

Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix bugs in movd implementation.

Unfortunately my implementation of the movd instruction had two bugs.

In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.

The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.

X86: Implement movd_Vo_Edp on X86

This patch implements the movd_Vo_Edp series of instructions.

It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.

This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.

X86: Implement MOVNTI.

X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.

X86: Don't truncate the immediate parameter for the ENTER instruction.

X86: Adjust the various sizes used for the enter and leave instructions.

X86: Fix a copy/paste error for cmovnp.

X86: Fix a number of places where the wrong form of a microop was used.

X86: Implement a locking version of XCHG.

X86: Fix the mov to segment selector in real mode instruction microcode.

X86: Set address size to 64 bits when generating addresses internally.

X86: Make rdcr use merge and the mov to control register instructions use the right operand size.

X86: Implement the mov to debug register intructions.

X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.

X86: Do a merge for the zero extension microop.

X86: Create a SeqOp class of microops and make Br one of them.

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

X86: Fix the microcode for sign/zero extending moves that use high byte registers.

X86: Change how segment loading is performed.

X86: Make pushes and pops use the stack size instead of the data size.

X86: Fix a byte register indexing issue in the sign extending move from memory microcode.

X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.

X86: Implement mov from control register.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the wrcr microop which writes a control register, and some control register work.

X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.

X86: Use the cda microop where appropriate. The ENTER instruction still needs these.

X86: Start using the stupd microop, and update statistics accordingly.

X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER.

X86: Implement the ENTER instruction. This could probably be optimized by cleaning up the indexing in the main loop.

X86: Added some new versions of MOV and a new argument type tag.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.