arch-x86: Adding warning for movnti

We are ignoring the non-temporal hint here, and implementing this
instruction as a cacheable instruction.

This change adds a warning to let user know about this workaround.

Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Use operand size 4 when it would be 2 for cmpxchg8b.

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: LOOP's operand size defaults to 64 bits in 64 bit mode.

The microcode for those instructions needs a directive which overrides
that setting in the instructions emulation environment.

Reported-by: Matt Sinclair <mattdsinclair@gmail.com>

Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967
Reviewed-on: https://gem5-review.googlesource.com/6301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Fix implicit stack addressing in 64-bit mode

When in 64-bit mode, if the stack is accessed implicitly by an instruction
the alternate address prefix should be ignored if present.

This patch adds an extra flag to the ldstop which signifies when the
address override should be ignored. Then, for all of the affected
instructions, this patch adds two options to the ld and st opcode to use
the current stack addressing mode for all addresses and to ignore the
AddressSizeFlagBit. Finally, this patch updates the x86 TLB to not
truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit
is set.

This fixes a problem when calling __libc_start_main with a binary that is
linked with a recent version of ld. This version of ld uses the address
override prefix (0x67) on the call instruction instead of a nop.

Note: This has not been tested in compatibility mode and only the call
instruction with the address override prefix has been tested.

See [1] page 9 (pdf page 45)

For instructions that are affected see [1] page 519 (pdf page 555).

[1] http://support.amd.com/TechDocs/24594.pdf

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

x86: revamp cmpxchg8b/cmpxchg16b implementation

The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models. It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops. It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.

This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg. This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

x86: x86 instruction-implementation bug fixes

Added explicit data sizes and an opcode type for correct execution.

x86: Fix setting segment bases in real mode.

The data size used for actually writing the base value for the segment was the
default size, but really it should set the entire value without any possible
truncation.

x86: Fix some bugs in the real mode far jmp instruction.

The far pointer should be shifted right to get the selector value, not left.
Also, when calculating the width of the offset, the wrong register was used in
one spot.

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

x86: Implementation of Int3 and Int_Ib in long mode

This is an implementation of the x86 int3 and int immediate
instructions for long mode according to 'AMD64 Programmers Manual
Volume 3'.

x86: mark instructions for being function call/return
Currently call and return instructions are marked as IsCall and IsReturn. Thus, the
branch predictor does not use RAS for these instructions. Similarly, the number of
function calls that took place is recorded as 0. This patch marks these instructions
as they should be.

x86: increment the stack pointer in lret inst
The 'lret' instruction reloads instruction pointer and code segment from the
stack and then pops them. But the popping part is missing from the current
implementation. This caused incorrect behavior in some code related to the
Fiasco OS. Microops are being added to rectify the behavior of the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

X86: Fix the IMUL_R_P_I macroop.

The disp displacement was left off the load microop so the wrong value was
used.

X86: Add memory fence to I/O instructions

x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.

X86: Mark IO reads and writes as non-speculative.

X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.

During SYSCALL_64, use dataSize=8 when handling new rip (ref
http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit
address)

X86: Fix JMP_FAR_I to unpack a far pointer correctly.

JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.

X86: Read the LDT/GDT at CPL0 when executing an iret.

During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).

X86: Replace the stupd microop with a store/update sequence.

X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions.

X86: Mark serializing macroops and regular instructions as such.

Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix bugs in movd implementation.

Unfortunately my implementation of the movd instruction had two bugs.

In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.

The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.

X86: Implement movd_Vo_Edp on X86

This patch implements the movd_Vo_Edp series of instructions.

It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.

This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.

X86: Fix checking the NT bit during an IRET.

X86: Implement MOVNTI.

X86: Turn the DIV and IDIV microcode into templates and generate all the variants.

X86: Remove some FIXMEs from IDIV that have been fixed.

X86: Turn the CMPXCHG8B microcode into a template and generate each variant.

X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug.

X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.

X86: Don't clobber the original dividend when doing signed divide.

X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.

X86: (Re)Implemented SHRD.

X86: Implement SHLD.

X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.

X86: Don't truncate the immediate parameter for the ENTER instruction.

X86: Adjust the various sizes used for the enter and leave instructions.

X86: Make scas compare its operands in the right order.

X86: Fix a copy/paste error for cmovnp.

X86: Fix condition code setting for signed multiplies with negative results.

X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.

X86: Fix the indexing for ah in byte division instructions.

X86: Fix the indexing for ah in byte multiply instructions.

X86: Set the flags on rotate left with carry instructions.

X86: Set the flags for rotate right with carry instructions.

X86: Set the flags on a rotate right instruction.

X86: Actually set the flags on a rotate left instruction.

X86: Fix a number of places where the wrong form of a microop was used.

X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.

X86: Keep track of more descriptor state to accomodate KVM.

X86: Implement a locking version of XADD.

X86: Implement a locking version of BTC.

X86: Implement a locking version of BTR.

X86: Implement a locking version of CMPXCHG.

X86: Implement a locking version of BTS.

X86: Implement a locking version of DEC.

X86: Implement a locking version of INC.

X86: Implement a locking version of NEG.

X86: Implement a locking version of NOT.

X86: Implement a locking version of XCHG.

X86: Implement a locking version of XOR.

X86: Implement a locking version of SUB.

X86: Implement a locking version of AND.

X86: Implement a locking version of SBB.

X86: Implement a locking version of ADC.

X86: Implement a locking version of OR.

X86: Implement a locking version of ADD.

X86: Make the TEST instruction set all the flags it's supposed to.

X86: Explicitly use the right width in a few places that need a 64 bit value.

X86: Implement far jmp.

X86: Fix the mov to segment selector in real mode instruction microcode.

Merge ARM into the head. ARM will compile but may not actually work.

X86: Implement shrd.

X86: Set address size to 64 bits when generating addresses internally.

X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

X86: Compute shift instruction flags correctly.

X86: Make rdcr use merge and the mov to control register instructions use the right operand size.

X86: Make the segment register reading microops use merge.

X86: Implement the mov to debug register intructions.

X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.

X86: Do a merge for the zero extension microop.

X86: Implement a basic prefetch instruction.

X86: Update CS later so stack accesses have the right permission checks.

X86: Implement the sysret instruction in long mode.

X86: Implement the longmode versions of the syscall instruction.

X86: Fix the microcode for the LODS instruction.

X86: Implement the xadd instruction.

X86: Implement the bswap instruction.

X86: Fix a bug in the iret microcode.

X86: Fix the segment setting code in IRET, and make it restore the flags.

X86: Create a SeqOp class of microops and make Br one of them.

X86: Implement CPUID with a magical function instead of microcode.

X86: Make far ret modify CS instead of some random selector.

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

X86: Fix the microcode for sign/zero extending moves that use high byte registers.

X86: Make the cpuid processor identifier return a real string.

X86: Implement and hook up STI and CLI instructions.

X86: Implement a partial, sort of correct version of the protected mode variant of iret.

X86: Change how segment loading is performed.

X86: Make pushes and pops use the stack size instead of the data size.

X86: Add microops and supporting code to manipulate the whole rflags register.

X86: Redo BSF.

X86: Make string instructions work when rcx=0.

X86: Bypass unaligned access support for register addressed MSRs.

X86: Fix the implementation of BSF.

X86: Bit scan forward/reverse were accidentally transposed.

X86: Fix a byte register indexing issue in the sign extending move from memory microcode.

X86: Optomize the bit scanning instruction microassembly a little. More can be done.

X86: Implement and attach the BSR and BSF instructions.

X86: Fill out group17 in the decoder.

X86: Redo the bit test instructions.

X86: Fix the general IO instructions dataSize.

X86: Please excuse my dear Aunt Sally. (precedence bug)

X86: Make sure the memory index is calculated using the address size for bit test instructions.

X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register.

X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.

X86: Fix a copy paste error in the bts microcode.

X86: Implement mov from control register.

X86: First crack at far returns. This is grossly approximate.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the wrcr microop which writes a control register, and some control register work.

X86: Implement some bit testing instructions.

X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.

X86: Use the cda microop where appropriate. The ENTER instruction still needs these.

X86: Start using the stupd microop, and update statistics accordingly.

X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER.

X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions.

X86: Implement the ENTER instruction. This could probably be optimized by cleaning up the indexing in the main loop.

X86: Implement the string IO instructions, ins and outs.

X86: Implement the undocumented SALC instruction which sets AL to 0xFF if CF=1 and 0x00 otherwise.

X86: Implement the XLAT instruction.

X86: Implement the BOUND instruction.

X86: Implement the in/out instructions. These will still need support from the TLB and memory system.

X86: Implement the LOOP instructions.

X86: Implemented the jrcx instruction.

X86: Added some new versions of MOV and a new argument type tag.

X86: Implemented LODS.

X86: Distinguish between the rep and repe prefixes.
STOS and MOVS only accept the rep prefix which always loops until rcx becomes
0. The other string instructions accept repe (same encoding as rep) and repne
which also check the condition code flags each iteration.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Implement MOVS

X86: Implement STOS.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.