arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts

Making the implementation of movntps/movntpd consistent with other
non-temporal instructions. We are ignoring the hint here, and
implementing those instructions as cacheable instructions.

This change adds a warning to let user know about this workaround.
Also, this change add the address check for second part of move.

Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Change warn to warn_once for NT instructions

Change-Id: I50353716f2a913b9b106b140644d95991879f662
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Adding warning for movnti

We are ignoring the non-temporal hint here, and implementing this
instruction as a cacheable instruction.

This change adds a warning to let user know about this workaround.

Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-x86: implement movntq/movntdq instructions

Non-temporal quadword/double-quadword move instructions.
This change ignores the non-temporal hint and instructions are
implemented to send cacheable request to memory.
This would have some "performance" impact (i.e. having some cache
pollution) to get better "correctness" in behavior.

Change-Id: I2052ac0970f61a54bafb7332762debcb7103202d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20288
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: fix movsd bug on %xmm register

The movsd instruction should zero out half the register, but
does not do it. This changeset adds the necessary microop to
the instruction to cause correct behavior.

Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: implement movntps/movntpd SSE insts

These are non-temporal packed SSE stores.

Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466
Reviewed-on: https://gem5-review.googlesource.com/9861
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Simplify the implementations of RDTSC and RDTSCP slightly.

These instructions originally read the TSC into t1 and then unpacked it
into eax and edx using a move, a right shift, and then another move.
We can combine the second shift and move. The shift will move the
upper 32 bits into the lower 32 bits, and clear the upper 32 bits to
zero. This has the same effect as moving the lower 32 bits post-shift
into another register, since the upper 32 bits will be cleared to zero
based on x86 partial register access semantics.

Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b
Reviewed-on: https://gem5-review.googlesource.com/9044
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Implement the RDTSCP instruction.

This is very similar to RDTSC, except that it requires all younger
instructions to retire before it completes, and it writes the TSC_AUX
MSR into ECX. I've added an mfence as an iniitial microop to ensure
that memory accesses complete before RDTSCP runs, and added an rdval
microop at the end to read the TSC_AUX value into ECX.

Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9
Reviewed-on: https://gem5-review.googlesource.com/9043
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Mark the RDTSC instruction as .serialize_before.

Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde
Reviewed-on: https://gem5-review.googlesource.com/9042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Replace the .serializing directive with .serialize_(before|after).

This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.

The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.

Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Use operand size 4 when it would be 2 for cmpxchg8b.

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Split apart x87's FSW and TOP, and add a missing break.

The FSW and TOP values are technically part of the same register, but
they have very different behaviors. One of them can be renamed and
float along without affecting global state, while the other requires
serialization. They just need to *look* like the same register when
read by the user.

Also, there was a missing break in setMiscRegNoEffect.

Change-Id: If58de0f566f65068208240f4001209fb9e1826d6
Reviewed-on: https://gem5-review.googlesource.com/6441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: LOOP's operand size defaults to 64 bits in 64 bit mode.

The microcode for those instructions needs a directive which overrides
that setting in the instructions emulation environment.

Reported-by: Matt Sinclair <mattdsinclair@gmail.com>

Change-Id: I474d938c0b3cf01da92ec817a58b08de783f1967
Reviewed-on: https://gem5-review.googlesource.com/6301
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Fix implicit stack addressing in 64-bit mode

When in 64-bit mode, if the stack is accessed implicitly by an instruction
the alternate address prefix should be ignored if present.

This patch adds an extra flag to the ldstop which signifies when the
address override should be ignored. Then, for all of the affected
instructions, this patch adds two options to the ld and st opcode to use
the current stack addressing mode for all addresses and to ignore the
AddressSizeFlagBit. Finally, this patch updates the x86 TLB to not
truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit
is set.

This fixes a problem when calling __libc_start_main with a binary that is
linked with a recent version of ld. This version of ld uses the address
override prefix (0x67) on the call instruction instead of a nop.

Note: This has not been tested in compatibility mode and only the call
instruction with the address override prefix has been tested.

See [1] page 9 (pdf page 45)

For instructions that are affected see [1] page 519 (pdf page 555).

[1] http://support.amd.com/TechDocs/24594.pdf

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

x86: revamp cmpxchg8b/cmpxchg16b implementation

The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models. It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops. It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.

This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg. This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

x86: implement rcpps and rcpss SSE insts

These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.

This code was basically developed by copying the code for
sqrtps and sqrtss. The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.

x86: implement fild, fucomi, and fucomip x87 insts

fild loads an integer value into the x87 top of stack register.
fucomi/fucomip compare two x87 register values (the latter
also doing a stack pop).
These instructions are used by some versions of GNU libstdc++.

x86: x86 instruction-implementation bug fixes

Added explicit data sizes and an opcode type for correct execution.

x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardware the size of some of these registers is smaller.
Previsouly all 64 bits where incorrectly set and then later read. To
ensure correctness we mask the value in setMiscRegNoEffect to write
only the valid bits.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

x86: implements x87 mult/div instructions

x86 : fxsave and fxrestore missing template code

This patch corrects the FXSAVE and FXRSTOR Macroops. The actual code used for
saving/restore the FP registers is in the file but it was not used.

The FXSAVE and FXRSTOR instructions are used in the kernel for saving and
loading the state of the mmx,xmm and fpu registers.

This operation is triggered in FS by issuing a Device Not Available Fault. The
cr0 register has a TS flag that is set upon each context change. Every time a
task access any FP related register (SIMD as well) if the TS flag is set to
one, the device not available fault is issued. The kernel saves the current
state of the registers, and restore the previous state of the currently running
task.

Right now Gem5 lacks of this capability. the Device Not Available Fault is
never issued, leading to several problems when different threads share the same
CPU and SMT is not used. The PARSEC Ferret benchmark is an example of this
behavior.

In order to test this a hack in the atomic cpu code was done to detect if a
static instruction has any FP operands and the cr0 reg TS bit is set. This
check must be done in the ISA dependent code. But it seems to be tricky to
access the cr0 register while executing an instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

x86: implements the simd128 ADDSUBPD instruction

This patch implements the simd128 ADDSUBPD instruction for the x86 architecture.

Tested with a simple program in assembly language which executes the
instruction. Checked that different versions of the instruction are executed
by using the execution tracing option.

Committed by: Nilay Vaish <nilay@cs.wisc.edu

x86: Fix setting segment bases in real mode.

The data size used for actually writing the base value for the segment was the
default size, but really it should set the entire value without any possible
truncation.

x86: Fix some bugs in the real mode far jmp instruction.

The far pointer should be shifted right to get the selector value, not left.
Also, when calculating the width of the offset, the wrong register was used in
one spot.

arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".

x86: use lfpimm instead of limm for fptan

x86: implements x87 add/sub instructions

x86: implements fxch instruction.

x86: Implementation of Int3 and Int_Ib in long mode

This is an implementation of the x86 int3 and int immediate
instructions for long mode according to 'AMD64 Programmers Manual
Volume 3'.

x86: Add support for FXSAVE, FXSAVE64, FXRSTOR, and FXRSTOR64

x86: Add support for FLDENV & FNSTENV

x86: Add support for loading 32-bit and 80-bit floats in the x87

The x87 FPU supports three floating point formats: 32-bit, 64-bit, and
80-bit floats. The current gem5 implementation supports 32-bit and
64-bit floats, but only works correctly for 64-bit floats. This
changeset fixes the 32-bit float handling by correctly loading and
rounding (using truncation) 32-bit floats instead of simply truncating
the bit pattern.

80-bit floats are loaded by first loading the 80-bits of the float to
two temporary integer registers. A micro-op (cvtint_fp80) then
converts the contents of the two integer registers to the internal FP
representation (double). Similarly, when storing an 80-bit float,
there are two conversion routines (ctvfp80h_int and cvtfp80l_int) that
convert an internal FP register to 80-bit and stores the upper 64-bits
or lower 32-bits to an integer register, which is the written to
memory using normal integer stores.

x86: Fix re-entrancy problems in x87 store instructions

X87 store instructions typically loads and pops the top value of the
stack and stores it in memory. The current implementation pops the
stack at the same time as the floating point value is loaded to a
temporary register. This will corrupt the state of the x87 stack if
the store fails. This changeset introduces a pop87 micro-instruction
that pops the stack and uses this instruction in the affected
macro-instructions to pop the stack after storing the value to memory.

x86: Fix loading of floating point constants

This changeset actually fixes two issues:

* The lfpimm instruction didn't work correctly when applied to a
floating point constant (it did work for integers containing the
bit string representation of a constant) since it used
reinterpret_cast to convert a double to a uint64_t. This caused a
compilation error, at least, in gcc 4.6.3.

* The instructions loading floating point constants in the x87
processor didn't work correctly since they just stored a truncated
integer instead of a double in the floating point register. This
changeset fixes the old microcode by using lfpimm instruction
instead of the limm instructions.

x86: Make fprem like the fprem on a real x87

The current implementation of fprem simply does an fmod and doesn't
simulate any of the iterative behavior in a real fprem. This isn't
normally a problem, however, it can lead to problems when switching
between CPU models. If switching from a real CPU in the middle of an
fprem loop to a simulated CPU, the output of the fprem loop becomes
correupted. This changeset changes the fprem implementation to work
like the one on real hardware.

x86: Fix the flag handling code in FABS and FCHS

This changeset fixes two problems in the FABS and FCHS
implementation. First, the ISA parser expects the assignment in
flag_code to be a pure assignment and not an and-assignment, which
leads to the isa_parser omitting the misc reg update. Second, the FCHS
and FABS macro-ops don't set the SetStatus flag, which means that the
default micro-op version, which doesn't update FSW, is executed.

x86: mark instructions for being function call/return
Currently call and return instructions are marked as IsCall and IsReturn. Thus, the
branch predictor does not use RAS for these instructions. Similarly, the number of
function calls that took place is recorded as 0. This patch marks these instructions
as they should be.

x86: increment the stack pointer in lret inst
The 'lret' instruction reloads instruction pointer and code segment from the
stack and then pops them. But the popping part is missing from the current
implementation. This caused incorrect behavior in some code related to the
Fiasco OS. Microops are being added to rectify the behavior of the instruction.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

x86: implement some of the x87 instructions
This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.

x86: implements fsin, fcos instructions

x86: implements emms instruction

x86: implement fabs, fchs instructions

x86: implement x87 fp instruction fnstsw
This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.

x86: implement x87 fp instruction fsincos
This patch implements the fsincos instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.

x86 ISA: Implement the sse3 haddps instruction.

Shuffle the 32 bit values into position, and then add in parallel.

X86: Fix the IMUL_R_P_I macroop.

The disp displacement was left off the load microop so the wrong value was
used.

X86: Add memory fence to I/O instructions

x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.

X86: Fix the Lldt instructions so they load the ldtr and not the tr.

X86: Mark IO reads and writes as non-speculative.

X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.

During SYSCALL_64, use dataSize=8 when handling new rip (ref
http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit
address)

X86: Fix JMP_FAR_I to unpack a far pointer correctly.

JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.

X86: Read the LDT/GDT at CPL0 when executing an iret.

During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).

X86: Replace the stupd microop with a store/update sequence.

X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions.

X86: Mark serializing macroops and regular instructions as such.

Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses

copyright: Change HP copyright on x86 code to be more friendly

X86: Add a common named flag for signed media operations.

X86: Create a common flag with a name to indicate high multiplies.

X86: Create a common flag with a name to indicate scalar media instructions.

X86: Fix bugs in movd implementation.

Unfortunately my implementation of the movd instruction had two bugs.

In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.

The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.

X86: Fix problem with movhps instruction

This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.

This fix is needed for the perlbmk spec2k benchmark to run.

X86: Add support for x86 psrldq and pslldq instructions

These are complicated instructions and the micro-code might be suboptimal.

This has been tested with some small sample programs (attached)

The psrldq instruction is needed by various spec2k programs.

X86: Implement movd_Vo_Edp on X86

This patch implements the movd_Vo_Edp series of instructions.

It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.

This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.

X86: Implement the X86 sse2 haddpd instruction

This patch implements the haddpd instruction.

It fixes the problem in the previous version (pointed out by Gabe Black)
where an incorrect result would happen if you issue the instruction
with the same argument twice, i.e. "haddpd %xmm0,%xmm0"

This instruction is used by many spec2k benchmarks.

X86: Replace "DISPLACEMENT" with disp in movhpd.

Fix problem with the x86 sse movhpd instruction.

The movhpd instruction was writing to the wrong memory offset.

Implement X86 sse2 movdqu and movdqa instructions

The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.

These instructions are needed for most of x86_64 spec2k to run.

X86: Fix checking the NT bit during an IRET.

X86: Fix setting the busy bit in the task descriptor in LTR.

X86: Fix the decoding for and fill out FST and FSTP.

X86: Implement MOVNTI.

X86: Implement MOVQ2DQ.

X86: Implement MOVDQ2Q.

X86: Implement the media instructions that convert fp values to ints.

X86: Implement the instructions that compare fp values and write a mask as a result.

X86: Implement the instructions that compare fp values and write to rflags.

X86: Implement MOVSS.

X86: Implement LDMXCSR.

X86: Implement STMXCSR.

X86: Implement the shuffle media instructions.

X86: Implement the mask move instructions.

X86: Implement the instructions that move sign bits.

X86: Implement the insert/extract instructions.

X86: Implement the media average instructions.

X86: Implement the multiply and add instructions.

X86: Implement the media shifts that operate on 64 bits or less at a time.

X86: Implement the sum of absolute differences instructions.

X86: Implement the media integer subtract instructions.

X86: Implement the integer media multiply instructions.

X86: Implement the integer media max instructions.

X86: Implement the integer media min instructions.

X86: Implement the media integer addition instructions.

X86: Implement the instructions that convert between forms of floating point.

X86: Implement the instructions that compare fp values and write masks as the result.

X86: Implement the MOVDDUP instruction.

X86: Implement many of the media mov instructions.

X86: Implement the media instructions that convert integer values to floating point.

X86: Implement the floating point media instructions.

X86: Implement the floating point media multiply instructions.

X86: Implement the floating point media subtract instructions.

X86: Implement the floating point media add instructions.

X86: Implement the media sqrt instructions.

X86: Implement the media floating point max instructions.

X86: Implement the media floating point min instructions.

X86: Implement the pack instructions.

X86: Rename sel to ext for media microops.

X86: Move the MMX version of MOVD into the simd64 directory.

X86: Implement the remaining unpack instructions.

X86: Implement PANDN, ANDNPS, and ANDNPD.

X86: Implement PAND, ANDPS, and ANDPD.

X86: Implement POR, ORPD and ORPS.

X86: Implement PXOR.

X86: (Re)implement XORPS and XORPD.

X86: Implement PUNPCKLQDQ.

X86: Implement PUNPCKHQDQ.

X86: Implement PUNPCKHDQ.

X86: Implement PUNPCKHWD.

X86: Implement PUNPCKHBW.

X86: Implement PUNPCKLDQ.

X86: Implement PUNPCKLWD.

X86: Implement the versions of PUNPCKLBW that use XMM registers.

X86: Implement the MOVQ instruction.

X86: Implement the versions of MOVD that have an MMX source.

X86: Implement the versions of PUNPCKLBW that use MMX registers.

X86: Implement the versions of MOVD that have an MMX destination.

X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.

X86: Use suffixes to differentiate XMM/MMX/GPR operands.

X86: Turn the DIV and IDIV microcode into templates and generate all the variants.

X86: Remove some FIXMEs from IDIV that have been fixed.

X86: Turn the CMPXCHG8B microcode into a template and generate each variant.

X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug.

X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.

X86: Don't clobber the original dividend when doing signed divide.

X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.

X86: (Re)Implemented SHRD.

X86: Implement SHLD.

X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.

X86: Don't truncate the immediate parameter for the ENTER instruction.

X86: Adjust the various sizes used for the enter and leave instructions.

X86: Make scas compare its operands in the right order.

X86: Fix a copy/paste error for cmovnp.

X86: Fix condition code setting for signed multiplies with negative results.

X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.

X86: Fix the indexing for ah in byte division instructions.

X86: Fix the indexing for ah in byte multiply instructions.

X86: Set the flags on rotate left with carry instructions.

X86: Set the flags for rotate right with carry instructions.

X86: Set the flags on a rotate right instruction.

X86: Actually set the flags on a rotate left instruction.

X86: Take limitted advantage of the compilers type checking for microop operands.

X86: Fix a number of places where the wrong form of a microop was used.

X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.

X86: Keep track of more descriptor state to accomodate KVM.

X86: Implement a locking version of XADD.

X86: Implement a locking version of BTC.

X86: Implement a locking version of BTR.

X86: Implement a locking version of CMPXCHG.

X86: Implement a locking version of BTS.

X86: Implement a locking version of DEC.

X86: Implement a locking version of INC.

X86: Implement a locking version of NEG.

X86: Implement a locking version of NOT.

X86: Implement a locking version of XCHG.

X86: Implement a locking version of XOR.

X86: Implement a locking version of SUB.

X86: Implement a locking version of AND.

X86: Implement a locking version of SBB.

X86: Implement a locking version of ADC.

X86: Implement a locking version of OR.

X86: Implement a locking version of ADD.

X86: Make the TEST instruction set all the flags it's supposed to.

X86: Explicitly use the right width in a few places that need a 64 bit value.

X86: Implement far jmp.

X86: Make the interrupt entering microcode record the value to use, not actually use it.

X86: Implement the save machine status word instruction (SMSW).

X86: Implement the load machine status word instruction (LMSW).

X86: Fix the mov to segment selector in real mode instruction microcode.

X86: Implement the INIT IPI.

Merge ARM into the head. ARM will compile but may not actually work.

X86: Implement shrd.

X86: Set address size to 64 bits when generating addresses internally.

X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

X86: Compute shift instruction flags correctly.

X86: Implement IST stack switching.

X86: Implement the lldt instruction.

X86: Make rdcr use merge and the mov to control register instructions use the right operand size.

X86: Implement CLTS.

X86: Make the segment register reading microops use merge.

X86: Implement the mov to debug register intructions.

X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.

X86: Fix a few bugs with the segment register instructions in real mode.
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.

X86: Do a merge for the zero extension microop.

X86: Implement a basic prefetch instruction.

X86: Update CS later so stack accesses have the right permission checks.

X86: Use atCPL0 for accesses that are part of CPU machinery.

X86: Move where CS is set so CPL checks work out.

X86: Implement the sysret instruction in long mode.

X86: Implement the longmode versions of the syscall instruction.

X86: Make exceptions handle stack switching.

X86: Implement the LTR instruction.

X86: All x86 fault classes now attempt to do something useful.

X86: Make the long mode interrupt/exception microcode handle an error code.

X86: Make the chks microop check for the right int descriptor type.

X86: Touch up the interrupt entering microcode.

X86: Fix the microcode for the LODS instruction.

X86: Implement the xadd instruction.

X86: Implement the bswap instruction.

X86: Fix a bug in the iret microcode.

X86: Fix the segment setting code in IRET, and make it restore the flags.

X86: Implement the swapgs instruction.

X86: Implement entering an interrupt in microcode.

X86: Create a SeqOp class of microops and make Br one of them.

X86: Implement CPUID with a magical function instead of microcode.

X86: Make far ret modify CS instead of some random selector.

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs

X86: Fix the microcode for sign/zero extending moves that use high byte registers.

X86: Make the cpuid processor identifier return a real string.

X86: Implement and hook up STI and CLI instructions.

X86: Implement a partial, sort of correct version of the protected mode variant of iret.

X86: Change how segment loading is performed.

X86: Make pushes and pops use the stack size instead of the data size.

X86: Add microops and supporting code to manipulate the whole rflags register.

X86: Redo BSF.

X86: Make string instructions work when rcx=0.

X86: Bypass unaligned access support for register addressed MSRs.

X86: Fix the implementation of BSF.

X86: Bit scan forward/reverse were accidentally transposed.

X86: Fix a byte register indexing issue in the sign extending move from memory microcode.

X86: Add in some support for the tsc register.

X86: Implement the INVLPG instruction and the TIA microop.

X86: Optomize the bit scanning instruction microassembly a little. More can be done.

X86: Implement and attach the BSR and BSF instructions.

X86: Fill out group17 in the decoder.

X86: Redo the bit test instructions.

X86: Fix the wrmsr instruction.

X86: Fix the general IO instructions dataSize.

X86: Please excuse my dear Aunt Sally. (precedence bug)

X86: Make sure the memory index is calculated using the address size for bit test instructions.

X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register.

X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.

X86: Fix a copy paste error in the bts microcode.

X86: Implement mov from control register.

X86: First crack at far returns. This is grossly approximate.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the LIDT instruction.

X86: Implement the lgdt instruction.

X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement.

X86: Implement the wrcr microop which writes a control register, and some control register work.

X86: Implement some bit testing instructions.

X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.

X86: Use the cda microop where appropriate. The ENTER instruction still needs these.

X86: Start using the stupd microop, and update statistics accordingly.

X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER.

X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions.

X86: Impelement the HLT instruction and fix the "halt" microop.

X86: Implement the ENTER instruction. This could probably be optimized by cleaning up the indexing in the main loop.

X86: Implement the string IO instructions, ins and outs.

X86: Implement the undocumented SALC instruction which sets AL to 0xFF if CF=1 and 0x00 otherwise.

X86: Implement the XLAT instruction.

X86: Implement the BOUND instruction.

X86: Implement the in/out instructions. These will still need support from the TLB and memory system.

X86: Implement the LOOP instructions.

X86: Implemented the jrcx instruction.

X86: Added some new versions of MOV and a new argument type tag.

X86: Implemented LODS.

X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.

X86: Distinguish between the rep and repe prefixes.
STOS and MOVS only accept the rep prefix which always loops until rcx becomes
0. The other string instructions accept repe (same encoding as rep) and repne
which also check the condition code flags each iteration.

X86: Fix places where movfp was used incorrectly.

X86: Fix x87 floating point stack register indexing.

X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

X86: Fix up the microcode for the FST and FSTP instructions.

X86: Add classes for the actual x86 faults.

X86: Implement MOVS

X86: Implement STOS.

X86: Implement the fld, fst, and fstp instructions.

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.

X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code.

X86: Total overhaul of the division instructions and microops.

X86: Rework the multiplication microops so that they work like they would in the patent.

X86: Make signed multiplication do something different from unsigned.

X86: Add a square root microop and the SSE sqrt instruction.

X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.

X86: Implement an SSE xor microop and instruction.

X86: Hook in the fp arithmetic instructions. Stale python made it work before.

X86: Implement some SSE fp microops and instructions.

X86: Add some SSE floating point/integer conversion microops.

X86: Fix a typo in the microassembly for the cqo instruction.

X86: Implement idiv and propogate the mul corner case fix.

X86: Fix a corner case where mul would overwrite an original register value it still needed.

X86: Implement the movaps instruction.

X86: Implement the movsd instruction.

X86: Implement the movlpd instruction.

X86: Return values for some cpuid functions that match what my development machine returns.

X86: Make the microassembler accept lines which are just labels.
The labels on these lines will be associated with whatever the next microop
is.

X86: Make cpuid actually consider the eax parameter and return different values.

X86: Implement cmps (string compare)

X86: Make shift instructions set some of the flags they're supposed to.
The flag mechanism for microops needs to be fleshd out a little more to allow
for custom flag calculation methods for certain microops. Shift is an example
where the rules for calculating OF and CF are unique.

X86: Implemented and hooked in SCAS (scan string)
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.

X86: Implement microops and instructions that manipulate the flags register.

X86: Implement the cmpxchg instruction.

X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

X86: Add the arch_prctl system call and fix up some microcoding.
The arch_prctl system call is used to set and get the FS and GS segment
bases. The FS segment is use for TLS, so glibc needs to be able to set it
up.

X86: Set up RIP relative LEA instructions operands correctly.

X86: Implement unsigned divide. The non-byte version ignores rdx which it shouldn't.

X86: Implement a stub CPUID function which is hardcode to return certain values.

X86: Force jumps to use 64 bit operand size.

X86: Make instructions use pick, and implement/adjust some multiplication microops and instructions.

X86: Implement LEAVE

X86: Make logic instructions flag setting work.
The instructions now ask for the appropriate flags to be set, and the microops do the "right thing" with the CF and OF flags, namely zero them.

X86: Make arithmetic instructions set the appropriate flags.

X86: Fix popa and push with the stack pointer.
POPA used st instead of ld, and it didn't skip rsp. push rsp needs to store the -original- value of the stack pointer.

X86: Fix pc relative versions of add and subtract.

X86: Implement rotate-by-one instructions, and make register rotates use registers.

X86: Implement shift-by-one instructions, and make register shifts use registers.

Implement NOT

Fix immediate shifts. Implement register shifts.

Fix immediate rotates and add register ones.

Clean out part of an old comment.

Implement cmov.

Implement cdqe and cqo, which are also called cbw and cwde, and cwd and cdq respectively, depending on the operand size.

Implement setcc.

Get rid of an old comment.

Get rid of an old comment

Implement pusha, popa, three operand imul, hook them into the decoder, and clean up the decoder a little.

Make the operand size reflect the size specifier on the operand tags, and implement NEG

Implemented and hooked in xchg, rotate with carry, and ret instructions