History log of /gem5/src/arch/sparc/solaris/
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14024:abe47b13653d 02-May-2019 Gabe Black <gabeblack@google.com>

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

These two functions were performing the same function but had two
different names for historical reasons. This change merges them
together, keeping the getVirtProxy name to be consistent with the
getPhysProxy method used to get a non-translating proxy port.

Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

14014:ce216ee5d886 21-May-2019 Ciro Santilli <ciro.santilli@arm.com>

sim-se: add a release parameter to Process.py

Set the default release to that single value for all ISAs.

glibc has checks for the kernel version based on uname, and refuses
to start any syscall emulation programs if those checks don't pass with
error:

FATAL: kernel too old

The ideal solution to this problem is to actually implement all missing
system calls for the required kernel version and bumping the release
accordingly.

However, it is very hard to implement all missing syscalls and verify
compliance.

Previously, we have simply bumped the version manually from time to
time when major glibc versions started breaking.

This commit alleviates the problem in two ways.

Firstly, having a single kernel version for all versions means that it is
easier to bump all versions at once.

Secondly, it makes it is possible to set the release with a parameter,
which in turn can be set from the command line with:

se.py --param 'system.cpu[:].workload[:].release = "4.18.0"'

Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13995:5d459168a680 28-Aug-2018 Brandon Potter <brandon.potter@amd.com>

sim-se: change syscall function signature

The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.

With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.

This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.

Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13988:d579f9c76531 03-May-2019 Gabe Black <gabeblack@google.com>

sparc: Add an object file loader for linux and solaris.

Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13570:b6484720c6a9 18-Apr-2018 Brandon Potter <brandon.potter@amd.com>

sim-se: add syscalls related to polling

Fix poll so that it will use the syscall retry capability
instead of causing a blocking call.

Add the accept and wait4 system calls.

Add polling to read to remove deadlocks that occur in the
event queue that are caused by blocking system calls.

Modify the write system call to return an error number in
case of error.

Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da
Reviewed-on: https://gem5-review.googlesource.com/c/12115
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

11851:824055fe6b30 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.


/gem5/configs/common/cpu2000.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/se.py
/gem5/configs/learning_gem5/part1/simple.py
/gem5/configs/learning_gem5/part1/two_level.py
/gem5/configs/splash2/cluster.py
/gem5/configs/splash2/run.py
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/process.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/freebsd/process.cc
/gem5/src/arch/arm/freebsd/process.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/riscv/linux/process.cc
/gem5/src/arch/riscv/linux/process.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
process.cc
process.hh
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/kern/freebsd/freebsd.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/operatingsystem.hh
/gem5/src/sim/Process.py
/gem5/src/sim/emul_driver.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/syscall_desc.cc
/gem5/src/sim/syscall_desc.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/tests/long/se/10.mcf/test.py
/gem5/tests/long/se/20.parser/test.py
/gem5/tests/long/se/30.eon/test.py
/gem5/tests/long/se/40.perlbmk/test.py
/gem5/tests/long/se/50.vortex/test.py
/gem5/tests/long/se/60.bzip2/test.py
/gem5/tests/long/se/70.twolf/test.py
/gem5/tests/quick/se/00.hello.mp/test.py
/gem5/tests/quick/se/00.hello/test.py
/gem5/tests/quick/se/01.hello-2T-smt/test.py
/gem5/tests/quick/se/02.insttest/test.py
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/10.mcf/test.py
/gem5/tests/quick/se/30.eon/test.py
/gem5/tests/quick/se/40.m5threads-test-atomic/test.py
/gem5/tests/quick/se/50.vortex/test.py
/gem5/tests/quick/se/70.twolf/test.py
11794:97eebddaae84 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc

The class was crammed into syscall_emul.hh which has tons of forward
declarations and template definitions. To clean it up a bit, moved the
class into separate files and commented the class with doxygen style
comments. Also, provided some encapsulation by adding some accessors and
a mutator.

The syscallreturn.hh file was renamed syscall_return.hh to make it consistent
with other similarly named files in the src/sim directory.

The DPRINTF_SYSCALL macro was moved into its own header file with the
include the Base and Verbose flags as well.

11793:ef606668d247 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

style: [patch 1/22] use /r/3648/ to reorganize includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/idle_event.cc
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/isa.cc
/gem5/src/arch/alpha/kernel_stats.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/pagetable.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/pseudo.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/kvm/base_cpu.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/generic/decode_cache.cc
/gem5/src/arch/generic/mmapped_ipr.cc
/gem5/src/arch/generic/pseudo_inst.cc
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/remote_gdb.cc
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/power/insts/branch.cc
/gem5/src/arch/power/insts/mem.cc
/gem5/src/arch/power/insts/static_inst.cc
/gem5/src/arch/power/isa.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/pagetable.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/stacktrace.cc
/gem5/src/arch/power/tlb.cc
/gem5/src/arch/power/utility.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/isa.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/pagetable.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/remote_gdb.cc
process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/e820.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/decoder.cc
/gem5/src/arch/x86/emulenv.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/insts/microop.cc
/gem5/src/arch/x86/insts/microregop.cc
/gem5/src/arch/x86/insts/static_inst.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/isa.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/pseudo_inst.cc
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/types.cc
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/vtophys.cc
/gem5/src/base/atomicio.cc
/gem5/src/base/bigint.cc
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cprintf.cc
/gem5/src/base/debug.cc
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.cc
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/dtb_object.cc
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/raw_object.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/match.cc
/gem5/src/base/misc.cc
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/random.cc
/gem5/src/base/remote_gdb.cc
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/str.cc
/gem5/src/base/time.cc
/gem5/src/base/trace.cc
/gem5/src/base/vnc/vncinput.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/cpu/activity.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/dummy_checker.cc
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.cc
/gem5/src/cpu/inteltrace.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/kvm/base.cc
/gem5/src/cpu/kvm/perfevent.cc
/gem5/src/cpu/kvm/timer.cc
/gem5/src/cpu/kvm/vm.cc
/gem5/src/cpu/kvm/x86_cpu.cc
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/checker.cc
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/deriv.cc
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.cc
/gem5/src/cpu/o3/probe/simple_trace.cc
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/scoreboard.cc
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pred/2bit_local.cc
/gem5/src/cpu/pred/bi_mode.cc
/gem5/src/cpu/pred/btb.cc
/gem5/src/cpu/pred/tournament.cc
/gem5/src/cpu/profile.cc
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/probes/simpoint.cc
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/timing_expr.cc
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/alpha/tsunami.cc
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/alpha/tsunami_io.cc
/gem5/src/dev/arm/a9scu.cc
/gem5/src/dev/arm/amba_device.cc
/gem5/src/dev/arm/amba_fake.cc
/gem5/src/dev/arm/energy_ctrl.cc
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/hdlcd.cc
/gem5/src/dev/arm/kmi.cc
/gem5/src/dev/arm/pl011.cc
/gem5/src/dev/arm/pl111.cc
/gem5/src/dev/arm/realview.cc
/gem5/src/dev/arm/rtc_pl031.cc
/gem5/src/dev/arm/timer_cpulocal.cc
/gem5/src/dev/arm/timer_sp804.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/baddev.cc
/gem5/src/dev/intel_8254_timer.cc
/gem5/src/dev/io_device.cc
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/mc146818.cc
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/pci/device.cc
/gem5/src/dev/pci/host.cc
/gem5/src/dev/platform.cc
/gem5/src/dev/ps2.cc
/gem5/src/dev/ps2.hh
/gem5/src/dev/sparc/dtod.cc
/gem5/src/dev/sparc/iob.cc
/gem5/src/dev/sparc/mm_disk.cc
/gem5/src/dev/sparc/t1000.cc
/gem5/src/dev/uart.cc
/gem5/src/dev/uart8250.cc
/gem5/src/dev/virtio/base.cc
/gem5/src/dev/virtio/block.cc
/gem5/src/dev/virtio/console.cc
/gem5/src/dev/virtio/fs9p.cc
/gem5/src/dev/virtio/pci.cc
/gem5/src/dev/x86/cmos.cc
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i82094aa.cc
/gem5/src/dev/x86/i8237.cc
/gem5/src/dev/x86/i8254.cc
/gem5/src/dev/x86/i8259.cc
/gem5/src/dev/x86/pc.cc
/gem5/src/dev/x86/south_bridge.cc
/gem5/src/dev/x86/speaker.cc
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/system_events.cc
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/bridge.cc
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/queued.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/coherent_xbar.cc
/gem5/src/mem/comm_monitor.cc
/gem5/src/mem/dram_ctrl.cc
/gem5/src/mem/drampower.cc
/gem5/src/mem/dramsim2.cc
/gem5/src/mem/dramsim2_wrapper.cc
/gem5/src/mem/external_master.cc
/gem5/src/mem/external_slave.cc
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/hmc_controller.cc
/gem5/src/mem/mem_checker.cc
/gem5/src/mem/mem_checker_monitor.cc
/gem5/src/mem/noncoherent_xbar.cc
/gem5/src/mem/packet.cc
/gem5/src/mem/packet_queue.cc
/gem5/src/mem/page_table.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/port.cc
/gem5/src/mem/port_proxy.cc
/gem5/src/mem/probes/base.cc
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/NetDest.cc
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/filters/BlockBloomFilter.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/LSB_CountingBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiGrainBloomFilter.cc
/gem5/src/mem/ruby/filters/NonCountingBloomFilter.cc
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/Prefetcher.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/WireBuffer.cc
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/serial_link.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/snoop_filter.cc
/gem5/src/mem/tport.cc
/gem5/src/mem/xbar.cc
/gem5/src/proto/protoio.cc
/gem5/src/python/swig/pyevent.cc
/gem5/src/python/swig/pyevent.hh
/gem5/src/python/swig/pyobject.cc
/gem5/src/sim/arguments.cc
/gem5/src/sim/backtrace_glibc.cc
/gem5/src/sim/clock_domain.cc
/gem5/src/sim/core.cc
/gem5/src/sim/cxx_manager.cc
/gem5/src/sim/debug.cc
/gem5/src/sim/dvfs_handler.cc
/gem5/src/sim/faults.cc
/gem5/src/sim/init.cc
/gem5/src/sim/probe/probe.cc
/gem5/src/sim/process.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/py_interact.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_object.cc
/gem5/src/sim/simulate.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/sub_system.cc
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/system.cc
/gem5/src/sim/voltage_domain.cc
/gem5/src/unittest/circlebuf.cc
/gem5/src/unittest/unittest.cc
11383:5ac090acd180 17-Mar-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.

11381:516213d2f0cf 17-Mar-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.

8706:b1838faf3bcc 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


/gem5/configs/common/FSConfig.py
/gem5/configs/example/se.py
/gem5/configs/ruby/Ruby.py
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/SConscript
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/port.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/port_proxy.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPortProxy.cc
/gem5/src/mem/ruby/system/RubyPortProxy.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/arguments.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8600:b0d7c64ada19 23-Oct-2011 Steve Reinhardt <steve.reinhardt@amd.com>

syscall_emul: implement MAP_FIXED option to mmap()

8229:78bf55f23338 15-Apr-2011 Nathan Binkert <nate@binkert.org>

includes: sort all includes


/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/mt.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/linux/atag.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/predecoder.hh
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/vtophys.hh
/gem5/src/arch/generic/debugfaults.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/isa.cc
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.hh
/gem5/src/arch/power/insts/floating.hh
/gem5/src/arch/power/insts/integer.hh
/gem5/src/arch/power/isa/includes.isa
/gem5/src/arch/power/linux/linux.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.hh
/gem5/src/arch/power/tlb.hh
/gem5/src/arch/power/vtophys.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/locked_mem.hh
/gem5/src/arch/sparc/mmapped_ipr.hh
/gem5/src/arch/sparc/nativetrace.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/remote_gdb.hh
process.cc
solaris.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/tlb_map.hh
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/acpi.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/faults.hh
/gem5/src/arch/x86/insts/badmicroop.cc
/gem5/src/arch/x86/insts/macroop.hh
/gem5/src/arch/x86/insts/microfpop.cc
/gem5/src/arch/x86/insts/microldstop.cc
/gem5/src/arch/x86/insts/micromediaop.cc
/gem5/src/arch/x86/interrupts.cc
/gem5/src/arch/x86/interrupts.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/linux/linux.cc
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/linux/system.hh
/gem5/src/arch/x86/microcode_rom.hh
/gem5/src/arch/x86/nativetrace.cc
/gem5/src/arch/x86/pagetable_walker.cc
/gem5/src/arch/x86/pagetable_walker.hh
/gem5/src/arch/x86/predecoder.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/arch/x86/system.cc
/gem5/src/arch/x86/tlb.cc
/gem5/src/arch/x86/tlb.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/debug.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/fenv.c
/gem5/src/base/hostinfo.cc
/gem5/src/base/inet.hh
/gem5/src/base/inifile.cc
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/symtab.cc
/gem5/src/base/misc.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/range_map.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/base/socket.cc
/gem5/src/base/statistics.cc
/gem5/src/base/statistics.hh
/gem5/src/base/stats/info.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/stats/output.cc
/gem5/src/base/stats/text.cc
/gem5/src/base/stats/text.hh
/gem5/src/base/str.hh
/gem5/src/base/time.hh
/gem5/src/base/trace.cc
/gem5/src/base/vnc/convert.cc
/gem5/src/base/vnc/vncserver.cc
/gem5/src/base/vnc/vncserver.hh
/gem5/src/cpu/activity.cc
/gem5/src/cpu/activity.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/func_unit.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/first_stage.cc
/gem5/src/cpu/inorder/first_stage.hh
/gem5/src/cpu/inorder/inorder_cpu_builder.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.cc
/gem5/src/cpu/inorder/inorder_dyn_inst.hh
/gem5/src/cpu/inorder/inorder_trace.cc
/gem5/src/cpu/inorder/pipeline_stage.cc
/gem5/src/cpu/inorder/pipeline_stage.hh
/gem5/src/cpu/inorder/pipeline_traits.5stage.cc
/gem5/src/cpu/inorder/pipeline_traits.5stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.hh
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.cc
/gem5/src/cpu/inorder/pipeline_traits.9stage.smt2.hh
/gem5/src/cpu/inorder/pipeline_traits.hh
/gem5/src/cpu/inorder/reg_dep_map.cc
/gem5/src/cpu/inorder/resource.cc
/gem5/src/cpu/inorder/resource.hh
/gem5/src/cpu/inorder/resource_pool.9stage.cc
/gem5/src/cpu/inorder/resource_pool.cc
/gem5/src/cpu/inorder/resource_pool.hh
/gem5/src/cpu/inorder/resource_sked.cc
/gem5/src/cpu/inorder/resource_sked.hh
/gem5/src/cpu/inorder/resources/agen_unit.hh
/gem5/src/cpu/inorder/resources/bpred_unit.hh
/gem5/src/cpu/inorder/resources/branch_predictor.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/resources/decode_unit.hh
/gem5/src/cpu/inorder/resources/execution_unit.cc
/gem5/src/cpu/inorder/resources/execution_unit.hh
/gem5/src/cpu/inorder/resources/fetch_seq_unit.hh
/gem5/src/cpu/inorder/resources/fetch_unit.cc
/gem5/src/cpu/inorder/resources/fetch_unit.hh
/gem5/src/cpu/inorder/resources/graduation_unit.hh
/gem5/src/cpu/inorder/resources/inst_buffer.cc
/gem5/src/cpu/inorder/resources/inst_buffer.hh
/gem5/src/cpu/inorder/resources/mem_dep_unit.hh
/gem5/src/cpu/inorder/resources/mult_div_unit.cc
/gem5/src/cpu/inorder/resources/mult_div_unit.hh
/gem5/src/cpu/inorder/resources/resource_list.hh
/gem5/src/cpu/inorder/resources/tlb_unit.cc
/gem5/src/cpu/inorder/resources/tlb_unit.hh
/gem5/src/cpu/inorder/resources/use_def.cc
/gem5/src/cpu/inorder/resources/use_def.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/inorder/thread_state.cc
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/nativetrace.hh
/gem5/src/cpu/o3/base_dyn_inst.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/fu_pool.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/isa_specific.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/thread_context.cc
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/back_end_impl.hh
/gem5/src/cpu/ozone/base_dyn_inst.cc
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue.cc
/gem5/src/cpu/ozone/inst_queue.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lsq_unit.cc
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_lsq.cc
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/ozone_base_dyn_inst.cc
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/rename_table.cc
/gem5/src/cpu/ozone/simple_base_dyn_inst.cc
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/gem5/src/mem/ruby/network/orion/Buffer/Buffer.cc
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/gem5/src/mem/ruby/network/orion/TechParameter.cc
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/gem5/util/ccdrv/devtime.c
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/gem5/util/statetrace/arch/arm/tracechild.cc
/gem5/util/statetrace/arch/arm/tracechild.hh
/gem5/util/statetrace/arch/i686/tracechild.cc
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/gem5/util/term/term.c
6701:4842482e1bd1 30-Oct-2009 Gabe Black <gblack@eecs.umich.edu>

Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.

6329:5d8b91875859 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.


/gem5/src/arch/SConscript
/gem5/src/arch/alpha/SConscript
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/regfile.cc
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/registers.hh
/gem5/src/arch/alpha/regredir.hh
/gem5/src/arch/alpha/types.hh
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/misc_regfile.hh
/gem5/src/arch/arm/regfile.cc
/gem5/src/arch/arm/regfile.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/regfile.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/SConscript
/gem5/src/arch/sparc/isa/includes.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/miscregs.hh
/gem5/src/arch/sparc/regfile.cc
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/registers.hh
process.cc
/gem5/src/arch/sparc/types.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/x86/SConscript
/gem5/src/arch/x86/emulenv.hh
/gem5/src/arch/x86/isa/includes.isa
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/miscregfile.hh
/gem5/src/arch/x86/regfile.cc
/gem5/src/arch/x86/regfile.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/arch/x86/types.hh
/gem5/src/arch/x86/utility.cc
/gem5/src/arch/x86/utility.hh
/gem5/src/cpu/legiontrace.cc
/gem5/src/cpu/nativetrace.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/mem/physical.cc
/gem5/src/sim/process.hh
5981:5e7899a2692f 28-Feb-2009 Steve Reinhardt <stever@gmail.com>

Fix Num_Syscall_Descs check bug in non-x86 ISAs.
(See cset d35d2b28df38 for x86 fix.)

5958:2d9737bf3c2f 27-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

Processes: Make getting and setting system call arguments part of a process object.


/gem5/src/arch/SConscript
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/syscallreturn.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/syscallreturn.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
process.cc
/gem5/src/arch/sparc/syscallreturn.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/x86/isa_traits.hh
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/arch/x86/syscallreturn.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
5748:f28f020f3006 15-Nov-2008 Steve Reinhardt <Steve.Reinhardt@amd.com>

syscalls: fix latent brk/obreak bug.
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.

5543:3af77710f397 10-Sep-2008 Ali Saidi <saidi@eecs.umich.edu>

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs


/gem5/configs/common/Benchmarks.py
/gem5/src/arch/alpha/aout_machdep.h
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/floatregfile.hh
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/ipr.hh
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/osfpal.cc
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/tru64.cc
/gem5/src/arch/alpha/tru64/tru64.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/isa_specific.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/remote_gdb.cc
solaris.cc
solaris.hh
/gem5/src/arch/sparc/sparc_traits.hh
/gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
/gem5/src/arch/x86/isa/insts/general_purpose/semaphores.py
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/linux/linux.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/base/bitunion.hh
/gem5/src/base/crc.cc
/gem5/src/base/fast_alloc.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/inifile.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/coff_sym.h
/gem5/src/base/loader/coff_symconst.h
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/res_list.hh
/gem5/src/base/stats/flags.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/time.hh
/gem5/src/base/trace.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/alpha/dyn_inst.hh
/gem5/src/cpu/o3/mips/dyn_inst.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/access.h
/gem5/src/dev/etherdump.cc
/gem5/src/dev/mips/access.h
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcireg.h
/gem5/src/dev/sinicreg.hh
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.hh
/gem5/src/kern/solaris/solaris.hh
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_syscalls.cc
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/dram.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/async.hh
/gem5/src/sim/debug.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/process.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/util/m5/m5op_alpha.S
/gem5/util/m5/m5ops.h
/gem5/util/term/term.c
5513:8631b29873a2 23-Jul-2008 Michael Adler <Michael.Adler@intel.com>

syscalls: Add a bunch of missing system calls.
readlink, umask, truncate, ftruncate, mkdir, and getcwd.

5154:7e6431213487 16-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.

5128:69fb816fa927 04-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

SPARC: Make software trap 3 flush the register windows like the ABI specifies.

3669:3607aaed36b6 16-Nov-2006 Nathan Binkert <binkertn@umich.edu>

Implement current working directory for LiveProcesses

3114:7a4771b9b720 17-Sep-2006 Gabe Black <gblack@eecs.umich.edu>

Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.

src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.

2980:eab855f06b79 15-Aug-2006 Gabe Black <gblack@eecs.umich.edu>

Cleaned up include files and got rid of many using directives in header files.


/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/util.isa
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/process.hh
solaris.cc
/gem5/src/arch/sparc/syscallreturn.hh
/gem5/src/cpu/base_dyn_inst_impl.hh
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/alpha/cpu.hh
/gem5/src/cpu/o3/alpha/cpu_impl.hh
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/mips/cpu.hh
/gem5/src/cpu/o3/mips/cpu_impl.hh
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/scoreboard.hh
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/dyn_inst.hh
/gem5/src/cpu/ozone/dyn_inst_impl.hh
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/lsq_unit.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/null_predictor.hh
/gem5/src/cpu/ozone/ozone_impl.hh
/gem5/src/cpu/ozone/simple_impl.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/miss/blocking_buffer.cc
/gem5/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/request.hh
/gem5/src/sim/pseudo_inst.hh
2680:246e7104f744 06-Jun-2006 Kevin Lim <ktlim@umich.edu>

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
Change ExecContext to ThreadContext.


/gem5/src/arch/alpha/arguments.cc
/gem5/src/arch/alpha/arguments.hh
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/freebsd/system.hh
/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tlb.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/tru64/system.hh
/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa_traits.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/regfile.hh
process.cc
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/sparc/vtophys.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.cc
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/exec_context.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpuevent.cc
/gem5/src/cpu/cpuevent.hh
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/quiesce_event.cc
/gem5/src/cpu/quiesce_event.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/alpha_console.cc
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/sinic.cc
/gem5/src/dev/tsunami_cchip.cc
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/events.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/system_events.hh
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/kern/tru64/tru64_events.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
2665:a124942bacb8 31-May-2006 Ali Saidi <saidi@eecs.umich.edu>

Updated Authors from bk prs info


/gem5/SConstruct
/gem5/docs/stl.hh
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/alpha/SConscript
/gem5/src/arch/alpha/aout_machdep.h
/gem5/src/arch/alpha/arguments.cc
/gem5/src/arch/alpha/arguments.hh
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/ev5.hh
/gem5/src/arch/alpha/faults.cc
/gem5/src/arch/alpha/faults.hh
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/freebsd/system.hh
/gem5/src/arch/alpha/isa/branch.isa
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/fp.isa
/gem5/src/arch/alpha/isa/int.isa
/gem5/src/arch/alpha/isa/main.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa/opcdec.isa
/gem5/src/arch/alpha/isa/pal.isa
/gem5/src/arch/alpha/isa/unimp.isa
/gem5/src/arch/alpha/isa/unknown.isa
/gem5/src/arch/alpha/isa/util.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/aligned.hh
/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/process.hh
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/thread_info.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/osfpal.cc
/gem5/src/arch/alpha/osfpal.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/stacktrace.hh
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tlb.cc
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/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/process.hh
/gem5/src/arch/alpha/tru64/system.cc
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/gem5/src/arch/alpha/tru64/tru64.cc
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/gem5/src/arch/alpha/utility.hh
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/isa_specific.hh
/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/isa/main.isa
/gem5/src/arch/mips/isa_traits.cc
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/process.cc
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/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/sparc/SConscript
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/isa/main.isa
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
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/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/regfile.hh
process.cc
process.hh
solaris.cc
solaris.hh
/gem5/src/arch/sparc/stacktrace.hh
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/arch/sparc/utility.hh
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/sparc/vtophys.hh
/gem5/src/base/bitfield.hh
/gem5/src/base/callback.hh
/gem5/src/base/chunk_generator.hh
/gem5/src/base/circlebuf.cc
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/gem5/src/base/compression/lzss_compression.cc
/gem5/src/base/compression/lzss_compression.hh
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/gem5/src/base/cprintf.hh
/gem5/src/base/cprintf_formats.hh
/gem5/src/base/crc.hh
/gem5/src/base/date.cc
/gem5/src/base/dbl_list.hh
/gem5/src/base/endian.hh
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/gem5/src/base/inet.cc
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/gem5/src/base/intmath.cc
/gem5/src/base/intmath.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/aout_object.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/ecoff_object.hh
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.cc
/gem5/src/base/loader/symtab.hh
/gem5/src/base/match.cc
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/gem5/src/base/misc.cc
/gem5/src/base/misc.hh
/gem5/src/base/mod_num.hh
/gem5/src/base/mysql.cc
/gem5/src/base/mysql.hh
/gem5/src/base/output.cc
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/gem5/src/base/pollevent.cc
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/gem5/src/base/random.cc
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/gem5/src/base/sat_counter.cc
/gem5/src/base/sat_counter.hh
/gem5/src/base/sched_list.hh
/gem5/src/base/socket.cc
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/gem5/src/base/stats/events.cc
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/gem5/src/base/stats/mysql.cc
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/gem5/src/base/str.cc
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/gem5/src/base/time.cc
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/gem5/src/base/trace.cc
/gem5/src/base/trace.hh
/gem5/src/base/traceflags.py
/gem5/src/base/userinfo.cc
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/gem5/src/cpu/SConscript
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.cc
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/cpu_exec_context.cc
/gem5/src/cpu/cpu_exec_context.hh
/gem5/src/cpu/cpu_models.py
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/gem5/src/cpu/exetrace.cc
/gem5/src/cpu/exetrace.hh
/gem5/src/cpu/inst_seq.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/2bit_local_pred.cc
/gem5/src/cpu/o3/2bit_local_pred.hh
/gem5/src/cpu/o3/alpha_cpu.cc
/gem5/src/cpu/o3/alpha_cpu.hh
/gem5/src/cpu/o3/alpha_cpu_builder.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/o3/alpha_dyn_inst.cc
/gem5/src/cpu/o3/alpha_dyn_inst.hh
/gem5/src/cpu/o3/alpha_dyn_inst_impl.hh
/gem5/src/cpu/o3/alpha_impl.hh
/gem5/src/cpu/o3/alpha_params.hh
/gem5/src/cpu/o3/bpred_unit.cc
/gem5/src/cpu/o3/bpred_unit.hh
/gem5/src/cpu/o3/bpred_unit_impl.hh
/gem5/src/cpu/o3/btb.cc
/gem5/src/cpu/o3/btb.hh
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/commit.cc
/gem5/src/cpu/o3/commit.hh
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/cpu_policy.hh
/gem5/src/cpu/o3/decode.cc
/gem5/src/cpu/o3/decode.hh
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/o3/fetch.cc
/gem5/src/cpu/o3/fetch.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/free_list.cc
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/iew.cc
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.cc
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/mem_dep_unit.cc
/gem5/src/cpu/o3/mem_dep_unit.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/ras.cc
/gem5/src/cpu/o3/ras.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.cc
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/rob.cc
/gem5/src/cpu/o3/rob.hh
/gem5/src/cpu/o3/rob_impl.hh
/gem5/src/cpu/o3/sat_counter.cc
/gem5/src/cpu/o3/sat_counter.hh
/gem5/src/cpu/o3/store_set.cc
/gem5/src/cpu/o3/store_set.hh
/gem5/src/cpu/o3/tournament_pred.cc
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/op_class.cc
/gem5/src/cpu/op_class.hh
/gem5/src/cpu/ozone/cpu.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/ea_list.cc
/gem5/src/cpu/ozone/ea_list.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/pc_event.hh
/gem5/src/cpu/profile.cc
/gem5/src/cpu/profile.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/smt.hh
/gem5/src/cpu/static_inst.cc
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/opt_cpu.hh
/gem5/src/cpu/trace/reader/ibm_reader.cc
/gem5/src/cpu/trace/reader/ibm_reader.hh
/gem5/src/cpu/trace/reader/itx_reader.cc
/gem5/src/cpu/trace/reader/itx_reader.hh
/gem5/src/cpu/trace/reader/m5_reader.cc
/gem5/src/cpu/trace/reader/m5_reader.hh
/gem5/src/cpu/trace/reader/mem_trace_reader.cc
/gem5/src/cpu/trace/reader/mem_trace_reader.hh
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/cpu/trace/trace_cpu.hh
/gem5/src/dev/alpha_access.h
/gem5/src/dev/alpha_console.cc
/gem5/src/dev/alpha_console.hh
/gem5/src/dev/baddev.cc
/gem5/src/dev/baddev.hh
/gem5/src/dev/disk_image.cc
/gem5/src/dev/disk_image.hh
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherbus.hh
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherdump.hh
/gem5/src/dev/etherint.cc
/gem5/src/dev/etherint.hh
/gem5/src/dev/etherlink.cc
/gem5/src/dev/etherlink.hh
/gem5/src/dev/etherpkt.cc
/gem5/src/dev/etherpkt.hh
/gem5/src/dev/ethertap.cc
/gem5/src/dev/ethertap.hh
/gem5/src/dev/ide_ctrl.cc
/gem5/src/dev/ide_ctrl.hh
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/ide_disk.hh
/gem5/src/dev/io_device.cc
/gem5/src/dev/io_device.hh
/gem5/src/dev/isa_fake.cc
/gem5/src/dev/isa_fake.hh
/gem5/src/dev/ns_gige.cc
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/ns_gige_reg.h
/gem5/src/dev/pciconfigall.cc
/gem5/src/dev/pciconfigall.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcidev.hh
/gem5/src/dev/pcireg.h
/gem5/src/dev/pitreg.h
/gem5/src/dev/pktfifo.cc
/gem5/src/dev/pktfifo.hh
/gem5/src/dev/platform.cc
/gem5/src/dev/platform.hh
/gem5/src/dev/rtcreg.h
/gem5/src/dev/simconsole.cc
/gem5/src/dev/simconsole.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/dev/simple_disk.hh
/gem5/src/dev/sinic.cc
/gem5/src/dev/sinic.hh
/gem5/src/dev/sinicreg.hh
/gem5/src/dev/tsunami.cc
/gem5/src/dev/tsunami.hh
/gem5/src/dev/tsunami_cchip.cc
/gem5/src/dev/tsunami_cchip.hh
/gem5/src/dev/tsunami_io.cc
/gem5/src/dev/tsunami_io.hh
/gem5/src/dev/tsunami_pchip.cc
/gem5/src/dev/tsunami_pchip.hh
/gem5/src/dev/tsunamireg.h
/gem5/src/dev/uart.cc
/gem5/src/dev/uart.hh
/gem5/src/dev/uart8250.cc
/gem5/src/dev/uart8250.hh
/gem5/src/kern/kernel_stats.cc
/gem5/src/kern/kernel_stats.hh
/gem5/src/kern/linux/events.cc
/gem5/src/kern/linux/events.hh
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/linux/linux_syscalls.cc
/gem5/src/kern/linux/linux_syscalls.hh
/gem5/src/kern/linux/printk.cc
/gem5/src/kern/linux/printk.hh
/gem5/src/kern/linux/sched.hh
/gem5/src/kern/solaris/solaris.hh
/gem5/src/kern/system_events.cc
/gem5/src/kern/system_events.hh
/gem5/src/kern/tru64/dump_mbuf.cc
/gem5/src/kern/tru64/dump_mbuf.hh
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/printf.cc
/gem5/src/kern/tru64/printf.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/kern/tru64/tru64_events.hh
/gem5/src/kern/tru64/tru64_syscalls.cc
/gem5/src/kern/tru64/tru64_syscalls.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bridge.hh
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
/gem5/src/mem/config/prefetch.hh
/gem5/src/mem/mem_object.cc
/gem5/src/mem/mem_object.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/page_table.cc
/gem5/src/mem/page_table.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/port.cc
/gem5/src/mem/port.hh
/gem5/src/mem/request.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/python/SConscript
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/config.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/multidict.py
/gem5/src/python/m5/smartdict.py
/gem5/src/sim/async.hh
/gem5/src/sim/builder.cc
/gem5/src/sim/builder.hh
/gem5/src/sim/byteswap.hh
/gem5/src/sim/debug.cc
/gem5/src/sim/debug.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/faults.cc
/gem5/src/sim/faults.hh
/gem5/src/sim/host.hh
/gem5/src/sim/main.cc
/gem5/src/sim/param.cc
/gem5/src/sim/param.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/sim_object.cc
/gem5/src/sim/sim_object.hh
/gem5/src/sim/startup.cc
/gem5/src/sim/startup.hh
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/stats.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/src/unittest/bitvectest.cc
/gem5/src/unittest/circletest.cc
/gem5/src/unittest/cprintftest.cc
/gem5/src/unittest/genini.py
/gem5/src/unittest/initest.cc
/gem5/src/unittest/lru_test.cc
/gem5/src/unittest/nmtest.cc
/gem5/src/unittest/offtest.cc
/gem5/src/unittest/paramtest.cc
/gem5/src/unittest/rangetest.cc
/gem5/src/unittest/sized_test.cc
/gem5/src/unittest/stattest.cc
/gem5/src/unittest/strnumtest.cc
/gem5/src/unittest/symtest.cc
/gem5/src/unittest/tokentest.cc
/gem5/src/unittest/tracetest.cc
/gem5/util/ccdrv/devtime.c
/gem5/util/m5/Makefile
/gem5/util/m5/m5.c
/gem5/util/m5/m5op.S
/gem5/util/m5/m5op.h
/gem5/util/oprofile-top.py
/gem5/util/qdo
/gem5/util/rundiff
/gem5/util/stats/db.py
/gem5/util/stats/dbinit.py
/gem5/util/stats/display.py
/gem5/util/stats/info.py
/gem5/util/stats/orderdict.py
/gem5/util/stats/print.py
/gem5/util/stats/profile.py
/gem5/util/stats/stats.py
/gem5/util/tap/tap.cc
2632:1bb2f91485ea 22-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.


/gem5/Doxyfile
/gem5/SConscript
/gem5/SConstruct
/gem5/arch/SConscript
/gem5/arch/alpha/SConscript
/gem5/arch/alpha/aout_machdep.h
/gem5/arch/alpha/arguments.cc
/gem5/arch/alpha/arguments.hh
/gem5/arch/alpha/ecoff_machdep.h
/gem5/arch/alpha/ev5.cc
/gem5/arch/alpha/ev5.hh
/gem5/arch/alpha/faults.cc
/gem5/arch/alpha/faults.hh
/gem5/arch/alpha/freebsd/system.cc
/gem5/arch/alpha/freebsd/system.hh
/gem5/arch/alpha/isa/branch.isa
/gem5/arch/alpha/isa/decoder.isa
/gem5/arch/alpha/isa/fp.isa
/gem5/arch/alpha/isa/int.isa
/gem5/arch/alpha/isa/main.isa
/gem5/arch/alpha/isa/mem.isa
/gem5/arch/alpha/isa/opcdec.isa
/gem5/arch/alpha/isa/pal.isa
/gem5/arch/alpha/isa/unimp.isa
/gem5/arch/alpha/isa/unknown.isa
/gem5/arch/alpha/isa/util.isa
/gem5/arch/alpha/isa_traits.hh
/gem5/arch/alpha/linux/aligned.hh
/gem5/arch/alpha/linux/hwrpb.hh
/gem5/arch/alpha/linux/linux.cc
/gem5/arch/alpha/linux/linux.hh
/gem5/arch/alpha/linux/process.cc
/gem5/arch/alpha/linux/process.hh
/gem5/arch/alpha/linux/system.cc
/gem5/arch/alpha/linux/system.hh
/gem5/arch/alpha/linux/thread_info.hh
/gem5/arch/alpha/linux/threadinfo.hh
/gem5/arch/alpha/osfpal.cc
/gem5/arch/alpha/osfpal.hh
/gem5/arch/alpha/process.cc
/gem5/arch/alpha/process.hh
/gem5/arch/alpha/regfile.hh
/gem5/arch/alpha/stacktrace.cc
/gem5/arch/alpha/stacktrace.hh
/gem5/arch/alpha/system.cc
/gem5/arch/alpha/system.hh
/gem5/arch/alpha/tlb.cc
/gem5/arch/alpha/tlb.hh
/gem5/arch/alpha/tru64/process.cc
/gem5/arch/alpha/tru64/process.hh
/gem5/arch/alpha/tru64/system.cc
/gem5/arch/alpha/tru64/system.hh
/gem5/arch/alpha/tru64/tru64.cc
/gem5/arch/alpha/tru64/tru64.hh
/gem5/arch/alpha/types.hh
/gem5/arch/alpha/utility.hh
/gem5/arch/alpha/vtophys.cc
/gem5/arch/alpha/vtophys.hh
/gem5/arch/isa_parser.py
/gem5/arch/isa_specific.hh
/gem5/arch/mips/SConscript
/gem5/arch/mips/faults.cc
/gem5/arch/mips/faults.hh
/gem5/arch/mips/isa/base.isa
/gem5/arch/mips/isa/bitfields.isa
/gem5/arch/mips/isa/decoder.isa
/gem5/arch/mips/isa/formats/basic.isa
/gem5/arch/mips/isa/formats/branch.isa
/gem5/arch/mips/isa/formats/formats.isa
/gem5/arch/mips/isa/formats/fp.isa
/gem5/arch/mips/isa/formats/int.isa
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