Cross Reference: /gem5/src/arch/riscv/bare

History log of /gem5/src/arch/riscv/bare_metal/
Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
12808:f275fd1244ce	13-Mar-2018	Robert <robert.scheffel1@tu-dresden.de>	arch-riscv: enable rudimentary fs simulation These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> /gem5/src/arch/riscv/RiscvSystem.py /gem5/src/arch/riscv/SConscript system.cc system.hh /gem5/src/arch/riscv/faults.cc /gem5/src/arch/riscv/faults.hh /gem5/src/arch/riscv/interrupts.hh /gem5/src/arch/riscv/system.cc /gem5/src/arch/riscv/system.hh /gem5/src/arch/riscv/tlb.cc /gem5/src/arch/riscv/utility.cc /gem5/src/arch/riscv/utility.hh