14024:abe47b13653d |
02-May-2019 |
Gabe Black <gabeblack@google.com> |
arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
These two functions were performing the same function but had two different names for historical reasons. This change merges them together, keeping the getVirtProxy name to be consistent with the getPhysProxy method used to get a non-translating proxy port.
Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
14014:ce216ee5d886 |
21-May-2019 |
Ciro Santilli <ciro.santilli@arm.com> |
sim-se: add a release parameter to Process.py
Set the default release to that single value for all ISAs.
glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error:
FATAL: kernel too old
The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly.
However, it is very hard to implement all missing syscalls and verify compliance.
Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking.
This commit alleviates the problem in two ways.
Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once.
Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with:
se.py --param 'system.cpu[:].workload[:].release = "4.18.0"'
Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> |
14010:0e1e887507c0 |
01-May-2019 |
Gabe Black <gabeblack@google.com> |
arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
13995:5d459168a680 |
28-Aug-2018 |
Brandon Potter <brandon.potter@amd.com> |
sim-se: change syscall function signature
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access.
With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error.
This patch removes the redundancy by forcing access through the ThreadContext field within each system call.
Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> |
13984:7200989d951c |
03-May-2019 |
Gabe Black <gabeblack@google.com> |
arm: Add an object file loader for linux and freebsd.
Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13678:1ad51de4cb42 |
24-Jan-2019 |
Ayaz Akram <yazakram@ucdavis.edu> |
sim-se: update the arm kernel version
This change is needed to run cpu tests with ARM binaries compiled with newer linux kernel headers
Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15855 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13570:b6484720c6a9 |
18-Apr-2018 |
Brandon Potter <brandon.potter@amd.com> |
sim-se: add syscalls related to polling
Fix poll so that it will use the syscall retry capability instead of causing a blocking call.
Add the accept and wait4 system calls.
Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls.
Modify the write system call to return an error number in case of error.
Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
13539:22b36f5a7a95 |
09-Jan-2019 |
Javier Setoain <javier.setoain@arm.com> |
sim-se, arch-arm: Add support for getdents64
Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15438 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
13538:642e19fa9db8 |
09-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arch-arm, sim-se: Add support for TLS in clone
Change-Id: I1f78dce05a48a2e3adfaf027cd38ab55507b9611 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15437 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13537:2441d9a15e3c |
09-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arch-arm, sim-se: Fix incorrect SP handling in clone
The clone syscall is currently broken on aarch64 since the aarch64 code uses an incorrect SP register. Fix this by storing the new stack pointer in SP_EL0 instead of R13.
Change-Id: Ie17990b4f359608e3b53e5bf625eca53769a6653 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15436 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13536:77e19417e723 |
09-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim-se: Refactor clone to avoid most ifdefs
Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation.
Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable.
Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13533:c19aabc6fe2b |
08-Jan-2019 |
Javier Setoain <javier.setoain@arm.com> |
arch-arm, sim-se: Wire up syscalls needed for pthreads
Change-Id: I8da5e3e0d7dc5d31ac82ed2045109d6d73cbf99d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15415 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
13370:f6f338f61b0f |
26-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
syscall_emul: implement arm openat
This is especially important because the Ubuntu 18.04 packaged arm-linux-gnueabihf-gcc uses the system call on the program initialization, which leads all programs to fail with:
fatal: syscall openat (#322) unimplemented.
Change-Id: I5596162ad19644df7b6d21f2a46acc07030001ae Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13004 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
13226:77114f781d94 |
25-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
syscall_emul: update arm uname release to 3.7.0+
Trying to compile an ARM C hello world with arm-linux-gnueabihf-gcc from Ubuntu 16.04 leads to a runtime failure with se.py:
FATAL: kernel too old
because the glibc tests if the kernel is at least 3.2.0, and gem5 was reporting 3.0.0.
Furthermore, it is hard to obtain such toolchain at all: for example crosstool-NG currently only allows for minimum kernels above 3.2.0.
3.7.0+ was chosen to match the aarch64 value, as it is likely that the level of support will be very similar.
This commit does not guarantee that full 3.7.0 is supported, but it is not likely that we had full 3.0.0 support previously either.
However, it is more likely that such support will be eventually achieved if users can at least try out their programs and implement the missing system calls as they are found.
Change-Id: I8df3763ae49788a6cb11cb0920e8202cd56b0f09 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12986 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
12515:e3d1a64d0260 |
05-Feb-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
sim: Remove _numContexts member in System class
A System object has a _numContexts member variable which represent the number of ThreadContext registered in the System. Since this has to match the size of the ThreadContext vector, this patch removes the manually cached size. This was usually used as a for-loop index, whereas we want to enforce the use of range-based loops whenever possible.
Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
12090:11d69759b378 |
04-Apr-2017 |
Paul Rosenfeld <prosenfeld@micron.com> |
arm,sim: fix context switch stats dumps for ARM64/Linux
32bit and 64bit Linux have different arguments passed to the __switch_to() function that gem5 hooks into in order to collect context switch statistics. 64bit Linux provides the task_struct pointer to the next task that will be switched to, which means we don't have to look up the task_struct from thread_info as we do in 32bit ARM Linux.
This patch adds a second set of accessors to ThreadInfo to extract details such as the pid, tgid, task name, etc., directly from a task_struct. The existing accessors maintain their existing behavior by first looking up the task_struct and then calling these new accessors.
A 64-bit variant of the DumpStatsPCEvent class is added that uses these new accessors to get the task details for the context switch dumps directly from the task_struct passed to __switch_to().
Change-Id: I63c4b3e1ad64446751a91f6340901d5180d7382d Reviewed-on: https://gem5-review.googlesource.com/2640 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
11886:43b882cada33 |
27-Feb-2017 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing. |
11851:824055fe6b30 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process. |
11794:97eebddaae84 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
The class was crammed into syscall_emul.hh which has tons of forward declarations and template definitions. To clean it up a bit, moved the class into separate files and commented the class with doxygen style comments. Also, provided some encapsulation by adding some accessors and a mutator.
The syscallreturn.hh file was renamed syscall_return.hh to make it consistent with other similarly named files in the src/sim directory.
The DPRINTF_SYSCALL macro was moved into its own header file with the include the Base and Verbose flags as well. |
11793:ef606668d247 |
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes |
11538:55014a40512c |
20-Jun-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
kern, arm: Dump dmesg on kernel panic/oops
Add helper functions to dump the guest kernel's dmesg buffer to a text file in m5out. This functionality is split into two parts. First, a dmesg dump function that can be used in other places:
void Linux::dumpDmesg(ThreadContext *, std::ostream &)
This function is used to implement two PCEvents: DmesgDumpEvent and KernelPanic event. The only difference between the two is that the latter produces a gem5 panic instead of a warning in addition to dumping the kernel log.
Change-Id: I6d2af1d666ace57124089648ea906f6c787ac63c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> |
11463:d9e32a851e2e |
27-Apr-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Remove BreakPCEvent on guest kernel panic
The LinuxArmSystem class normally provides support for panicing gem5 if the simulated kernel panics. When this is turned off (default), gem5 uses a BreakPCEvent to provide a debugger hook into the simulator when the kernel crashes. This hook unconditionally kills gem5 with a SIGTRAP unless gem5 is compiled in fast mode. This is undesirable since the panic_on_panic param already provides similar functionality.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
11414:cfad34a15729 |
01-Apr-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: remove mmapFlagTable
After all this it turns out we don't even use it. |
11413:3d47d83a48eb |
01-Apr-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: factor out flag tables into common file
The openFlagTable and mmapFlagTables for emulated Linux platforms are basically identical, but are specified repetitively for every platform. Use a common file that gets included for each platform so that we only have one copy, making them more consistent and simplifying changes (like adding #ifdefs).
In the process, made some minor fixes that slipped through due to previous inconsistencies, and added more #ifdefs to try to fix building on alternative hosts. |
11392:5967db4cff04 |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
base: add symbol support for dynamic libraries
Libraries are loaded into the process address space using the mmap system call. Conveniently, this happens to be a good time to update the process symbol table with the library's incoming symbols so we handle the table update from within the system call.
This works just like an application's normal symbols. The only difference between a dynamic library and a main executable is when the symbol table update occurs. The symbol table update for an executable happens at program load time and is finished before the process ever begins executing. Since dynamic linking happens at runtime, the symbol loading happens after the library is first loaded into the process address space. The library binary is examined at this time for a symbol section and that section is parsed for symbol types with specific bindings (global, local, weak). Subsequently, these symbols are added to the table and are available for use by gem5 for things like trace generation.
Checkpointing should work just as it did previously. The address space (and therefore the library) will be recorded and the symbol table will be entirely recorded. (It's not possible to do anything clever like checkpoint a program and then load the program back with different libraries with LD_LIBRARY_PATH, because the library becomes part of the address space after being loaded.) |
11383:5ac090acd180 |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: extend mmap system call to support file backed mmaps
For O3, which has a stat that counts reg reads, there is an additional reg read per mmap() call since there's an arg we no longer ignore. Otherwise, stats should not be affected. |
11382:654272b82e94 |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: add many Linux kernel flags |
11381:516213d2f0cf |
17-Mar-2016 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: rename OpenFlagTransTable struct
The structure definition only had the open system call flag set in mind when it was named, so we rename it here with the intention of using it to define additional tables to translate flags for other system calls in the future. |
11359:b0b976a1ceda |
27-Nov-2015 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Add support for changing output directories
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
11337:4e3bf51208ba |
13-Feb-2016 |
Michael LeBeane <Michael.Lebeane@amd.com> |
syscall_emul: Implement clock_getres() system call
This patch implements the clock_getres() system call for arm and x86 in linux SE mode. |
11321:02e930db812d |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'. |
11320:42ecb523c64a |
06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'. |
11050:65fc1db5d795 |
21-Aug-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
cpu: Move invldPid constant from Request to BaseCPU
A more natural home for this constant. |
10850:e4328e028961 |
26-May-2015 |
Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> |
arm: Implement some missing syscalls (SE mode)
Adding a few syscalls that were previously considered unimplemented. |
10831:fbdaa08aaa42 |
05-May-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: fix warn_once behavior
The current ignoreWarnOnceFunc doesn't really work as expected, since it will only generate one warning total, for whichever "warn-once" syscall is invoked first. This patch fixes that behavior by keeping a "warned" flag in the SyscallDesc object, allowing suitably flagged syscalls to warn exactly once per syscall. |
10822:d259f2bc2b31 |
05-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable accesses there is no longer need for the work arounds put in place to enforce certain sections of memory to be uncacheable during boot. |
10810:683ab55819fd |
29-Apr-2015 |
Ruslan Bukin <br@bsdpad.com> |
arch, base, dev, kern, sym: FreeBSD support
This adds support for FreeBSD/aarch64 FS and SE mode (basic set of syscalls only)
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10633:ae3b12c845b8 |
03-Jan-2015 |
mike upton <michaelupton@gmail.com> |
arm: Add unlinkat syscall implementation
added ARM aarch64 unlinkat syscall support, modeled on other <xxx>at syscalls. This gets all of the cpu2006 int workloads passing in SE mode on aarch64.
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10537:47fe87b0cf97 |
14-Nov-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arm: Fixes based on UBSan and static analysis
Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base.
Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code. |
10508:aa46a8ae3487 |
30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file. Check SCTLR_EL1 to verify all caches are enabled. |
10495:75d2f19fecce |
22-Oct-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
sim: revert 6709bbcf564d The identifier SYS_getdents is not available on Mac OS X. Therefore, its use results in compilation failure. It seems there is no straight forward way to implement the system call getdents using readdir() or similar C functions. Hence the commit 6709bbcf564d is being rolled back. |
10484:6709bbcf564d |
20-Oct-2014 |
Michael Adler <Michael.Adler@intel.com> |
sim: implement getdents/getdents64 in user mode
Has been tested only for alpha. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10203:3b9e1fa3da47 |
17-Apr-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
sim, arm: implement more of the at variety syscalls
Needed for new AArch64 binaries |
10050:d222a22f78e9 |
28-Jan-2014 |
Mitch Hayenga <mitch.hayenga+gem5@gmail.com> |
arm: Enable umask syscall in SE mode
Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
10037:5cac77888310 |
24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black |
9934:b105ac205021 |
17-Oct-2013 |
Eric Van Hensbergen <Eric.VanHensbergen@ARM.com> |
arm: Accomodate function name changes in newer linux kernels |
9649:c717bd5e0a1d |
22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Enable support for triggering a sim panic on kernel panics
Add the options 'panic_on_panic' and 'panic_on_oops' to the LinuxArmSystem SimObject. When these option are enabled, the simulator panics when the guest kernel panics or oopses. Enable panic on panic and panic on oops in ARM-based test cases. |
9645:c483700ae0ce |
22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Add helper functions that add PCEvents with custom arguments
This changeset adds support for forwarding arguments to the PC event constructors to following methods:
addKernelFuncEvent addFuncEvent
Additionally, this changeset adds the following helper method to the System base class:
addFuncEventOrPanic - Hook a PCEvent to a symbol, panic on failure.
addKernelFuncEventOrPanic - Hook a PCEvent to a kernel symbol, panic on failure.
System implementations have been updated to use the new functionality where appropriate. |
9552:460cf901acba |
19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for overloaded virtual functions
A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur.
This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
9538:182d67b5b57a |
15-Feb-2013 |
Anthony Gutierrez <atgutier@umich.edu> |
loader: add a flattened device tree blob (dtb) object
this adds a dtb_object so the loader can load in the dtb file for linux/android ARM kernels. |
9455:31afddc29cd4 |
08-Jan-2013 |
Mitch Hayenga <mitch.hayenga+gem5@gmail.com> |
arm: add access syscall for ARM SE mode
This patch adds the "access" syscall for ARM SE as required by some spec2006 benchmarks. |
9405:c0a0593510db |
07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
base: Encapsulate the underlying fields in AddrRange
This patch makes the start and end address private in a move to prevent direct manipulation and matching of ranges based on these fields. This is done so that a transition to ranges with interleaving support is possible.
As a result of hiding the start and end, a number of member functions are needed to perform the comparisons and manipulations that previously took place directly on the members. An accessor function is provided for the start address, and a function is added to test if an address is within a range. As a result of the latter the != and == operator is also removed in favour of the member function. A member function that returns a string representation is also created to allow debug printing.
In general, this patch does not add any functionality, but it does take us closer to a situation where interleaving (and more cleverness) can be added under the bonnet without exposing it to the user. More on that in a later patch. |
9332:ae2a5329ce96 |
02-Nov-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
ARM: dump stats and process info on context switches
This patch enables dumping statistics and Linux process information on context switch boundaries (__switch_to() calls) that are used for Streamline integration (a graphical statistics viewer from ARM). |
9290:90dd57ca9a7e |
15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Fix: Address a few minor issues identified by cppcheck
This patch addresses a number of smaller issues identified by the code inspection utility cppcheck. There are a number of identified leaks in the arm/linux/system.cc (although the function only get's called once so it is not a major problem), a few deletes in dev/x86/i8042.cc that were not array deletes, and sprintfs where the character array had one element less than needed. In the IIC tags there was a function allocating an array of longs which is in fact never used. |
9261:f795ce1feb5b |
25-Sep-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
ARM: added support for flattened device tree blobs
Newer Linux kernels require DTB (device tree blobs) to specify platform configurations. The input DTB filename can be specified through gem5 parameters in LinuxArmSystem. |
9146:a61fdbbc1d45 |
06-Aug-2012 |
Marc Orr <marc.orr@gmail.com> |
syscall emulation: Enabled getrlimit and getrusage for x86. Added/moved rlimit constants to base linux header file.
This patch is a revised version of Vince Weaver's earlier patch. |
9141:593fe25c86a6 |
06-Aug-2012 |
Marc Orr <marc.orr@gmail.com> |
syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations, since some use the generic Linux definitions only, and others use definitions inherited from earlier Unix flavors on those architectures.
Also update x86 function pointers so ioctl is no longer unimplemented on that platform.
This patch is a revised version of Vince Weaver's earlier patch. |
9075:b423daedefe5 |
29-Jun-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Update version of linux we claim to be to 3.0.0.
Static binaries generated with new versions of libc complain that the kernel is too old otherwise. |
8997:f07639e4b676 |
10-May-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
ARM: guard masked symbol tables by default
Symbol tables masked with the loadAddrMask create redundant entries that could conflict with kernel function events that rely on the original addresses. This patch guards the creation of those masked symbol tables by default, with an option to enable them when needed (for early-stage kernel debugging, etc.) |
8931:7a1dfb191e3f |
06-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range.
All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables.
Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. |
8902:75b524b64c28 |
19-Mar-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts). |
8885:52bbd95b31ed |
09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from. |
8884:fd92c46655ad |
09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix valgrind reported error on O3 that was causing minor stats changes. |
8870:f95c4042f2d0 |
01-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit. |
8852:c744483edfcf |
24-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would not be complete without a port proxy by making the proxies members rathen than dynamically allocated. In essence, if NULL would not be a valid value for the proxy, then we avoid using a pointer to make this clear.
The same approach is used for the methods using these proxies, such as loadSections, that now use references rather than pointers to better reflect the fact that NULL would not be an acceptable value (in fact the code would break and that is how this patch started out).
Overall the concept of "using a reference to express unconditional composition where a NULL pointer is never valid" could be done on a much broader scale throughout the code base, but for now it is only done in the locations affected by the proxies. |
8706:b1838faf3bcc |
17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy.
The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy |
8601:af28085882dc |
23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable.
The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process. |
8600:b0d7c64ada19 |
23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: implement MAP_FIXED option to mmap() |
8527:6bac5b04d588 |
19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression). |
8286:abc8ab4ddd93 |
04-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for loading the a bootloader and configuring parameters for it |
8245:a9d06c894afe |
20-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
fix some build problems from prior changesets |
8229:78bf55f23338 |
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes |
8216:70e61aa65759 |
10-Apr-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix checkpoint restoration in ARM_SE. |
8215:1c89a6d235b9 |
10-Apr-2011 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Get rid of some comments/todos that no longer apply. |
8149:12bd3ad81f9d |
17-Mar-2011 |
Chris Emmons <Chris.Emmons@ARM.com> |
ARM: Add minimal ARM_SE support for m5threads.
Updated some of the assembly code sequences to use armv7 instructions and coprocessor 15 for storing the TLS pointer. |
8143:b0b94a7b7c1f |
17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Detect and skip udelay() functions in linux kernel.
This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed. |
7799:5d0f62927d75 |
20-Dec-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Style: Replace some tabs with spaces. |
7733:08d6a773d1b6 |
08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add checkpointing support |
7723:ee4ac00d0774 |
08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
sim: Use forward declarations for ports.
Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything. |
7720:65d338a8dba4 |
31-Oct-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later.
Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. |
7585:afbc40280b56 |
23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Add system for ARM/Linux and bootstrapping |
7441:be2acdfb8bdc |
02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all Spec2k benchmarks seem to run with atomic or timing mode simple CPUs. Fixed up some constants, handling of 64 bit arguments, and marked a few more syscalls ignoreFunc. |
7416:e1a7a9f33a00 |
02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: fix sizes of structs for ARM Linux |
7414:0a05aa495903 |
02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fixup native trace support and add some v7/recent stack code |
7411:b70c71ac7399 |
02-Jun-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Implement the getrusage syscall. |
7096:e81026b9dfe0 |
02-Jun-2010 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Allow ARM processes to start in Thumb mode. |
6701:4842482e1bd1 |
30-Oct-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly.
All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. |
6689:67d980fcbc7a |
24-Oct-2009 |
Timothy M. Jones <tjones1@inf.ed.ac.uk> |
syscall: Addition of an ioctl command code for Power. |
6640:30d92d2b66a1 |
16-Sep-2009 |
Vince Weaver <vince@csl.cornell.edu> |
Syscalls: Implement sysinfo() syscall. |
6421:1aa0b4673699 |
29-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Fix an instruction in the cmpxchg kernel provided routine. The instruction was encoded as a load instead of the intended store. |
6420:7d0e7547be5e |
29-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Get rid of a stray line in the set_tls handler. |
6416:425703ea71c9 |
29-Jul-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Ignore the "times" system call. |
6415:d6f1c81980e2 |
29-Jul-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix an ioctl constant. |
6413:424ac9b1079a |
27-Jul-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Update some syscall constants and delete others that are Alpha only. |
6395:05f1d2cd7e9e |
27-Jul-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix fstat/fstat64 structs to match EABI definitions. |
6393:1895318a1b26 |
27-Jul-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Handle register indexed system calls. |
6341:46819ffe2778 |
15-Jul-2009 |
Jack Whitham <jack-m5ml2@cs.york.ac.uk> |
ARM: Fix the "open" flag constants. |
6236:9c0f2130478b |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params. |
6235:33adfb8af4c0 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a memory_barrier function to the "comm page". This function doesn't actually provide a memory barrier (I don't think they're implemented) and instead just returns. |
6234:17e7ab512377 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Add a cmpxchg implementation to the "comm page". This implementation does what it's supposed to (I think), but it's not atomic and doesn't have memory barriers like the kernel's version. |
6233:014ae6da6c2a |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Implement TLS. This is not tested. |
6232:e0ea733d2105 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Make ArmLinuxProcess understand "ARM private" system calls. |
6231:8130f3faa584 |
10-Jun-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ARM: Update the kernel version M5 reports to 2.6.16.19 |
6020:0647c8b31a99 |
06-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
Merge ARM into the head. ARM will compile but may not actually work. |
6019:76890d8b28f5 |
05-Apr-2009 |
Stephen Hines <hines@cs.fsu.edu> |
arm: add ARM support to M5 |