arch-arm: Add Illegal Execution flag to PCState

This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage. This is
done by adding the illegalExecution field to the PCState.

Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add AArch32 HLT Semihosting interface

AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Raise an alignment fault if a PC has illegal alignment

We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the TLB when running in aarch64 mode, but this
check does not cover cases where the CPU does not do a TLB lookup when
decoding an instruction (e.g., a branch stays within the same cache
line). Additionally, the Decoder class sometimes throws an assertion
for unaligned PCs which breaks speculation.

This changeset introduces a decoder fault bit field in the ExtMachInst
structure. This field can be used to signal a decoder failure. If set,
the decoder generates an internal gem5fault instruction instead of a
normal instruction. This instruction in turns either panics (fault
type PANIC), returns an PCAlignmentFault (fault type UNALIGNED,
aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32).

The patch causes minor changes to the realview64 regressions, and a
stats bump will follow.

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ARM: Add limited CP14 support.

New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.

ARM: Add support for M5 ops in the ARM ISA

ARM: Implement all ARM SIMD instructions.

ARM: Decode the neon instruction space.

ARM: Move some case values out of ##included files.

This will help keep the high level decode together and not have it spread into
the subordinate decode stuff. The ##include lines still need to be on a line
by themselves, though.

ARM: Move some miscellaneous instructions out of the decoder to share with thumb.

ARM: Get rid of some of the old FP implementation.

ARM: Add BKPT instruction

ARM: Implement ARM CPU interrupts

ARM: Move the VFP data operation decode into a function.

ARM: Add some support for wfi/wfe/yield/etc

ARM: BXJ should be BX when there is no J support

ARM: Fix up thumb decoding of coproc instructions.

ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.

ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.

ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.

ARM: Decode the RFE instruction.

ARM: When an instruction is intentionally undefined, fault on it.

ARM: Decode the thumb32 load byte/memory hint instructions.

ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.

ARM: Replace the ARM decode of CP15 MCR and MRC instructions.

ARM: Decode the thumb versions of the mcr and mrc instructions.

ARM: Decode miscellaneous arm mode media instructions.

ARM: Decode the clz instruction.

ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.

ARM: Decode the usad8 and usada8 instructions.

ARM: Decode 32 bit thumb data processing register instructions.

ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.

ARM: Decode the swp and swpb instructions.

ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.

ARM: Implement SVC (was SWI) outside of the decoder.

ARM: Trigger system calls from the SupervisorCall invoke method.

This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.

ARM: Decode the scalar saturating add/subtract instructions.

ARM: Decode the parallel add and subtract instructions.

ARM: Decode unconditional ARM instructions.

ARM: Define the VFP load/store multiple instructions.

ARM: Hook the new multiply instructions into all the decoders.

ARM: Decode plain binary immediate thumb data processing instructions.

ARM: Hook the new branch instructions into the 32 bit thumb decoder.

ARM: Hook the new branch instructions into the 16 bit thumb decoder.

ARM: Hook the new branch instructions into the ARM decoder.

ARM: Implement branch instructions external to the decoder.

ARM: Hook the external data processing instructions into the Thumb decoder.

ARM: Hook the new external data processing instructions to the ARM decoder.

ARM: Hook up 32 bit thumb load/store multiple.

ARM: Hook up 16 bit thumb load/store multiple.

ARM: Reimplement load/store multiple external to the decoder.

ARM: Eliminate decoding for the very deprecated FPA instructions.

ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.

ARM: Decode 16 bit thumb PC relative memory instructions.

ARM: Decode 16 bit thumb immediate addressed memory instructions.

ARM: Decode 16 bit thumb register addressed memory instructions.

ARM: Make single stores decode to the new external store instructions.

ARM: Make 32 bit thumb use the new, external load instructions.

ARM: Define the store instructions from outside the decoder.

ARM: Define the load instructions from outside the decoder.

ARM: Create a "decoder" directory for the files implementing the decoder.