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13774:a1be2a0c55f2 25-Feb-2019 Andreas Sandberg <andreas.sandberg@arm.com>

configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


/gem5/configs/common/BPConfig.py
/gem5/configs/common/Benchmarks.py
/gem5/configs/common/CacheConfig.py
/gem5/configs/common/Caches.py
/gem5/configs/common/CpuConfig.py
/gem5/configs/common/FSConfig.py
/gem5/configs/common/GPUTLBConfig.py
/gem5/configs/common/GPUTLBOptions.py
/gem5/configs/common/HMC.py
/gem5/configs/common/MemConfig.py
/gem5/configs/common/Options.py
/gem5/configs/common/PlatformConfig.py
/gem5/configs/common/SimpleOpts.py
/gem5/configs/common/Simulation.py
/gem5/configs/common/SysPaths.py
/gem5/configs/common/__init__.py
/gem5/configs/common/cores/__init__.py
/gem5/configs/common/cores/arm/HPI.py
/gem5/configs/common/cores/arm/O3_ARM_v7a.py
/gem5/configs/common/cores/arm/__init__.py
/gem5/configs/common/cores/arm/ex5_LITTLE.py
/gem5/configs/common/cores/arm/ex5_big.py
/gem5/configs/common/cpu2000.py
/gem5/configs/dram/lat_mem_rd.py
/gem5/configs/dram/low_power_sweep.py
/gem5/configs/dram/sweep.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/arm/devices.py
/gem5/configs/example/arm/dist_bigLITTLE.py
/gem5/configs/example/arm/fs_bigLITTLE.py
/gem5/configs/example/arm/fs_power.py
/gem5/configs/example/arm/starter_fs.py
/gem5/configs/example/arm/starter_se.py
/gem5/configs/example/etrace_replay.py
/gem5/configs/example/fs.py
/gem5/configs/example/garnet_synth_traffic.py
/gem5/configs/example/hmc_hello.py
/gem5/configs/example/hmctest.py
/gem5/configs/example/memcheck.py
/gem5/configs/example/memtest.py
/gem5/configs/example/read_config.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_gpu_random_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/learning_gem5/part1/caches.py
/gem5/configs/learning_gem5/part1/simple.py
/gem5/configs/learning_gem5/part1/two_level.py
/gem5/configs/learning_gem5/part2/hello_goodbye.py
/gem5/configs/learning_gem5/part2/run_simple.py
/gem5/configs/learning_gem5/part2/simple_cache.py
/gem5/configs/learning_gem5/part2/simple_memobj.py
/gem5/configs/learning_gem5/part3/msi_caches.py
/gem5/configs/learning_gem5/part3/ruby_caches_MI_example.py
/gem5/configs/learning_gem5/part3/ruby_test.py
/gem5/configs/learning_gem5/part3/simple_ruby.py
/gem5/configs/learning_gem5/part3/test_caches.py
/gem5/configs/network/Network.py
/gem5/configs/network/__init__.py
/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/Ruby.py
cluster.py
run.py
/gem5/configs/topologies/BaseTopology.py
/gem5/configs/topologies/Cluster.py
/gem5/configs/topologies/Crossbar.py
/gem5/configs/topologies/CrossbarGarnet.py
/gem5/configs/topologies/MeshDirCorners_XY.py
/gem5/configs/topologies/Mesh_XY.py
/gem5/configs/topologies/Mesh_westfirst.py
/gem5/configs/topologies/Pt2Pt.py
/gem5/configs/topologies/__init__.py
13731:67cd980cb20f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

configs: Fix Python 3 iterator and exec compatibility issues

Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.

This change doesn't fix import paths since that might require us to
restructure the configs slightly.

Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>


/gem5/configs/common/BPConfig.py
/gem5/configs/common/Benchmarks.py
/gem5/configs/common/CacheConfig.py
/gem5/configs/common/CpuConfig.py
/gem5/configs/common/FSConfig.py
/gem5/configs/common/GPUTLBConfig.py
/gem5/configs/common/HMC.py
/gem5/configs/common/MemConfig.py
/gem5/configs/common/Options.py
/gem5/configs/common/PlatformConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/common/SysPaths.py
/gem5/configs/common/cores/arm/HPI.py
/gem5/configs/common/cpu2000.py
/gem5/configs/dist/sw.py
/gem5/configs/dram/lat_mem_rd.py
/gem5/configs/dram/low_power_sweep.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/fs.py
/gem5/configs/example/garnet_synth_traffic.py
/gem5/configs/example/hmctest.py
/gem5/configs/example/memcheck.py
/gem5/configs/example/memtest.py
/gem5/configs/example/read_config.py
/gem5/configs/example/ruby_gpu_random_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/AMD_Base_Constructor.py
/gem5/configs/ruby/GPU_RfO.py
/gem5/configs/ruby/GPU_VIPER.py
/gem5/configs/ruby/GPU_VIPER_Baseline.py
/gem5/configs/ruby/GPU_VIPER_Region.py
/gem5/configs/ruby/Garnet_standalone.py
/gem5/configs/ruby/MESI_Three_Level.py
/gem5/configs/ruby/MESI_Two_Level.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_AMD_Base.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Ruby.py
cluster.py
run.py
/gem5/configs/topologies/MeshDirCorners_XY.py
/gem5/configs/topologies/Mesh_XY.py
/gem5/configs/topologies/Mesh_westfirst.py
/gem5/configs/topologies/Pt2Pt.py
12564:2778478ca882 06-Mar-2018 Gabe Black <gabeblack@google.com>

config: Switch from the print statement to the print function.

Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0
Reviewed-on: https://gem5-review.googlesource.com/8762
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

11851:824055fe6b30 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.


/gem5/configs/common/cpu2000.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/se.py
/gem5/configs/learning_gem5/part1/simple.py
/gem5/configs/learning_gem5/part1/two_level.py
cluster.py
run.py
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/process.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/freebsd/process.cc
/gem5/src/arch/arm/freebsd/process.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/riscv/linux/process.cc
/gem5/src/arch/riscv/linux/process.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/process.hh
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/kern/freebsd/freebsd.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/operatingsystem.hh
/gem5/src/sim/Process.py
/gem5/src/sim/emul_driver.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/syscall_desc.cc
/gem5/src/sim/syscall_desc.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/tests/long/se/10.mcf/test.py
/gem5/tests/long/se/20.parser/test.py
/gem5/tests/long/se/30.eon/test.py
/gem5/tests/long/se/40.perlbmk/test.py
/gem5/tests/long/se/50.vortex/test.py
/gem5/tests/long/se/60.bzip2/test.py
/gem5/tests/long/se/70.twolf/test.py
/gem5/tests/quick/se/00.hello.mp/test.py
/gem5/tests/quick/se/00.hello/test.py
/gem5/tests/quick/se/01.hello-2T-smt/test.py
/gem5/tests/quick/se/02.insttest/test.py
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/10.mcf/test.py
/gem5/tests/quick/se/30.eon/test.py
/gem5/tests/quick/se/40.m5threads-test-atomic/test.py
/gem5/tests/quick/se/50.vortex/test.py
/gem5/tests/quick/se/70.twolf/test.py
11682:612f75cf36a0 14-Oct-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Make configs/common a Python package

Continue along the same line as the recent patch that made the
Ruby-related config scripts Python packages and make also the
configs/common directory a package.

All affected config scripts are updated (hopefully).

Note that this change makes it apparent that the current organisation
and naming of the config directory and its subdirectories is rather
chaotic. We mix scripts that are directly invoked with scripts that
merely contain convenience functions. While it is not addressed in
this patch we should follow up with a re-organisation of the
config structure, and renaming of some of the packages.


/gem5/configs/common/__init__.py
/gem5/configs/dist/sw.py
/gem5/configs/dram/lat_mem_rd.py
/gem5/configs/dram/sweep.py
/gem5/configs/example/apu_se.py
/gem5/configs/example/arm/devices.py
/gem5/configs/example/arm/fs_bigLITTLE.py
/gem5/configs/example/etrace_replay.py
/gem5/configs/example/fs.py
/gem5/configs/example/garnet_synth_traffic.py
/gem5/configs/example/hmctest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_gpu_random_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/learning_gem5/part1/caches.py
/gem5/configs/learning_gem5/part1/two_level.py
/gem5/configs/ruby/Ruby.py
cluster.py
run.py
/gem5/tests/configs/alpha_generic.py
/gem5/tests/configs/arm_generic.py
/gem5/tests/configs/base_config.py
/gem5/tests/configs/checkpoint.py
/gem5/tests/configs/gpu-randomtest-ruby.py
/gem5/tests/configs/gpu-ruby.py
/gem5/tests/configs/learning-gem5-p1-two-level.py
/gem5/tests/configs/memtest-filter.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mt.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview64-o3-checker.py
/gem5/tests/configs/realview64-o3-dual.py
/gem5/tests/configs/realview64-o3.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/switcheroo.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
/gem5/tests/configs/x86_generic.py
11053:62544e45c0f4 21-Aug-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Add explicit Cache subclass and make BaseCache abstract

Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.

10720:67b3e74de9ae 02-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Move crossbar default latencies to subclasses

This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the different uses in the system. We
use the crossbar in a wide range of places: interfacing cores to the
L2, as a system interconnect, connecting I/O and peripherals,
etc. Needless to say, these crossbars have very different performance,
and the clock frequency alone is not enough to distinguish these
scenarios.

Instead of trying to capture every possible case, this patch
introduces dedicated subclasses for the three primary use-cases:
L2XBar, SystemXBar and IOXbar. More can be added if needed, and the
defaults can be overridden.

10405:7a618c07e663 20-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.

9815:3b3b94536547 18-Jul-2013 Andreas Hansson <andreas.hansson>

config: Update script to set cache line size on system

This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.

9790:ccc428657233 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Add a system clock command-line option

This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.

9036:6385cf85bf12 31-May-2012 Andreas Hansson <andreas.hansson@arm.com>

Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.


/gem5/configs/common/CacheConfig.py
/gem5/configs/common/FSConfig.py
/gem5/configs/example/memtest.py
/gem5/configs/example/se.py
cluster.py
run.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/mem/Bus.py
/gem5/src/mem/SConscript
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/coherent_bus.cc
/gem5/src/mem/coherent_bus.hh
/gem5/src/mem/noncoherent_bus.cc
/gem5/src/mem/noncoherent_bus.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
8931:7a1dfb191e3f 06-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.


/gem5/configs/common/FSConfig.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
/gem5/configs/ruby/MESI_CMP_directory.py
/gem5/configs/ruby/MI_example.py
/gem5/configs/ruby/MOESI_CMP_directory.py
/gem5/configs/ruby/MOESI_CMP_token.py
/gem5/configs/ruby/MOESI_hammer.py
/gem5/configs/ruby/Network_test.py
/gem5/configs/ruby/Ruby.py
cluster.py
run.py
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/ide_disk.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/SConscript
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/System.py
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8847:ef8630054b5e 14-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.

8836:922edffe734d 12-Feb-2012 Ali Saidi <saidi@eecs.umich.edu>

configs: fix minor config bugs posted on the mailing list

8801:1a84c6a81299 28-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Make SE vs. FS mode a runtime parameter.


/gem5/configs/common/FSConfig.py
/gem5/configs/example/fs.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_direct_test.py
/gem5/configs/example/ruby_fs.py
/gem5/configs/example/ruby_mem_test.py
/gem5/configs/example/ruby_network_test.py
/gem5/configs/example/ruby_random_test.py
/gem5/configs/example/se.py
cluster.py
run.py
/gem5/src/sim/Root.py
/gem5/src/sim/full_system.hh
/gem5/src/sim/root.cc
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
7876:189b9b258779 03-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

7716:fa706473bcd5 22-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

Configs: Stop setting the "mem" parameter in splash2 config files.

This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.

7525:722f2ad014a7 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.

6654:4c84e771cca7 22-Sep-2009 Nathan Binkert <nate@binkert.org>

python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.


/gem5/SConstruct
/gem5/configs/common/Caches.py
/gem5/configs/common/FSConfig.py
/gem5/configs/common/Simulation.py
/gem5/configs/example/fs.py
/gem5/configs/example/memtest.py
/gem5/configs/example/ruby_se.py
/gem5/configs/example/se.py
cluster.py
run.py
/gem5/src/SConscript
/gem5/src/arch/mips/BISystem.py
/gem5/src/arch/mips/MipsCPU.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/memtest/MemTest.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/ozone/OzoneCPU.py
/gem5/src/cpu/ozone/OzoneChecker.py
/gem5/src/cpu/ozone/SimpleOzoneCPU.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/dev/Uart.py
/gem5/src/mem/Bus.py
/gem5/src/python/SConscript
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/environment.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/params.py
/gem5/src/python/m5/simulate.py
/gem5/src/python/m5/smartdict.py
/gem5/src/python/m5/ticks.py
/gem5/src/python/m5/trace.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/m5/util/convert.py
/gem5/src/python/m5/util/jobfile.py
/gem5/src/python/m5/util/misc.py
/gem5/src/python/m5/util/smartdict.py
/gem5/src/sim/System.py
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
/gem5/tests/long/00.gzip/test.py
/gem5/tests/long/10.mcf/test.py
/gem5/tests/long/20.parser/test.py
/gem5/tests/long/30.eon/test.py
/gem5/tests/long/40.perlbmk/test.py
/gem5/tests/long/50.vortex/test.py
/gem5/tests/long/60.bzip2/test.py
/gem5/tests/long/70.twolf/test.py
5256:723d4c11ac26 15-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Configs: Fix for benchmarks that don't use getopt.

5255:79825caee5fd 15-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Config: Fix some errors in the splash2 config file.

4876:a18cedc19da5 30-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Get rid of remaining traces of obsolete CoherenceProtocol object.

4403:824f7311059c 23-Apr-2007 Ron Dreslinski <rdreslin@umich.edu>

Fix the splash2 run script

3646:66853026ad52 13-Nov-2006 Ron Dreslinski <rdreslin@umich.edu>

Update splash2 config files

configs/splash2/run.py:
Fix MaxTick for splash configs
configs/splash2/cluster.py:
Add a config that allows clusters of CPU's to be attached to a single L1

3623:c37f82ace0fe 12-Nov-2006 Ron Dreslinski <rdreslin@umich.edu>

Update for maxtick in splash2/memtest configs

configs/example/memtest.py:
configs/splash2/run.py:
Update for maxtick

3360:9a802e1085ec 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Add some default options, point it to the /dist version of the splash benchmarks

3358:f70480ec2642 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Clean up splash2 so it works in v2.0

configs/splash2/run.py:
Update the splash2 file

1714:e83b18b0238d 04-Jun-2005 Steve Reinhardt <stever@eecs.umich.edu>

Clean up to work with recent python config changes.

configs/splash2/run.py:
parent is now Parent.
Need to explicitly instantiate classes.

1693:627f0d579dc1 01-Jun-2005 Steve Reinhardt <stever@eecs.umich.edu>

A few more config updates. Works with regression now.

configs/splash2/run.py:
Update file for new config changes.
python/m5/config.py:
- isParamContext() not defined any more
- fix bug with re-assigning vectors over scalars
and vice versa

1569:d98e324566b3 16-Mar-2005 Ron Dreslinski <rdreslin@umich.edu>

Fixed the super/parent change fpr splash2 benchmarks

configs/splash2/run.mpy:
Change super to parent

1516:2e7e1db672dd 11-Mar-2005 Ron Dreslinski <rdreslin@umich.edu>

Added config files for splash2 benchmarks. Parameters:
ROOTDIR = root directory of the splash2 code
NP = number of proccessors
BENCHMARK = name of the splash2 benchmark (Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig, OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial)
SYSTEM = Type of system to simulate detailed or simple

Note: They use MOESI protocol and do_events is enabled (Multiple L1's and a shared L2)