History log of /gem5/configs/
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14216:188a91ee11c1 02-Sep-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

configs: Fix replacement policy assignment

Commit d207e9ccee411877fdeac80bb68a27900560f50f reworked the tags
to split the replacement policies, however the name of the variable
that contains the replacement policy changed between patch revisions,
which was not updated accordingly in the configs files.

Change-Id: I2072529e2c7d54197c371bcaa323bfd9f34ec3ba
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20548
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14178:f68430623245 13-Aug-2019 Adrian Herrera <adrian.herrera@arm.com>

configs: root, platform options in fs bigLITTLE

(1) Two new options are added to fs_bigLITTLE.py:
- "root": disk/partition containing the rootfs (def. "/dev/vda1")
- "machine-type": hardware platform class (def. "VExpress_GEM5_V1")
+ Accepts platform classes from PlatformConfig
(2) Default kernel is not available in public uploads, force the user
to provide its own kernel instead of crashing.

Change-Id: I88283ae12cd7289e15b9277ea2cc382e9136f11c
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20148
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14115:2a3eee6ded38 29-Jul-2019 Chun-Chen TK Hsu <chunchenhsu@google.com>

configs, arch-arm: Check if gic has cpu_addr attribute

Add this check because Gicv3 does not have the cpu_addr attribute.

Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the
following command to boot Debian.

M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \
--dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \
--kernel $PWD/fs_files/binaries/vmlinux \
--disk $PWD/fs_files/disks/disk.img \
--cpu-type atomic --big-cpus 1 --little-cpus 0

Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14062:21848204c189 19-Jun-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

configs: Fix NULL dram-lowp regressions

The problem arises since there are some scripts (like NULL dram
regressions) which are making use of MemConfig.py without using
Opions.py so they won't have the new enable-dram-powerdown option

Change-Id: Id9769cce2e8a25b57da76f07eeebd279a6e00440
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19268
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14051:aff599136be8 07-Jun-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Fix read_config to work with new AddrRange serialization

Change-Id: I122c77c34c2f8c75f8b32682be858f651112ce89
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19151
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14050:09be542e022f 07-Jun-2019 Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Add python3 workarounds in read_config

Change-Id: Ib065f41b87e5ada9535b9c2645067162aa69234b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19150
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14038:8ba13d8b7810 01-May-2019 Matthew Poremba <matthew.poremba@amd.com>

mem: Option to toggle DRAM low-power states

Adding an option to enable DRAM low-power states. The low power
states can have a significant impact on application performance
(sim_ticks) on the order of 2-3x, especially for compute-gpu apps.
The options allows for it to easily be enabled/disabled to compare
performance numbers. The option is disabled by default.

Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14032:f65b663b0df8 03-Apr-2019 Willy Wolff <willy.mh.wolff.ml@gmail.com>

config, arm: memoryMode test

Commit 9a13acaa367769c38859342de9bc35aac59a6710 doesn't comply with the
same behaviour. The conditional test the memory mode on the same cluster,
while it should test the other cluster.

Change-Id: If3a7863f0905e66a548001d8e74689f5dd07179c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17748
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13980:62a28c423e91 16-May-2019 Jason Lowe-Power <jason@lowepower.com>

configs: Generalize FileSystemConfig for non se.py

This patch updates the FileSystemConfig so it works with more kinds of
config scripts (e.g., the Learning gem5 scripts).

There are 4 main changes:
- Added system as a parameter to the config_filesystem function so the
function can search the system for the number of CPUs instead of relying
on options from Options.py
- Instead of calling redirect_paths everywhere config_filesystem is
used, now it is implicitly called.
- Cleaned up the Ruby scripts a bit to remove redundant calls to
config_filesystem
- Added a config_filesystem call to the Ruby Learning gem5 script
(currently the only Learning gem5 script that requires it).

In the future, I think it would be better to move the config_filesystem
call into simulate.py, probably into the instantiate function. I tried to
use the per-CPU configuration parameters instead of options from
Options.py, but that's not possible until after the SimObject params
have been finalized in instantiate.

Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

13975:31372ed09a54 19-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Cache latencies for MOESI_CMP_dir

Modified both L1 and L2 controllers to take into account the cache
latency parameters. Default values in the configuration script updated
as well.

Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13974:af47a3ae0f6b 19-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Hit latencies defined by the controllers

Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.

Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13971:0201983aad69 14-Feb-2019 Tiago Muck <tiago.muck@arm.com>

mem-ruby: Change MOESI_CMP_Dir L2 addressing

L1 controller selects the L2 to message based on the assigned address
ranges instead of explicitly interleaving bits in the L1 controller. This
simplifies the L1 controller implementation a bit and allows for more
flexibility when changing the address->controller mapping.

Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13967:755cdc26b48d 14-May-2019 Javier Bueno <javier.bueno@metempsy.com>

configs: Fix duplicate branchPred reference in Simulation.py

Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13958:1945df12e5b0 07-Jan-2019 Jairo Balart <jairo.balart@metempsy.com>

config: add an option to list and select indirect branch predictor

Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13952:197e72db5ab0 09-May-2019 Brandon Potter <brandon.potter@amd.com>

config, sim-se: bugfix for 54c77aa0

The NULL ISA does not have some members for the options
class which are referenced by the FileSystemConfig
code.

Create default values for the members so that the
simulation does not fail during the configuration phase.

Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18748
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13951:b8ec67ca5e42 08-May-2019 Daniel R. Carvalho <odanrc@yahoo.com.br>

configs: Fix FileSystemConfig import

Add source to FileSystemConfig import

Change-Id: I2cd70a332244cbdc58b1b7c06d589b4339f6e19a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18709
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

13885:d10ea5e56cb0 18-Apr-2018 David Hashe <david.hashe@amd.com>

configs: faux-filesystem fix w/ ruby in se mode

These changes are needed so that the config scripts
can report cache hierarchy information to the faux
filesystem.

This is useful for the ROCm runtime when it reads
psuedofiles from the host filesytem from "/proc".

Change-Id: Iad3e6c088d47c9b93979f584de748367eae8259b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12121
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13883:f44e21d3aaa7 18-Apr-2018 David Hashe <david.hashe@amd.com>

sim-se: add a faux-filesystem

This change introduces the concept of a faux-filesystem.
The faux-filesystem creates a directory structure in m5out
(or whatever output dir the user specifies) where system calls
may be redirected.

This is useful to avoid non-determinism when reading files
with varying path names (e.g., variations from run-to-run if
the simulation is scheduled on a cluster where paths may change).

Also, this changeset allows circumventing host pseudofiles which
have information specific to the host processor (such as cache
hierarchy or processor information). Bypassing host pseudofiles
can be useful when executing runtimes in the absence of an
operating system kernel since runtimes may try to query standard
files (i.e. /proc or /sys) which are not relevant to an
application executing in syscall emulation mode.

Change-Id: I90821b3b403168b904a662fa98b85def1628621c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13876:1643f200987c 27-Mar-2019 Javier Bueno <javier.bueno@metempsy.com>

config: Add flag options to set the hardware prefetchers to use

This patch adds three flag options to set the prefetcher class of the
L1i cache, L1d cache and L2 cache.

Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17709
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13864:815193aa6617 22-Apr-2019 Po-Hao Su <supohaosu@gmail.com>

configs: Use param to get number of processors

Although the parameter np is the same as options.num_cpus. But we should
get the number of processors from the parameters of the function.

Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

13842:7bda240061e4 05-Apr-2019 Jason Lowe-Power <jason@lowepower.com>

learning_gem5,configs: Update ruby_test

Use SimpleMemory instead of DDR3 so we can use the timing results in
tests. By using SimpleMemory, even if the DRAM timing changes the timing
of this test won't change. I expect the timing of SimpleMemory to never
change.

Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

13840:b831620edab0 04-Apr-2019 Jason Lowe-Power <jason@lowepower.com>

configs: Fix import path error in learning_gem5 part3

Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

13839:a32423451596 04-Apr-2019 Jason Lowe-Power <jason@lowepower.com>

configs: Add full path for learning_gem5 binaries

Change-Id: Ie48429d65e322136109a223ed404937989aae494
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

13838:d90eaeb087c8 07-Apr-2019 Ryan Gambord <gambordr@oregonstate.edu>

configs: Removed redudant exec-style import

garnet_synth_traffic.py imports common.Options on line 40, so exec'ing
the Options.py file again seems redundant.

It also runs Options.py as a script rather than a module, which throws
ValueError: Attempted relative import in non-package due to the recent
change to python3 imports.

Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13811:88827de8fced 26-Mar-2019 Javier Bueno <javier.bueno@metempsy.com>

config: Use the corresponding HPI Caches when using the HPI cpu

The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.

Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13806:e2ca4f169e82 23-Mar-2019 Javier Bueno <javier.bueno@metempsy.com>

configs: fix class reference in CacheConfigs

One reference was not properly updated when changing to absolute import paths

Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13803:32c104f40e57 25-Jul-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

configs: Remove default kernel value from system creation

Kernel was being set using a placeholder and then assigned the
correct value. This would generate the following error if the
placeholder file did not exist:
'IOError: Can't find file <placeholder> on path'

This patch follows the same directions of commit
12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default
values, forcing the user to properly configure the kernel.

Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13774:a1be2a0c55f2 25-Feb-2019 Andreas Sandberg <andreas.sandberg@arm.com>

configs: Use absolute import paths

Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.

Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>


common/BPConfig.py
common/Benchmarks.py
common/CacheConfig.py
common/Caches.py
common/CpuConfig.py
common/FSConfig.py
common/GPUTLBConfig.py
common/GPUTLBOptions.py
common/HMC.py
common/MemConfig.py
common/Options.py
common/PlatformConfig.py
common/SimpleOpts.py
common/Simulation.py
common/SysPaths.py
common/__init__.py
common/cores/__init__.py
common/cores/arm/HPI.py
common/cores/arm/O3_ARM_v7a.py
common/cores/arm/__init__.py
common/cores/arm/ex5_LITTLE.py
common/cores/arm/ex5_big.py
common/cpu2000.py
dram/lat_mem_rd.py
dram/low_power_sweep.py
dram/sweep.py
example/apu_se.py
example/arm/devices.py
example/arm/dist_bigLITTLE.py
example/arm/fs_bigLITTLE.py
example/arm/fs_power.py
example/arm/starter_fs.py
example/arm/starter_se.py
example/etrace_replay.py
example/fs.py
example/garnet_synth_traffic.py
example/hmc_hello.py
example/hmctest.py
example/memcheck.py
example/memtest.py
example/read_config.py
example/ruby_direct_test.py
example/ruby_gpu_random_test.py
example/ruby_mem_test.py
example/ruby_random_test.py
example/se.py
learning_gem5/part1/caches.py
learning_gem5/part1/simple.py
learning_gem5/part1/two_level.py
learning_gem5/part2/hello_goodbye.py
learning_gem5/part2/run_simple.py
learning_gem5/part2/simple_cache.py
learning_gem5/part2/simple_memobj.py
learning_gem5/part3/msi_caches.py
learning_gem5/part3/ruby_caches_MI_example.py
learning_gem5/part3/ruby_test.py
learning_gem5/part3/simple_ruby.py
learning_gem5/part3/test_caches.py
network/Network.py
network/__init__.py
ruby/GPU_RfO.py
ruby/MI_example.py
ruby/Ruby.py
splash2/cluster.py
splash2/run.py
topologies/BaseTopology.py
topologies/Cluster.py
topologies/Crossbar.py
topologies/CrossbarGarnet.py
topologies/MeshDirCorners_XY.py
topologies/Mesh_XY.py
topologies/Mesh_westfirst.py
topologies/Pt2Pt.py
topologies/__init__.py
13731:67cd980cb20f 26-Jan-2019 Andreas Sandberg <andreas.sandberg@arm.com>

configs: Fix Python 3 iterator and exec compatibility issues

Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.

This change doesn't fix import paths since that might require us to
restructure the configs slightly.

Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>

13727:8d69b7e86acd 20-Feb-2019 Gabe Black <gabeblack@google.com>

systemc: Update the sc_main.py config to use m5.systemc.

Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991
Reviewed-on: https://gem5-review.googlesource.com/c/16568
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

13684:076506a21535 24-Jan-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

configs: simpoint-profile usable with NonCachingCPUs only

NonCachingCPU is replacing the Atomic+fastmem option.

Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15935
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13659:c2d68b376f7f 11-Feb-2019 Gabe Black <gabeblack@google.com>

systemc: config: Don't inject a custom argv[0] in sc_main.py.

argv[0] is already part of sys.argv, so we don't need to add an
additional argument in front of sys.argv.

The argv[0] which is used in gem5 config scripts is the name of the
config script itself. While it might seem a little odd for the name of
a systemc program to end in .py, it's as arbitrary as any other name,
and generally shouldn't cause a problem. If some other more
sophisticated mechanism for setting argv[0] is necessary, then the user
can write a very slightly more complicated version of this script with
additional logic.

Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8
Reviewed-on: https://gem5-review.googlesource.com/c/16342
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

13658:f82614880471 09-Feb-2019 Gabe Black <gabeblack@google.com>

systemc: configs: Add a very simple config which just runs sc_main.

This config will just run the sc_main function (which must have been
provided in c++ somehow), passing through any of the scripts command
line arguments to sc_main.

Needing to do this sort of thing is common enough that there should be
a canned config which supports it.

Change-Id: I8f88ba4776b9ec919dd8145a58cd856e11ac4e77
Reviewed-on: https://gem5-review.googlesource.com/c/16287
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13636:3b55e4bae1d8 04-Feb-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

configs, arch-arm: Using AddrRange for Realview mem_regions

Physical memory ranges are now saved in Realview objects as pairs of
addresses (start address and size). This patch is substituting them with
a single AddrRange object.

Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16206
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13635:d9dcebb1d6b6 03-Feb-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

configs: Unifiy interpretation of Realview mem_regions

In every arm platform which is making use of them, mem_regions are
interpreted as a pair of start address and size. However arm
SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as
start address and end address. This patch is fixing this mismatch.

Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16205
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13609:adc3dd5e3384 25-Jan-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

configs: Enable DTB autogeneration in starter_fs.py

This patch is removing hardcoded default DTBs in favour of common DTB
autogeneration.

Change-Id: I68fdc2a169bfa8e8657c9ed4e4e127957a08cca1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15959
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13608:e91969b61d3d 25-Jan-2019 Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm, configs: Create single instance of DTB autogeneration

This patch is rewriting the DTB autogeneration functions available in
fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem
so that other configuration scripts can make use of it.

Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15958
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13606:2ad4449e6cb4 24-Jan-2019 Ciro Santilli <ciro.santilli@arm.com>

configs: fs.py remove --generate-dtb and enable it by default

The option is now enabled if neither --bare-metal nor --dtb-filename are
given.

This is what fs_bigLITTLE.py already did before this patch.

Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921
Reviewed-on: https://gem5-review.googlesource.com/c/15899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13605:8904f6c497e6 03-Dec-2018 Ciro Santilli <ciro.santilli@arm.com>

configs, arch-arm: don't search for default DTB and kernel

Before this commit, there were default magic DTB and kernel filenames
for some platforms.

This was inelegant and error prone, as it refered to out-of-tree files,
and set defaults which users almost always want to customize with
explicit command line options.

One result of this is that a wrong exception could be thrown if --kernel
was given but not --machine-type, since the default machine type
VExpress_EMM had a default kernel, and the code would always search for
the default filename even though --kernel was given:

IOError: Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path.

The defaults existed only for older machine types, and not for the
usually recommended VExpress_GEM5_V1, which suggests that this
deprecation should not affect many users.

Change-Id: Ia49298304f658701ea0800bd79e08db404a655c3
Reviewed-on: https://gem5-review.googlesource.com/c/15898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13532:b1cacf73cd4e 13-Nov-2018 Jairo Balart <jairo.balart@metempsy.com>

dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 support

Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7
Reviewed-on: https://gem5-review.googlesource.com/c/14255
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

13432:6ce67b7e6e44 07-Nov-2018 Pau Cabre <pau.cabre@metempsy.com>

configs: Added an option for choosing branch predictor type

Added the parameter "--bp-type" to set the branch predictor type
Added the parameter "--list-bp-types" to list all the available branch
predictor types

Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14015
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13408:f586d7fb4623 04-Oct-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Revamp ruby mem test to align with MemTest

The test script was broken as it was based on an older version of
MemTest, this changes revamps the creation of MemTest and removes
parameters that are not any longer valid.

Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13596
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13400:cf74d21e948f 07-Nov-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

configs: Add missing path to ruby imports

Add missing addToPath to ruby files, so that import
modules from previous folder are visible.

Change-Id: I912d78a2f709974f72fe768e73abac1617126f46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13995
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13357:110926e15f1f 13-Sep-2018 Ciro Santilli <ciro.santilli@arm.com>

config: add --param to fs.py, se.py and fs_bigLITTLE.py

The option allows to set SimObject params from the CLI.

The existing config scripts have a large number of options that simply set
a single SimObject parameter, and many still are not exposed.

This commit allows users to pass arbitrary parameters from the command
line to prevent the need for this kind of trivial option.

Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Reviewed-on: https://gem5-review.googlesource.com/c/12985
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13174:6d96125a657c 09-Oct-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

configs: Fix CPUClass typo in se.py

Change 719eb033fe435133abf15501c249eec10d1c861f added a typo
to se.py that breaks simpoint simulation, which generates the
following error:

Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/daniel/gem5/src/python/m5/main.py", line 435, in main
exec filecode in scope
File "./configs/example/se.py", line 217, in <module>
if not CpuConfig.is_atomic_cpu(TestCPUClass):
NameError: name 'TestCPUClass' is not defined

Change-Id: Ideede8c96a40ee16af733c3d57b02b64f1a18d12
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13267
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13167:258a04d4c20b 04-Sep-2018 Ciro Santilli <ciro.santilli@arm.com>

dev, arm: remove the RealViewEB platform

This is an old platform, and we haven't had official Linux kernel configs
for it in a while, so we've decided to deprecate it.

Furthermore, trying to use it fails with:

object 'RealViewEB' has no attribute 'pci_host'

and the last commit in the class happened two years ago, which indicates
that no one has been using it.

Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/12471
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13022:6c0f747b0c64 14-Sep-2018 Sherif Elhabbal <elhabbalsherif@gmail.com>

config, arm, power: Example to report the power for the L2 Cache

This patch add an example to demonstrate how to report the power for the L2
Cache of the big cluster separately ,it decouples the L2 contributions from
the CPU power equation

Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58
Reviewed-on: https://gem5-review.googlesource.com/12684
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

13015:9e48c6a83b85 30-Aug-2018 Ciro Santilli <ciro.santilli@arm.com>

config, dev-arm: Fix UART handling baremetal mode

fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform
due to inconsistent UART naming with error message:

AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'

Consistently name keep all UARTs in the Arm platforms in a vector named
'uart' or as a single device named 'uart'. Update the configuration
scripts to reflect the fact that 'uart' can be a vector.

Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12473
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

13012:5fbc6b9c64bc 15-Mar-2016 Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12976:125099a94768 30-Aug-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Use the same address ranges for dir and mem_ctrls

In Ruby, for every directory we create one memory controller for every
range in the memory ranges. Previously the memory controllers and the
directories created their address ranges independently and as a result
a mismatch was possible. In fact, we assinged an interleaved address
range with hasing for the memory controllers while the corresponding
directories would be assigned the same interleaved address range
without hashing.

This change uses the address range of the memory controllers to
populate the list of address ranges for the corresponding directory
and avoid bugs due to code duplication.

Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a
Reviewed-on: https://gem5-review.googlesource.com/12318
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12941:24771c7aee2e 28-Aug-2018 Andreas Sandberg <andreas.sandberg@arm.com>

config: Move KVM CPU checking to CpuConfig helper module

Both se.py and fs.py need to check if a CPU is a KVM CPU. This is
somewhat involved since CPUs can be disabled at compile time. Enable
better code reuse by moving it to the CpuConfig module.

Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12418
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12880:cb1fb179e8c8 21-Sep-2017 Jason Lowe-Power <jason@lowepower.com>

configs: Always exit with code 0

Update simulation.py to always exit with code 0 assuming the simulation
exits normally. If the running application has a return code that is non
zero, then print the return code before exiting.

Change-Id: I1983985d50311627574d4364b32ee961ae88e003
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4880

12814:074f6240ff4c 27-Apr-2018 Andreas Sandberg <andreas.sandberg@arm.com>

configs: Update the DRAM sweep script to use PyTrafficGen

Instead of generating a text configuration, use the new Python-based
traffic generator.

Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11519
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12726:850e9965525b 05-Feb-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

12697:cd71b966be1e 27-Apr-2018 Tony Gutierrez <anthony.gutierrez@amd.com>

style: fix amd license and style issues

Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5
Reviewed-on: https://gem5-review.googlesource.com/10463
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>


example/apu_se.py
ruby/MOESI_AMD_Base.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/mem/ruby/common/IntVec.cc
/gem5/src/mem/ruby/common/IntVec.hh
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.hh
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/sim/aux_vector.cc
/gem5/src/sim/aux_vector.hh
/gem5/src/sim/fd_array.cc
/gem5/src/sim/fd_array.hh
/gem5/src/sim/fd_entry.cc
/gem5/src/sim/fd_entry.hh
12647:6d7e2f321496 12-Apr-2018 Tony Gutierrez <anthony.gutierrez@amd.com>

configs, mem-ruby: fix issues with style in AMD license

fixes line length and white space issues.

Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3
Reviewed-on: https://gem5-review.googlesource.com/9801
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

12611:8c69b5670fbb 09-Mar-2018 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add a simple config for MI_example

Adds a new config script to configure the MI_example protocol. This script
closely follows the script used for MSI, but instead supports the
MI_example protocol. This script works with the simple_ruby runscript and
can be included instead of msi_caches.

Change-Id: I8be0be67bf51369763ba103a5f101cfc01ad8859
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8945
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12610:ce4e3b0639b2 09-Mar-2018 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Ruby random tester files for MSI

Adds a pair of scripts to run the Ruby random tester with the MSI protocol.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I15550a36618546f0354163b0216cf771f434ed84
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8944
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12609:72f3f62b4f38 09-Mar-2018 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add config files for MSI protocol

Adds the required configuration files to run the MSI protocol. These
config files are much simpler than the current Ruby examples and follow
the pattern in the other Learning gem5 run scripts.

By default, this script runs with two CPUs and runs the recently added
thread test binary.

Currently, only SE mode is supported.

This code follows Learning gem5 Part 3.
http://learning.gem5.org/book/part3/index.html

Change-Id: I813a3153d49e47198444c38a6af30269bd1310cd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8943
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12600:e670dd17c8cf 19-Feb-2018 Daniel R. Carvalho <odanrc@yahoo.com.br>

mem-cache: Split array indexing and replacement policies.

Replacement policies (LRU, Random) are currently considered as array
indexing methods, but have completely different functionalities:

- Array indexers determine the possible locations for block allocation.
This information is used to generate replacement candidates when
conflicts happen.
- Replacement policies determine which of the replacement candidates
should be evicted to make room for new allocations.

For this reason, they were split into different classes. Advantages:

- Easier and more straightforward to implement other replacement
policies (RRIP, LFU, ARC, ...)
- Allow easier future implementation of cache organization schemes

As now we can't assure the use of sets, the previous way to create a
true LRU is not viable. Now a timestamp_bits parameter controls how
many bits are dedicated for the timestamp, and a true LRU can be
achieved through an infinite number of bits (although a few bits suffice
in practice).

Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda
Reviewed-on: https://gem5-review.googlesource.com/8501
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

12598:b80b2d9a251b 12-Feb-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12579:b5385b9f9d3c 09-Mar-2018 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Update README for Learning gem5

Change-Id: I94485e401bc77207cab68c1e24ef7a6ed83bd43d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/8946
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

12564:2778478ca882 06-Mar-2018 Gabe Black <gabeblack@google.com>

config: Switch from the print statement to the print function.

Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0
Reviewed-on: https://gem5-review.googlesource.com/8762
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

12550:e33f0bfa3eda 05-Feb-2018 Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Fix L3Cache instantiation in lat_mem_rd.py

This changeset updates the lat_mem_rd.py to configure the L3Cache
using the split tag_latency, data_latency parameters.

Change-Id: I8bc41d5f7664111bdda0972356d1a17762aa77e5
Reviewed-on: https://gem5-review.googlesource.com/8288
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

12490:a98a4a21417a 04-Feb-2018 Nayan Deshmukh <nayan26deshmukh@gmail.com>

config: remove dead code in fs.py

We have not added the --generate-dtb option for non-ARM systems and
hence this case becomes dead code. It also leads to error on non-ARM
systems as is tries to access a non existent field.

Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/7801
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12476:a891137813ec 11-Sep-2017 Curtis Dunham <Curtis.Dunham@arm.com>

config, arm: enable device tree autogeneration for bigLITTLE

Change-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5969
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12475:c6a23d6370de 14-Mar-2016 Glenn Bergmans <glenn.bergmans@arm.com>

config: Embed Device Tree generation in fs.py config

Equips the fs.py config routine with an extra commandline option
--generate-dtb that will generate a dtb file automatically before
running the simulation. Only works with ARM systems and gives a warning
if the simulated system is not of --machine-type VExpress_GEM5_V1.

Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5968
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12430:11cb907bd81b 03-Jan-2018 Chen Zou <chenzou@uchicago.edu>

configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now

Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb
Reviewed-on: https://gem5-review.googlesource.com/7021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12418:340406d827e2 05-Jan-2018 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: call createThreads() on cpu objs in apu_se.py

commit 8ad26e2688b8736f9290086bb4026cc7500429e9
cpu: Don't override ISA if provided by user

removed the default ISA from the BaseCPU, and instead relies on
createThreads() to initiate a default ISA if none is specified. the apu_se.py
script, however does not call creatThreads() leading to a fatal when
constructing CPU objects. this patch adds the appropriate calls to
createThreads() inside apu_se.py.

Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412
Reviewed-on: https://gem5-review.googlesource.com/7101
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

12411:394fa4ecc018 21-Dec-2017 Gabe Black <gabeblack@google.com>

config: Handle NULL simobject parameters in read_config.py.

Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409
Reviewed-on: https://gem5-review.googlesource.com/6943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12410:184beca7f554 21-Dec-2017 Gabe Black <gabeblack@google.com>

config: Fix parsing AddrRange parameters in read_config.py.

The format of AddrRange parameters was changed, but
config/example/read_config.py wasn't updated for the new format.

Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794
Reviewed-on: https://gem5-review.googlesource.com/6942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12409:0435e2ab811a 14-Dec-2017 Gabe Black <gabeblack@google.com>

config: Add a --checkpoint-dir argument to read_config.py.

This argument lets the user restore a checkpoint after loading
simulator state from config.ini.

Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b
Reviewed-on: https://gem5-review.googlesource.com/6941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12395:322bb93e5f06 09-Nov-2017 Swapnil Haria <swapnilster@gmail.com>

mem-ruby: Support atomic_noncaching acceses in ruby

Ruby has no support for atomic_noncaching accesses, which prevents using
it with kvm-cpu. This patch fixes this by directly forwarding atomic
requests from the ruby port/sequencer to the corresponding directory
based on the destination address of the packet.

Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d
Reviewed-on: https://gem5-review.googlesource.com/5601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

12374:df27dd3da16d 02-Dec-2017 Austin Harris <austinharris@utexas.edu>

config: Fix need to set ISA of switch cpus.

Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa
parameter, switch_cpus should have the ISA copied. This fixes a
fatal error in BaseCPU when restoring from a checkpoint.

Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/6241
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12340:a52f6d327259 22-Nov-2017 Éder F. Zulian <zulian@eit.uni-kl.de>

config, mem, hmc: fix HMC test script

This patch keeps the logic behind the HMC model implementation untouched.

Additional changes:
- simple hello world script using HMC (SE simulation)

Usage examples:

./build/ARM/gem5.opt configs/example/hmctest.py
./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same
./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed
./build/ARM/gem5.opt configs/example/hmc_hello.py
./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor

Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394
Reviewed-on: https://gem5-review.googlesource.com/6061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12339:1141f798a210 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Adding code for SimpleCache

This is the rest of the code for part 2.

See http://learning.gem5.org/book/part2/simplecache.html

Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5023
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12338:ae907b0a57c2 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Adds the simple MemObject code

Adding more code from Learning gem5 Part II

See http://learning.gem5.org/book/part2/memoryobject.html

Change-Id: Iaa9480c5cdbe4090364f02e81dc1d0a0ddac392a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5022
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12337:97857a19fb72 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add code for hello-goodbye example

Adding more code from Learning gem5 Part II

See http://learning.gem5.org/book/part2/parameters.html

Change-Id: I9fe5655239e011c718c5cf5fd62bebcda66ea966
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5021
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

12336:9ead840035df 06-Oct-2017 Jason Lowe-Power <jason@lowepower.com>

learning_gem5: Add code for simple SimObject

This adds code from Learning gem5 Part II.

See http://learning.gem5.org/book/part2/helloobject.html

Change-Id: Ic2caa07876ca57f937729c27ce29b2cd8bf2380c
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5020
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

12268:54566b73dc61 16-Dec-2016 Radhika Jagtap <radhika.jagtap@arm.com>

tests: Add tests for DRAM low power modes

This patch adds two regression tests that execute the script in the
configs dir for triggering low power mode transitions. A separate
test is required for each page policy because for close-adaptive
page policy the DRAM goes into the Precharge Power-down mode while
for open-adaptive page policy it goes into the Activate Power-down
mode.

Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5726
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12267:e523442346c5 25-Nov-2016 Radhika Jagtap <radhika.jagtap@arm.com>

config: Add low power sweep for DRAM

This change adds a Python script to sweep a few parameters with a
goal to trigger transitions to the low power states of the DRAM
controller.

This script is largely based on the sweep.py but is helpful to study
the impact of inter-transaction delay on the behaviour of the DRAM
in addition to typical sweep params like stride size, bank
utilization and read percent. An idle period is added as the last
traffic generator state to target hitting self-refresh.

Change-Id: I34380afffbf2de9f4e997dfe9fff5e615e077524
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5725
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12254:e4b3baf80eb4 10-Nov-2017 Gabe Black <gabeblack@google.com>

config: Fix the "script" SysPath functor.

This particular functor looks in the config root, not in the path
specified by M5_ROOT like binary and disk.

Change-Id: Ib007c36934c65ca9f808e995a2e0c71f0b338788
Reviewed-on: https://gem5-review.googlesource.com/5641
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

12233:53cf2e32cb59 30-Oct-2017 Gabe Black <gabeblack@google.com>

config: Rework the SysPaths functions into functors.

These functions were already being treated as psuedo objects and had
properties assigned to them setting what their paths were. That's a bit
unusual and made it less obvious what the code was doing, but also
forced the "system" function to know what all the possible path
searching functions were so that they'd have their "path" property
initialized properly in a central location.

This change introduces a PathSearcFunc class which encapsulates the
mechanisms of the old code and makes it implicitly extensible so that
other path searching functions which might look in other directories
can be added in other places.

Change-Id: I7be28e51481a06ec83997677af99927709b18003
Reviewed-on: https://gem5-review.googlesource.com/5341
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12166:1e88ad5f1a47 03-Aug-2017 Andreas Sandberg <andreas.sandberg@arm.com>

configs, arm: Fix incorrect use of mem_range in bL example

The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.

Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12165:463d335724d7 20-Jul-2017 Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: Fix CPU names in ARM example configs

The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.

Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4360
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12153:dc6e9f6dfd9c 27-Jul-2017 Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Switch to DTOnly as the default machine type

Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.

Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12152:e44b42795fee 04-Jul-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Discover CPU timing models based on target ISA

The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.

Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.

Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12151:52ac7a63ca39 07-Jul-2017 Gabor Dozsa <gabor.dozsa@arm.com>

config, arm: SE configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4203
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12150:765558361fd6 05-Jul-2017 Gabor Dozsa <gabor.dozsa@arm.com>

config, arm: FS configuration for the ARM starter kit

Add a full system example configuration for the ARM Research Starter
Kit on System Modeling. More information can be found at:
http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
[ Minor cleanups and more documentation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12149:b87a60509a13 10-Jul-2017 Ashkan Tousi <ashkan.tousimojarad@arm.com>

config, arm: Add a high-performance in order timing model

The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling

Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12148:6d367c7fdb1d 05-Jul-2017 Gabor Dozsa <gabor.dozsa@arm.com>

config: Change mem_range attribute naming in ARM SimpleSystem

MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.

Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12146:bb4ca633cf1f 19-Jul-2017 Pau Cabre <pau.cabre@metempsy.com>

configs,sim-se: fix se.py multi-cpu multi-cmd issue

Assign different pids to the different commands specified with the "--cmd"
flag to configs/example/se.py

Without this change, the following command line triggers
a "fatal: _pid 100 is already used" error:

command=$PWD/tests/test-progs/hello/bin/arm/linux/hello
./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command"

Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4160
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

12109:f29e9c5418aa 05-Apr-2017 Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>

cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705


common/cores/arm/O3_ARM_v7a.py
/gem5/src/arch/SConscript
/gem5/src/arch/alpha/isa.hh
/gem5/src/arch/alpha/registers.hh
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/generic/ISACommon.py
/gem5/src/arch/generic/SConscript
/gem5/src/arch/generic/traits.hh
/gem5/src/arch/generic/types.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/isa.hh
/gem5/src/arch/mips/registers.hh
/gem5/src/arch/null/registers.hh
/gem5/src/arch/power/isa.hh
/gem5/src/arch/power/registers.hh
/gem5/src/arch/riscv/isa.hh
/gem5/src/arch/riscv/registers.hh
/gem5/src/arch/sparc/isa.hh
/gem5/src/arch/sparc/registers.hh
/gem5/src/arch/x86/isa.hh
/gem5/src/arch/x86/registers.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/exec_context.hh
/gem5/src/cpu/inst_res.hh
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/exec_context.hh
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/minor/scoreboard.hh
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/comm.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/dyn_inst.hh
/gem5/src/cpu/o3/free_list.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/regfile.cc
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/rename_map.cc
/gem5/src/cpu/o3/rename_map.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/reg_class.cc
/gem5/src/cpu/reg_class.hh
/gem5/src/cpu/reg_class_impl.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/exec_context.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.cc
/gem5/src/cpu/thread_context.hh
/gem5/src/sim/serialize.cc
12099:40bbc2917b8a 04-Jul-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config, arm: Don't import timing models for missing CPUs

When importing the cores.arm package, we currently throw an exception
if a timing model can't be imported due to a missing dependency (e.g.,
the required CPU model wasn't included in the build). This is
undesirable since it prevents other, working, timing models from being
added to the package. Wrap the import_module call in a try-except
block and skip timing models that have missing dependencies.

Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3946
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12098:6a2ac80ff671 26-Jun-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Clean up core timing model discovery

Instead of hard-coding timing models in CpuConfig.py, use
introspection to find them in the cores.arm model package.

Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3944
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12097:77a3d2890ba6 26-Jun-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Move core timing models to config/common/cores

Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12096:a5289d3657b3 26-Jun-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Make ex5_*.py independent of old configs

The ex5_LITTLE and ex5_big configs currently depend on Caches.py and
O3_ARM_v7a.py. These aren't actual dependencies since all of the
params from the caches and the old O3 model are overridden. This
changeset updates the ex5 models to derive from the base SimObjects
instead.

Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3942
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12095:07ec0befb9f1 26-Jun-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Add missing import of 'fatal' in CpuConfig

Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3941
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12094:81aba95c81f9 26-Jun-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config: Make some MemConfig options optional

MemConfig currently assumes that all callers include the its full set
of options in the command line parser. This is unnecessary and
sometimes confusing. Make most of the options optional to avoid having
to add all of them to example scripts.

Change-Id: I2d73be2454427b00db16716edcfd96a47133c888
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3940
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12079:a5cc6df83fcf 23-Feb-2017 Gedare Bloom <gedare@rtems.org>

configs, arm: add option to enable security extensions

Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c
Signed-off-by: Gedare Bloom <gedare@rtems.org>
Reviewed-on: https://gem5-review.googlesource.com/3264
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12072:2ee7f25dd00d 19-Apr-2017 Zhang Zheng <perise@gmail.com>

configs: fixed SimpleOpts missing error by adding library path

Change-Id: I0de761c8a322a506e436d5c7f12ee509535f52fd
Reviewed-on: https://gem5-review.googlesource.com/2801
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12067:9423cf8c1e87 06-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

config: Warn not fail for ARM systems configured with ruby

Ruby for ARM systems is not fully supported but certain configurations
are expected to work. This change removes the more general fail
statement and warns or fails depending on the particular
configuration.

Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2905
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

12066:a4fd03c9ca5a 04-Apr-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby, arm: Forward invalidations to the local exclusive monitor

ARM systems require local exclusive monitors for the implementation of
synchronization primitives between processors. A ruby memory system
needs to forward invalidations to the local exclusive monitors to
to correctly determine their state.

Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2904
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12065:e3e51756dfef 13-Mar-2017 Nikos Nikoleris <nikos.nikoleris@arm.com>

ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>


ruby/GPU_RfO.py
ruby/Garnet_standalone.py
ruby/MESI_Three_Level.py
ruby/MESI_Two_Level.py
ruby/MI_example.py
ruby/MOESI_AMD_Base.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Ruby.py
/gem5/src/base/addr_range.hh
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/Garnet_standalone-cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/slicc/symbols/Type.py
12029:f8b3a3bf4711 12-May-2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

configs: fix cpu names in big.LITTLE example

CPU aliases have been dropped, this change fixes the big.LITTLE example.

Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/3300
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12028:29ea3c7bc92f 22-Mar-2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

arm, config: added support for ex5 model of big.LITTLE

This patch enables using calibrated big and LITTLE cores, ex5_big and
ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5
model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory
hierarchy latencies have been calibrated using the lmbench micro-benchmark
suite. The preliminary validation results have been published as: 'Full-System
Simulation of big.LITTLE Multicore Architecture for Performance and Energy
Exploration', in International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016).

From http://reviews.gem5.org/r/3666

Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7
Signed-off-by: Anastasiia Butko <abutko@lbl.gov>
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2464
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

12026:1219d7a06a66 12-Jan-2017 Weiping Liao <weipingliao@google.com>

config: Changes to boot Android N

necessary kernel command line options in FSConfig.py

Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d
Reviewed-on: https://gem5-review.googlesource.com/3320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

12014:f973caaf935d 08-May-2017 Gabe Black <gabeblack@google.com>

config: Fix up some configs to not use CPU aliases.

Support for CPU aliases were removed recently.

Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f
Reviewed-on: https://gem5-review.googlesource.com/3100
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11995:d3dbd5a6b19a 27-Apr-2017 Gabe Black <gabeblack@google.com>

config: Remove support for CPU aliases.

This was added for backwards compatability, but it adds a decent amount
of complexity.

The table below shows what CPU class name to use in place of a given
alias.

+==========+========================================================+
| Alias | CPU class |
+==========+========================================================+
| timing | TimingSimpleCPU |
| atomic | AtomicSimpleCPU |
| minor | MinorCPU |
| detailed | DrivO3CPU |
| kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch |
| trace | TraceCPU |
+==========+========================================================+

Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08
Reviewed-on: https://gem5-review.googlesource.com/2940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11973:aa43e508ade4 05-Apr-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config, arm: Add an example power model

Add a script to demonstrate how power models can be wired to gem5
models. The script is meant as an example only and does not correlate
with any realistic implementation.

Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2721
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

11949:db6d68484756 03-Apr-2017 Gabe Black <gabeblack@google.com>

config: Add a default system disk image for SPARC FS.

When the change below removed the hard coded disk name for the SPARC FS
configuration, it broke the regression which had not specified a disk name.
This change adds a default disk name so that the regression will continue to
work like it used to, but preserving the effect of this other change.

commit 86a25bbcee88f6e69299867b6264885d738f636e
Author: Jakub Jermar <jakub@jermar.eu>
Date: Tue Jul 19 09:52:46 2016 -0500

config: Allow SPARC FS image to be specified on the command line

Change-Id: Ieb317b2bf573a4f2fc435d34cccd1f246c28d84c
Reviewed-on: https://gem5-review.googlesource.com/2645
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

11936:8ab45fd19f40 17-Mar-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config, arm: Add multi-core KVM support to bL config

Add support for KVM in the big.LITTLE(tm) example configuration. This
replaces the --atomic option with a --cpu-type option that can be used
to switch between atomic, kvm, and timing simulation.

When running in KVM mode, the simulation script automatically assigns
separate event queues (threads) to each of the simulated CPUs. All
simulated devices, including CPU child devices (e.g., interrupt
controllers and caches), are assigned to event queue 0.

Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2561
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>

11935:28290ed77b03 20-Mar-2017 Andreas Sandberg <andreas.sandberg@arm.com>

config, arm: Unify checkpoint path handling in bL configs

The vanilla bL configuration file and the dist-gem5 configuration file
use slightly different code paths when restoring from
checkpoints. Unify this by passing the parsed options to the
instantiate() method and adding an optional checkpoint keyword
argument for checkpoint directories (only used by the dist-gem5
script).

Change-Id: I9943ec10bd7a256465e29c8de571142ec3fbaa0e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>

11889:3e7a56472f08 23-Feb-2017 Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>

config: exit with fatal() if error

If output redirection is activated, the error message is printed in
simout. This change ensure it will be printed in simerr.

Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459
Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr>
Reviewed-on: https://gem5-review.googlesource.com/2221
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

11851:824055fe6b30 09-Nov-2016 Brandon Potter <brandon.potter@amd.com>

syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead

The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.


common/cpu2000.py
example/apu_se.py
example/se.py
learning_gem5/part1/simple.py
learning_gem5/part1/two_level.py
splash2/cluster.py
splash2/run.py
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/process.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/process.hh
/gem5/src/arch/arm/freebsd/process.cc
/gem5/src/arch/arm/freebsd/process.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/linux/process.hh
/gem5/src/arch/power/process.cc
/gem5/src/arch/power/process.hh
/gem5/src/arch/riscv/linux/process.cc
/gem5/src/arch/riscv/linux/process.hh
/gem5/src/arch/riscv/process.cc
/gem5/src/arch/riscv/process.hh
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/linux/process.cc
/gem5/src/arch/sparc/linux/process.hh
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/process.hh
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/solaris/process.hh
/gem5/src/arch/x86/linux/process.cc
/gem5/src/arch/x86/linux/process.hh
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/kern/freebsd/freebsd.hh
/gem5/src/kern/linux/linux.cc
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.cc
/gem5/src/kern/operatingsystem.hh
/gem5/src/sim/Process.py
/gem5/src/sim/emul_driver.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/syscall_desc.cc
/gem5/src/sim/syscall_desc.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/tests/long/se/10.mcf/test.py
/gem5/tests/long/se/20.parser/test.py
/gem5/tests/long/se/30.eon/test.py
/gem5/tests/long/se/40.perlbmk/test.py
/gem5/tests/long/se/50.vortex/test.py
/gem5/tests/long/se/60.bzip2/test.py
/gem5/tests/long/se/70.twolf/test.py
/gem5/tests/quick/se/00.hello.mp/test.py
/gem5/tests/quick/se/00.hello/test.py
/gem5/tests/quick/se/01.hello-2T-smt/test.py
/gem5/tests/quick/se/02.insttest/test.py
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/10.mcf/test.py
/gem5/tests/quick/se/30.eon/test.py
/gem5/tests/quick/se/40.m5threads-test-atomic/test.py
/gem5/tests/quick/se/50.vortex/test.py
/gem5/tests/quick/se/70.twolf/test.py
11845:afd6aaee268e 14-Feb-2017 Gabor Dozsa <gabor.dozsa@arm.com>

arm,config: Add dist-gem5 support to the big.LITTLE(tm) config

This patch extends the example big.LITTLE configuration to enable
dist-gem5 simulations of big.LITTLE systems.

Change-Id: I49c095ab3c737b6a082f7c6f15f514c269217756
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11844:d229654ff4c2 14-Feb-2017 Gabor Dozsa <gabor.dozsa@arm.com>

config: Refactor the network switch configuration file

This patch prevents the body of the script getting executed when
the script is imported as a module.

Change-Id: I70a50f6295f1e7a088398017f5fa9d06fe90476a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11843:9323db591b22 14-Feb-2017 Gabor Dozsa <gabor.dozsa@arm.com>

arm,config: Refactor the example big.LITTLE(tm) configuration

This patch prepares future extensions and customisation of the example
big.LITTLE configuration script. It breaks out the major phases into
functions so they can be called from other python scripts.

Change-Id: I2cb7c207c410fe14602cf17af7482719abba6c24
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11839:dd6df2e47c14 14-Feb-2017 Curtis Dunham <Curtis.Dunham@arm.com>

sim, kvm: make KvmVM a System parameter

A KVM VM is typically a child of the System object already, but for
solving future issues with configuration graph resolution, the most
logical way to keep track of this object is for it to be an actual
parameter of the System object.

Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11837:17b37f38944a 14-Feb-2017 Wendy Elsasser <wendy.elsasser@arm.com>

mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>


common/HMC.py
common/MemConfig.py
common/Options.py
dram/lat_mem_rd.py
dram/sweep.py
example/hmctest.py
example/memcheck.py
learning_gem5/part1/simple.py
learning_gem5/part1/two_level.py
/gem5/src/mem/DRAMCtrl.py
/gem5/tests/configs/minor-timing-mp.py
/gem5/tests/configs/minor-timing.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-mt.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/pc-switcheroo-full.py
/gem5/tests/configs/realview-minor-dual.py
/gem5/tests/configs/realview-minor.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/realview-switcheroo-full.py
/gem5/tests/configs/realview-switcheroo-o3.py
/gem5/tests/configs/realview-switcheroo-timing.py
/gem5/tests/configs/realview64-minor-dual.py
/gem5/tests/configs/realview64-minor.py
/gem5/tests/configs/realview64-o3-checker.py
/gem5/tests/configs/realview64-o3-dual.py
/gem5/tests/configs/realview64-o3.py
/gem5/tests/configs/realview64-simple-timing-dual.py
/gem5/tests/configs/realview64-simple-timing.py
/gem5/tests/configs/realview64-switcheroo-full.py
/gem5/tests/configs/realview64-switcheroo-o3.py
/gem5/tests/configs/realview64-switcheroo-timing.py
/gem5/tests/configs/tgen-dram-ctrl.py
/gem5/tests/configs/tsunami-minor-dual.py
/gem5/tests/configs/tsunami-minor.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/tsunami-switcheroo-full.py
11818:f12963cb9dc2 09-Feb-2017 Christian Menard <Christian.Menard@tu-dresden.de>

misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

11803:4f04a6593119 27-Jan-2017 Rahul Thakur <rjthakur@google.com>

mem: Add memory footprint probe

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

11790:f1ffedcf3b98 09-Jan-2017 Matthias Jung <jungma@eit.uni-kl.de>

config: Fix missing include in fs.py

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:


build/ARM/gem5.opt \
configs/example/fs.py \
--cpu-type=arm_detailed \
--num-cpu=1 \
--mem-type=SimpleMemory \
--mem-size=512MB \
--mem-channels=1 \
--caches \
--elastic-trace-en \
--data-trace-file=data.proto.gz \
--inst-trace-file=inst.proto.gz \
--machine-type=VExpress_EMM \
--dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
--kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
--disk-image=linux-aarch32-ael.img


NameError: global name 'CpuConfig' is not defined

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

11766:7c95caf53250 19-Dec-2016 Andreas Sandberg <andreas.sandberg@arm.com>

python: Export periodicStatDump

Some configuration scripts need periodic stat dumps. One of the ways
this can be achieved is by using the pariodicStatDump helper
function. This function was previously only exported in the internal
name space. Export it as a normal function in m5.stat instead.

Change-Id: Ic88bf1fd33042a62ab436d5944d8ed778264ac98
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>

11763:302c6b957854 19-Dec-2016 Andreas Sandberg <andreas.sandberg@arm.com>

sim: Remove redundant buildEnv import

Change-Id: Id6bdbc0c988aa92b96e292cabc913e6b974f14bb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>

11762:29d401db3746 15-Dec-2016 Jieming Yin <jieming.yin@amd.com>

ruby: Detect garnet network-level deadlock.

This patch detects garnet network deadlock by monitoring
network interfaces. If a network interface continuously
fails to allocate virtual channels for a message, a
possible deadlock is detected.

11756:0d38e56356c7 06-Dec-2016 Gabor Dozsa <gabor.dozsa@arm.com>

arm, config: Add missing IOCache in bL config

This patch adds an IOCache to the example bigLITTLE
configuration. An IOCache is required for correct DMA
transfers when we have caches in the system.

Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11753:6aefb19ff369 05-Dec-2016 Nikos Nikoleris <nikos.nikoleris@arm.com>

config: Add an option to generate a random topology in memcheck

This change adds the option to use the memcheck with random memory
hierarchies at the moment limited to a maximum depth of 3 allowing
testing with uncommon topologies.

Change-Id: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>

11752:e922938edf18 05-Dec-2016 Nikos Nikoleris <nikos.nikoleris@arm.com>

config: Add whole line accesses to improve memchecker's coverage

Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>

11722:f15f02d8c79e 30-Nov-2016 Sophiane Senni <sophiane.senni@gmail.com>

mem: Split the hit_latency into tag_latency and data_latency

If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

11703:08b78e0a3717 26-Oct-2016 Michael LeBeane <michael.lebeane@amd.com>

dev: Add m5 op to toggle synchronization for dist-gem5.
This patch adds the ability for an application to request dist-gem5 to begin/
end synchronization using an m5 op. When toggling on sync, all nodes agree
on the next sync point based on the maximum of all nodes' ticks. CPUs are
suspended until the sync point to avoid sending network messages until sync has
been enabled. Toggling off sync acts like a global execution barrier, where
all CPUs are disabled until every node reaches the toggle off point. This
avoids tricky situations such as one node hitting a toggle off followed by a
toggle on before the other nodes hit the first toggle off.

11700:7d4d424c9f17 26-Oct-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: support in-order data delivery in GM pipe

this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the buffer is implemented as
a stl ordered map, which sorts the request in program order by
using their sequence ID. when requests return to the GM pipeline
they are marked as done. only the oldest request may be serviced
from the ordered buffer, and only if is marked as done.

the FIFO response buffers are kept and used in OoO delivery mode

11688:725fef71f376 26-Oct-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Break out base options for usage with NULL ISA

This patch breaks out the most basic configuration options into a set
of base options, to allow them to be used also by scripts that do not
involve any ISA, and thus no actual CPUs or devices.

The patch also fixes a few modules so that they can be imported in a
NULL build, and avoid dragging in FSConfig every time Options is
imported.

11683:f1e198a028be 15-Oct-2016 Fernando Endo <fernando.endo2@gmail.com>

cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

11682:612f75cf36a0 14-Oct-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Make configs/common a Python package

Continue along the same line as the recent patch that made the
Ruby-related config scripts Python packages and make also the
configs/common directory a package.

All affected config scripts are updated (hopefully).

Note that this change makes it apparent that the current organisation
and naming of the config directory and its subdirectories is rather
chaotic. We mix scripts that are directly invoked with scripts that
merely contain convenience functions. While it is not addressed in
this patch we should follow up with a re-organisation of the
config structure, and renaming of some of the packages.


common/__init__.py
dist/sw.py
dram/lat_mem_rd.py
dram/sweep.py
example/apu_se.py
example/arm/devices.py
example/arm/fs_bigLITTLE.py
example/etrace_replay.py
example/fs.py
example/garnet_synth_traffic.py
example/hmctest.py
example/ruby_direct_test.py
example/ruby_gpu_random_test.py
example/ruby_mem_test.py
example/ruby_random_test.py
example/se.py
learning_gem5/part1/caches.py
learning_gem5/part1/two_level.py
ruby/Ruby.py
splash2/cluster.py
splash2/run.py
/gem5/tests/configs/alpha_generic.py
/gem5/tests/configs/arm_generic.py
/gem5/tests/configs/base_config.py
/gem5/tests/configs/checkpoint.py
/gem5/tests/configs/gpu-randomtest-ruby.py
/gem5/tests/configs/gpu-ruby.py
/gem5/tests/configs/learning-gem5-p1-two-level.py
/gem5/tests/configs/memtest-filter.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mt.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview64-o3-checker.py
/gem5/tests/configs/realview64-o3-dual.py
/gem5/tests/configs/realview64-o3.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/switcheroo.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
/gem5/tests/configs/x86_generic.py
11670:6ce719503eae 13-Oct-2016 Andreas Hansson <andreas.hansson@arm.com>

ruby: Fix regressions and make Ruby configs Python packages

This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.

11669:220fa4099b9a 07-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: fix typo in cluster topology.

11666:10d59d546ea2 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.


network/Network.py
topologies/Crossbar.py
topologies/MeshDirCorners_XY.py
topologies/Mesh_XY.py
topologies/Mesh_westfirst.py
topologies/Pt2Pt.py
/gem5/src/base/statistics.cc
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/garnet2.0/CommonTypes.hh
/gem5/src/mem/ruby/network/garnet2.0/Credit.cc
/gem5/src/mem/ruby/network/garnet2.0/Credit.hh
/gem5/src/mem/ruby/network/garnet2.0/CreditLink.hh
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.cc
/gem5/src/mem/ruby/network/garnet2.0/CrossbarSwitch.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.cc
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetLink.py
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/InputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet2.0/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet2.0/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.cc
/gem5/src/mem/ruby/network/garnet2.0/OutVcState.hh
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/OutputUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/README.txt
/gem5/src/mem/ruby/network/garnet2.0/Router.cc
/gem5/src/mem/ruby/network/garnet2.0/Router.hh
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.cc
/gem5/src/mem/ruby/network/garnet2.0/RoutingUnit.hh
/gem5/src/mem/ruby/network/garnet2.0/SConscript
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.cc
/gem5/src/mem/ruby/network/garnet2.0/SwitchAllocator.hh
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.cc
/gem5/src/mem/ruby/network/garnet2.0/VirtualChannel.hh
/gem5/src/mem/ruby/network/garnet2.0/flit.cc
/gem5/src/mem/ruby/network/garnet2.0/flit.hh
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet2.0/flitBuffer.hh
11664:2365e9e396f7 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.

11663:cf870cd20cfc 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.

11662:004d34b65092 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

config: add a separate config file for the network.
This patch adds a new file configs/network/Network.py to setup the network,
instead of doing that within Ruby.py.

11661:2bc3962f59fe 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: rename networktest to garnet_synthetic_traffic.
networktest is essentially a collection of synthetic traffic patterns
for the network. The protocol name and the tester having the same name
led to multiple python configuration files with the same name, adding
confusion. This patch renames networktest to garnet_synthetic_traffic,
and also adds more synthetic traffic patterns.

11660:cfa97c37117a 06-Oct-2016 Tushar Krishna <tushar@ece.gatech.edu>

ruby: rename ALPHA_Network_test protocol to Garnet_standalone.
Over the past 6 years, we realized that the protocol is essentially used
to run the garnet network in a standalone manner, and feed standard synthetic
traffic patterns through it.

11656:02a0c6b9c057 04-Oct-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Fix lat_mem_rd example script

Adjust the traffic generator time-out so that the script works out of
the box

Change-Id: I6b3b6b11f98b094ae3acdbe09488c26e4aeb0ab4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11630:6e2408ad4425 15-Sep-2016 Gabor Dozsa <gabor.dozsa@arm.com>

arm, config: Fixups for the example big.LITTLE(tm) configuration

This patch refactors the configuration file to use a more
object-oriented design.

Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>

11626:c89c72b0e5f5 13-Sep-2016 Michael LeBeane <michael.lebeane@amd.com>

config: move dist-gem5 options to common config
dist-gem5 should not be restricted to FullSystem mode.

11616:d726d0cea027 22-Aug-2016 David Hashe <david.j.hashe@gmail.com>

config: KVM acceleration for apu_se.py

Add support for using KVM to accelerate APU simulations. The intended use
case is to fast-forward through runtime initialization until the first
kernel launch.

11604:b254396b7759 12-Aug-2016 Andreas Hansson <andreas.hansson@arm.com>

mem: Add snoop filter to SystemXBar by default

This patch changes the default behaviour of the SystemXBar, adding a
snoop filter. With the recent updates to the snoop filter allocation
behaviour this change no longer causes problems for the regressions
without caches.

Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>

11599:55bd18998b7c 10-Aug-2016 Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: Exit with fatal error if using Ruby

Ruby on ARM is currently very experimental. Fail with a fatal error
that explains this to make sure users are aware of the limitations (it
doesn't actually work yet!).

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

11598:e0ddee91eb13 10-Aug-2016 Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: Add initial support for Ruby

Add initial support for creating an ARM system with a Ruby-based
memory system. This support is currently experimental and limited to
the new VExpress_GEM5_V1 platform.

Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>

11596:329e49c419b1 10-Aug-2016 Andreas Sandberg <andreas.sandberg@arm.com>

ruby: Implement support for functional accesses to PIO ranges

There are cases where we want to put boot ROMs on the PIO bus. Ruby
currently doesn't support functional accesses to such memories since
functional accesses are always assumed to go to physical memory. Add
the required support for routing functional accesses to the PIO bus.

Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>

11569:2eae1dfaa791 21-Jul-2016 Gabor Dozsa <gabor.dozsa@arm.com>

arm, config: Add an example ARM big.LITTLE(tm) configuration script

An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

11563:1040cd2252d4 19-Jul-2016 Jakub Jermar <jakub@jermar.eu>

config: Allow SPARC FS image to be specified on the command line

At the moment the SPARC FS machine configuration comes with a hardcoded
value for using the Solaris 10 disk image from the OpenSPARC tarball. The
--disk-image option is completely ignored for SPARC. This simple patch
modifies the behavior so that --disk-image option is both taken into
account and also required. This makes it possible to easily change SPARC FS
images without having to modify the configuration files.

11552:354e5631a6c1 01-Jul-2016 Abdul Mutaal Ahmad <abdul.mutaal@gmail.com>

mem: tester for new HMC configuration

This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.

Committed by Jason Lowe-Power <jason@lowepower.com>

11551:d24ad08b22b0 01-Jul-2016 Abdul Mutaal Ahmad <abdul.mutaal@gmail.com>

mem: different HMC configuration

In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>

11539:de57dbf319d0 20-Jun-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Fix omission of walker cache in config scripts

This patch ensures a walker cache is instantiated if specfied.

Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>

11534:7106f550afad 09-Jun-2016 jkalamat <john.kalamatianos@amd.com>

gpu-compute: parametrize Wavefront size

Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.

11501:9345c4320477 27-May-2016 Stephan Diestelhorst <stephan.diestelhorst@arm.com>

mem, config: Selective use of snoop filter

Disable the default snoop filter in the SystemXBar so that the
typical membus does not have a snoop filter by default. Instead,
add the snoop filter only when there are caches added to the system
(with the caches / l2cache options).

The underlying problem is that the snoop filter grows without
bounds (for now) if there are no caches to tell it that lines have
been evicted. This causes slow regression runs for all the atomic
regressions. This patch fixes this behaviour.

11481:fc247b9c42b6 19-May-2016 Bjoern A. Zeeb <baz21@cam.ac.uk>

config, x86: Properly space pad the X86IntelMPBus Entry descriptions

According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.

(*) http://www.intel.com/design/pentium/datashts/24201606.pdf

Committed by Jason Lowe-Power <power.jg@gmail.com>

11451:082f25c02518 21-Apr-2016 Andreas Hansson <andreas.hansson@arm.com>

config: Add missing point of coherency to memcheck script

Bring in line with changes to the XBar class.

11444:219c5fe8fa0e 14-Apr-2016 Mohammad Alian <m.alian1369@gmail.com>

dist: config file for distributed switch

Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.

11368:2fd64ea0a7cb 08-Mar-2016 Andreas Hansson <andreas.hansson@arm.com>

configs: Add a lat_mem_rd style test script

This patch adds a config script that broadly replicates the behaviour
of lat_mem_rd. The test is based on traffic generators, and as such we
simply randomise addresses in increasingly large ranges, and play them
back using the trace functionality of the traffic generator.

The test script is accompanied by a post-processing and visualisation
script. At the moment no configurability is added to tweak the memory
hierarchy, but a follow on patch could easily extend the
functionality.

11334:9bd2e84abdca 10-Feb-2016 Andreas Hansson <andreas.hansson@arm.com>

mem: Move the point of coherency to the coherent crossbar

This patch introduces the ability of making the coherent crossbar the
point of coherency. If so, the crossbar does not forward packets where
a cache with ownership has already committed to responding, and also
does not forward any coherency-related packets that are not intended
for a downstream memory controller. Thus, invalidations and upgrades
are turned around in the crossbar, and the memory controller only sees
normal reads and writes.

In addition this patch moves the express snoop promotion of a packet
to the crossbar, thus allowing the downstream cache to check the
express snoop flag (as it should) for bypassing any blocking, rather
than relying on whether a cache is responding or not.

11331:cd5c48db28e6 10-Feb-2016 Andreas Hansson <andreas.hansson@arm.com>

mem: Deduce if cache should forward snoops

This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.

The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement

11320:42ecb523c64a 06-Feb-2016 Steve Reinhardt <steve.reinhardt@amd.com>

style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.


common/CacheConfig.py
common/Simulation.py
example/ruby_mem_test.py
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/process.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/formats/pred.isa
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/power/SConscript
/gem5/src/arch/sparc/interrupts.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/pagetable.hh
/gem5/src/arch/x86/cpuid.cc
/gem5/src/arch/x86/faults.cc
/gem5/src/arch/x86/insts/micromediaop.hh
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/isa/insts/romutil.py
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py
/gem5/src/arch/x86/isa/microops/base.isa
/gem5/src/arch/x86/isa/microops/mediaop.isa
/gem5/src/arch/x86/isa/microops/regop.isa
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/process.hh
/gem5/src/base/cp_annotate.cc
/gem5/src/base/cp_annotate.hh
/gem5/src/base/cprintf.hh
/gem5/src/base/flags.hh
/gem5/src/base/inet.cc
/gem5/src/base/inet.hh
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/statistics.cc
/gem5/src/cpu/o3/decode_impl.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/networktest/networktest.cc
/gem5/src/cpu/timebuf.hh
/gem5/src/dev/mc146818.cc
/gem5/src/dev/net/i8254xGBe.cc
/gem5/src/dev/net/i8254xGBe.hh
/gem5/src/dev/net/i8254xGBe_defs.hh
/gem5/src/dev/x86/i8042.cc
/gem5/src/dev/x86/i8254.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/mport.hh
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.cc
/gem5/src/mem/ruby/network/fault_model/FaultModel.hh
/gem5/src/mem/ruby/network/fault_model/FaultModel.py
/gem5/src/mem/ruby/network/fault_model/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/simple/SimpleLink.cc
/gem5/src/mem/slicc/ast/StallAndWaitStatementAST.py
/gem5/src/mem/slicc/ast/TypeFieldEnumAST.py
/gem5/src/mem/slicc/ast/TypeFieldStateAST.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/swig/event.i
/gem5/src/sim/Root.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/unittest/cprintftest.cc
/gem5/system/alpha/console/console.c
/gem5/tests/configs/memtest-ruby.py
/gem5/util/checkpoint-tester.py
/gem5/util/compile
/gem5/util/m5/m5.c
/gem5/util/qdo
/gem5/util/statetrace/SConstruct
11310:b4bbf540d1a7 22-Jan-2016 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: changed all references to numCPs to num-cp

11308:7d8836fd043d 19-Jan-2016 Tony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: AMD's baseline GPU model


/gem5/SConstruct
/gem5/build_opts/HSAIL_X86
/gem5/build_opts/X86_MOESI_AMD_Base
common/GPUTLBConfig.py
common/GPUTLBOptions.py
example/apu_se.py
example/ruby_gpu_random_test.py
ruby/AMD_Base_Constructor.py
ruby/GPU_RfO.py
ruby/GPU_VIPER.py
ruby/GPU_VIPER_Baseline.py
ruby/GPU_VIPER_Region.py
ruby/MOESI_AMD_Base.py
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/hsail/Brig.h
/gem5/src/arch/hsail/Brig_new.hpp
/gem5/src/arch/hsail/SConscript
/gem5/src/arch/hsail/SConsopts
/gem5/src/arch/hsail/gen.py
/gem5/src/arch/hsail/generic_types.cc
/gem5/src/arch/hsail/generic_types.hh
/gem5/src/arch/hsail/gpu_decoder.hh
/gem5/src/arch/hsail/gpu_types.hh
/gem5/src/arch/hsail/insts/branch.cc
/gem5/src/arch/hsail/insts/branch.hh
/gem5/src/arch/hsail/insts/decl.hh
/gem5/src/arch/hsail/insts/gpu_static_inst.cc
/gem5/src/arch/hsail/insts/gpu_static_inst.hh
/gem5/src/arch/hsail/insts/main.cc
/gem5/src/arch/hsail/insts/mem.cc
/gem5/src/arch/hsail/insts/mem.hh
/gem5/src/arch/hsail/insts/mem_impl.hh
/gem5/src/arch/hsail/insts/pseudo_inst.cc
/gem5/src/arch/hsail/operand.cc
/gem5/src/arch/hsail/operand.hh
/gem5/src/gpu-compute/GPU.py
/gem5/src/gpu-compute/LdsState.py
/gem5/src/gpu-compute/SConscript
/gem5/src/gpu-compute/X86GPUTLB.py
/gem5/src/gpu-compute/brig_object.cc
/gem5/src/gpu-compute/brig_object.hh
/gem5/src/gpu-compute/cl_driver.cc
/gem5/src/gpu-compute/cl_driver.hh
/gem5/src/gpu-compute/cl_event.hh
/gem5/src/gpu-compute/code_enums.hh
/gem5/src/gpu-compute/compute_unit.cc
/gem5/src/gpu-compute/compute_unit.hh
/gem5/src/gpu-compute/condition_register_state.cc
/gem5/src/gpu-compute/condition_register_state.hh
/gem5/src/gpu-compute/dispatcher.cc
/gem5/src/gpu-compute/dispatcher.hh
/gem5/src/gpu-compute/exec_stage.cc
/gem5/src/gpu-compute/exec_stage.hh
/gem5/src/gpu-compute/fetch_stage.cc
/gem5/src/gpu-compute/fetch_stage.hh
/gem5/src/gpu-compute/fetch_unit.cc
/gem5/src/gpu-compute/fetch_unit.hh
/gem5/src/gpu-compute/global_memory_pipeline.cc
/gem5/src/gpu-compute/global_memory_pipeline.hh
/gem5/src/gpu-compute/gpu_dyn_inst.cc
/gem5/src/gpu-compute/gpu_dyn_inst.hh
/gem5/src/gpu-compute/gpu_exec_context.cc
/gem5/src/gpu-compute/gpu_exec_context.hh
/gem5/src/gpu-compute/gpu_static_inst.cc
/gem5/src/gpu-compute/gpu_static_inst.hh
/gem5/src/gpu-compute/gpu_tlb.cc
/gem5/src/gpu-compute/gpu_tlb.hh
/gem5/src/gpu-compute/hsa_code.hh
/gem5/src/gpu-compute/hsa_kernel_info.hh
/gem5/src/gpu-compute/hsa_object.cc
/gem5/src/gpu-compute/hsa_object.hh
/gem5/src/gpu-compute/hsail_code.cc
/gem5/src/gpu-compute/hsail_code.hh
/gem5/src/gpu-compute/kernel_cfg.cc
/gem5/src/gpu-compute/kernel_cfg.hh
/gem5/src/gpu-compute/lds_state.cc
/gem5/src/gpu-compute/lds_state.hh
/gem5/src/gpu-compute/local_memory_pipeline.cc
/gem5/src/gpu-compute/local_memory_pipeline.hh
/gem5/src/gpu-compute/misc.hh
/gem5/src/gpu-compute/ndrange.hh
/gem5/src/gpu-compute/of_scheduling_policy.cc
/gem5/src/gpu-compute/of_scheduling_policy.hh
/gem5/src/gpu-compute/pool_manager.cc
/gem5/src/gpu-compute/pool_manager.hh
/gem5/src/gpu-compute/qstruct.hh
/gem5/src/gpu-compute/rr_scheduling_policy.cc
/gem5/src/gpu-compute/rr_scheduling_policy.hh
/gem5/src/gpu-compute/schedule_stage.cc
/gem5/src/gpu-compute/schedule_stage.hh
/gem5/src/gpu-compute/scheduler.cc
/gem5/src/gpu-compute/scheduler.hh
/gem5/src/gpu-compute/scheduling_policy.hh
/gem5/src/gpu-compute/scoreboard_check_stage.cc
/gem5/src/gpu-compute/scoreboard_check_stage.hh
/gem5/src/gpu-compute/shader.cc
/gem5/src/gpu-compute/shader.hh
/gem5/src/gpu-compute/simple_pool_manager.cc
/gem5/src/gpu-compute/simple_pool_manager.hh
/gem5/src/gpu-compute/tlb_coalescer.cc
/gem5/src/gpu-compute/tlb_coalescer.hh
/gem5/src/gpu-compute/vector_register_file.cc
/gem5/src/gpu-compute/vector_register_file.hh
/gem5/src/gpu-compute/vector_register_state.cc
/gem5/src/gpu-compute/vector_register_state.hh
/gem5/src/gpu-compute/wavefront.cc
/gem5/src/gpu-compute/wavefront.hh
/gem5/src/mem/protocol/GPU_RfO-SQC.sm
/gem5/src/mem/protocol/GPU_RfO-TCC.sm
/gem5/src/mem/protocol/GPU_RfO-TCCdir.sm
/gem5/src/mem/protocol/GPU_RfO-TCP.sm
/gem5/src/mem/protocol/GPU_RfO.slicc
/gem5/src/mem/protocol/GPU_VIPER-SQC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER-TCP.sm
/gem5/src/mem/protocol/GPU_VIPER.slicc
/gem5/src/mem/protocol/GPU_VIPER_Baseline.slicc
/gem5/src/mem/protocol/GPU_VIPER_Region-TCC.sm
/gem5/src/mem/protocol/GPU_VIPER_Region.slicc
/gem5/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-dir.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-msg.sm
/gem5/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
/gem5/src/mem/protocol/MOESI_AMD_Base.slicc
/gem5/src/mem/protocol/RubySlicc_ComponentMapping.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/protocol/SConsopts
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/RubyCache.py
/gem5/src/mem/ruby/system/GPUCoalescer.cc
/gem5/src/mem/ruby/system/GPUCoalescer.hh
/gem5/src/mem/ruby/system/GPUCoalescer.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.cc
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/VIPERCoalescer.cc
/gem5/src/mem/ruby/system/VIPERCoalescer.hh
/gem5/src/mem/ruby/system/VIPERCoalescer.py
/gem5/src/mem/ruby/system/WeightedLRUPolicy.cc
/gem5/src/mem/ruby/system/WeightedLRUPolicy.hh
/gem5/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/tests/SConscript
/gem5/tests/configs/gpu-randomtest-ruby.py
/gem5/tests/configs/gpu-ruby.py
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout
/gem5/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt
/gem5/tests/quick/se/04.gpu/test.py
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout
/gem5/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt
/gem5/tests/quick/se/60.gpu-randomtest/test.py
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello
/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm
/gem5/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl
/gem5/tests/test-progs/gpu-hello/src/gpu-hello.cpp
/gem5/util/regress
11297:d1f8610cdffd 15-Jan-2016 Andreas Sandberg <andreas.sandberg@arm.com>

dev, arm: Add a platform with support for both aarch32 and aarch64

Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:

* Automatic PCI interrupt assignment
* PCI interrupts allocated in a contiguous range.
* Automatic boot loader selection (32-bit / 64-bit)
* Cleaner memory map where gem5-specific devices live in CS5 which
isn't used by current Versatile Express platforms.
* No fake devices. Devices that were previously faked will be
removed from the device tree instead.
* Support for 510 GiB contiguous memory

11292:5d1d5bf9c178 11-Jan-2016 Andreas Hansson <andreas.hansson@arm.com>

configs: Fix inheritance of HMCSystem and cleanup spacing

Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.

11291:9d2364203316 07-Jan-2016 Gabor Dozsa <gabor.dozsa@arm.com>

config: Updates for distributed gem5 simulations

11272:744e6074f6ae 17-Dec-2015 Andreas Hansson <andreas.hansson@arm.com>

configs: Make the default memtest behaviour more complex

Add functional and uncacheable accesses by default.

11266:452e10b868ea 20-Jul-2015 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: more flexible ruby tester support

This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests. This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code. Finally, the patch also includes better DPRINTFs for
debugging the tester.

11251:a15c86af004a 07-Dec-2015 Radhika Jagtap <radhika.jagtap@ARM.com>

config: Enable elastic trace capture and replay in se/fs

This patch adds changes to the configuration scripts to support elastic
tracing and replay.

The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.

The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.

11244:a2af58a06c4e 04-Dec-2015 Andreas Sandberg <andreas.sandberg@arm.com>

dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.

* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.

* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.

11238:627dd43a5846 03-Dec-2015 Andreas Sandberg <andreas.sandberg@arm.com>

arm, config: Automatically discover available platforms

Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.

11228:021524c21cbc 22-Nov-2015 Andrew Bardsley <Andrew.Bardsley@arm.com>

config: Added missing types to JSON/INI Python reader

Added the missing types EthernetAddr and Current to the JSON/INI file
reader example configs/example/read_config.py.

Also added __str__ to EthernetAddr to make values appear in the same form
in JSON an INI files.

11223:2981e399c816 22-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Minor fixes to the DRAM utilisation sweep

11200:6ef7d715d583 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Update memtest to stress test clean writebacks

This patch adds yet another twist to the memtest cache hierarchy, in that
the writeback_clean option is toggled at every level to match the
clusivity of the downstream cache.

11199:929fd978ab4e 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Add an option to perform clean writebacks from caches

This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.

The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.

The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py

11198:8149b36b8803 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Update memtest to stress test cache clusivity

This patch adds an new twist to the memtest cache hierarchy, in that
it switches from mostly inclusive to mostly exclusive at every level
in the tree. This has helped weed out plenty issues, and serves as a
good stress tests.

11197:f8fdd931e674 06-Nov-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Add cache clusivity

This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.

The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.

This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.

Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.

The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).

11187:854e61d5390e 04-Nov-2015 Nilay Vaish <nilay@cs.wisc.edu>

configs: fix bug introduced due to 276ad9121192

I had made a typo in changeset 276ad9121192. This changeset fixes it

11183:276ad9121192 03-Nov-2015 Erfan Azarkhish <erfan.azarkhish@unibo.it>

mem: hmc: top level design

This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It
highly reuses the existing components in gem5's general memory system with some
small modifications. This changeset requires additional patches to model a
complete HMC device.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

11182:fa8b2a99d4fe 03-Nov-2015 Palle Lyckegaard <palle@lyckegaard.dk>

sparc: add missing parameter to makeSparcSystem()

makeSparcSystem() in configs/common/FSConfig.py is missing the cmdLine
parameter Without the parameter the simulation fails to start. With the
parameter the simulation starts properly.

11172:9261e98e4501 14-Oct-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: provide the number of vnets through ruby system

The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().

11154:fce93f1c885b 01-Oct-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Fix 'learning gem5' configs after SMT push

This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.

11150:a8a64cca231b 30-Sep-2015 Mitch Hayenga <mitch.hayenga@arm.com>

isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.

11147:cc8d6e99cf46 30-Sep-2015 Mitch Hayenga <mitch.hayenga@arm.com>

config,cpu: Add SMT support to Atomic and Timing CPUs

Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.

11125:f918d72dbc02 25-Sep-2015 Andreas Hansson <andreas.hansson@arm.com>

util: Fix minor issues in DRAM sweep scripts

This patch fixes a few issues in the sweep scripts, bringing them
up-to-date with the latest memory configs and options.

11104:2d537040a4b9 16-Sep-2015 Jason Lowe-Power <power.jg@gmail.com>

config: Add configs scripts used in Learning gem5

Added a new directory in configs (learning_gem5) to hold the scripts that are
used in the book. See http://lowepower.com/jason/learning_gem5/ for a working
copy. For now, only the scripts in Part 1: Getting started with gem5
have been added. A separate patch adds tests for these scripts.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

11088:d322dd2e2b2d 07-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

config: allow ruby to be used with Minor CPU

11074:2763a59c73ff 01-Sep-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove random seed
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.

11065:37e19af67f62 30-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed. Each protocol
should now specify the value it needs.

11053:62544e45c0f4 21-Aug-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Add explicit Cache subclass and make BaseCache abstract

Open up for other subclasses to BaseCache and transition to using the
explicit Cache subclass.

11052:3137d34acf29 21-Aug-2015 Andreas Hansson <andreas.hansson@arm.com>

ruby: Move Rubys cache class from Cache.py to RubyCache.py

This patch serves to avoid name clashes with the classic cache. For
some reason having two 'SimObject' files with the same name creates
problems.

11049:dfb0aa3f0649 19-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: reverts to changeset: bf82f1f7b040


ruby/Ruby.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/common/DataBlock.hh
/gem5/src/mem/ruby/common/Histogram.cc
/gem5/src/mem/ruby/common/Histogram.hh
/gem5/src/mem/ruby/common/SubBlock.cc
/gem5/src/mem/ruby/common/SubBlock.hh
/gem5/src/mem/ruby/common/TypeDefines.hh
/gem5/src/mem/ruby/filters/H3BloomFilter.cc
/gem5/src/mem/ruby/filters/H3BloomFilter.hh
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.cc
/gem5/src/mem/ruby/filters/MultiBitSelBloomFilter.hh
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/network/MessageBuffer.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/profiler/AccessTraceForAddress.hh
/gem5/src/mem/ruby/profiler/AddressProfiler.cc
/gem5/src/mem/ruby/profiler/AddressProfiler.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/StoreTrace.cc
/gem5/src/mem/ruby/profiler/StoreTrace.hh
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
/gem5/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.cc
/gem5/src/mem/ruby/structures/AbstractReplacementPolicy.hh
/gem5/src/mem/ruby/structures/BankedArray.cc
/gem5/src/mem/ruby/structures/BankedArray.hh
/gem5/src/mem/ruby/structures/CacheMemory.cc
/gem5/src/mem/ruby/structures/CacheMemory.hh
/gem5/src/mem/ruby/structures/DirectoryMemory.cc
/gem5/src/mem/ruby/structures/DirectoryMemory.hh
/gem5/src/mem/ruby/structures/LRUPolicy.cc
/gem5/src/mem/ruby/structures/LRUPolicy.hh
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.cc
/gem5/src/mem/ruby/structures/PseudoLRUPolicy.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/CacheRecorder.cc
/gem5/src/mem/ruby/system/CacheRecorder.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/EnumDeclAST.py
/gem5/src/mem/slicc/ast/FormalParamAST.py
/gem5/src/mem/slicc/ast/FuncCallExprAST.py
/gem5/src/mem/slicc/ast/FuncDeclAST.py
/gem5/src/mem/slicc/ast/InPortDeclAST.py
/gem5/src/mem/slicc/ast/MethodCallExprAST.py
/gem5/src/mem/slicc/ast/StateDeclAST.py
/gem5/src/mem/slicc/parser.py
/gem5/src/mem/slicc/symbols/Func.py
/gem5/src/mem/slicc/symbols/StateMachine.py
11046:0cd13910b063 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: profiler: provide the number of vnets through ruby system

The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().

11041:d3bae341e151 14-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove random seed

We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng. So setting the random seed for
the RubySystem class has no effect. Hence the variable and the corresponding
option are being dropped.

11022:e6e3b7097810 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Protocol changes for SimObject MessageBuffers

11021:e8a6637afa4c 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Expose MessageBuffers as SimObjects

Expose MessageBuffers from SLICC controllers as SimObjects that can be
manipulated in Python. This patch has numerous benefits:
1) First and foremost, it exposes MessageBuffers as SimObjects that can be
manipulated in Python code. This allows parameters to be set and checked in
Python code to avoid obfuscating parameters within protocol files. Further, now
as SimObjects, MessageBuffer parameters are printed to config output files as a
way to track parameters across simulations (e.g. buffer sizes)

2) Cleans up special-case code for responseFromMemory buffers, and aligns their
instantiation and use with mandatoryQueue buffers. These two special buffers
are the only MessageBuffers that are exposed to components outside of SLICC
controllers, and they're both slave ends of these buffers. They should be
exposed outside of SLICC in the same way, and this patch does it.

3) Distinguishes buffer-specific parameters from buffer-to-network parameters.
Specifically, buffer size, randomization, ordering, recycle latency, and ports
are all specific to a MessageBuffer, while the virtual network ID and type are
intrinsics of how the buffer is connected to network ports. The former are
specified in the Python object, while the latter are specified in the
controller *.sm files. Unlike buffer-specific parameters, which may need to
change depending on the simulated system structure, buffer-to-network
parameters can be specified statically for most or all different simulated
systems.

11019:fc1e41e88fd3 14-Aug-2015 Joel Hestness <jthestness@gmail.com>

ruby: Remove the RubyCache/CacheMemory latency

The RubyCache (CacheMemory) latency parameter is only used for top-level caches
instantiated for Ruby coherence protocols. However, the top-level cache hit
latency is assessed by the Sequencer as accesses flow through to the cache
hierarchy. Further, protocol state machines should be enforcing these cache hit
latencies, but RubyCaches do not expose their latency to any existng state
machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter
is superfluous for all caches. This is confusing for users.

As a step toward pushing L0/L1 cache hit latency into the top-level cache
controllers, move their latencies out of the RubyCache declarations and over to
their Sequencers. Eventually, these Sequencer parameters should be exposed as
parameters to the top-level cache controllers, which should assess the latency.
NOTE: Assessing these latencies in the cache controllers will require modifying
each to eliminate instantaneous Ruby hit callbacks in transitions that finish
accesses, which is likely a large undertaking.

10993:4e27d8806403 04-Aug-2015 Matthias Jung <jungma@eit.uni-kl.de>

misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.

Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension. For event
handling single events are now created.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10988:ede920fb4f66 03-Aug-2015 Nilay Vaish <nilay@cs.wisc.edu>

ruby: correctly number the sequencer in MESI_Three_Level.py

10976:c0a9bdc36e52 20-Jul-2015 David Hashe <david.hashe@amd.com>

config: add base class for ruby controllers

The CntrlBase python class handles configuration parameters such as running
counts of controllers and sequencers.

10970:ea8bdb1d9f1e 20-Jul-2015 David Hashe <david.hashe@amd.com>

ruby: initialize replacement policies with their own simobjs

this is in preparation for other replacement policies that take additional
parameters.

10926:f48e72961850 21-Jul-2015 Nilay Vaish <nilay@cs.wisc.edu>

configs: network test: remove redundant physical memory

10917:c38f28fad4c3 10-Jul-2015 Brandon Potter <brandon.potter@amd.com>

ruby: remove extra whitespace and correct misspelled words

10898:96c0fe4a09f0 04-Jul-2015 David Hashe <david.hashe@amd.com>

config: Update location of ruby topologies in help

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10887:279efb97ec99 03-Jul-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Remove redundant is_top_level cache parameter

This patch takes the final step in removing the is_top_level parameter
from the cache. With the recent changes to read requests and write
invalidations, the parameter is no longer needed, and consequently
removed.

This also means that asymmetric cache hierarchies are now fully
supported (and we are actually using them already with L1 caches, but
no table-walker caches, connected to a shared L2).

10884:c60acdbdd6ad 03-Jul-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Allow read-only caches and check compliance

This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.

A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.

10860:cba0f26038b4 01-Jun-2015 Andreas Sandberg <andreas.sandberg@arm.com>

kvm, arm: Add support for aarch64

This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:

* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.

* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.

* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).

* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.

10833:a4a2ba97a654 15-May-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Use null memory for DRAM sweep script

Do not waste time when we do not care about the data.

10832:33f1c7b65a88 15-May-2015 Wendy Elsasser <wendy.elsasser@arm.com>

config: Add new MemConfig options to DRAM sweep script

Update script to match current MemConfig options with
external_memory_system option set to 0.

10820:e2a283400c43 05-May-2015 Andreas Hansson <andreas.hansson@arm.com>

arch, cpu: Do not forward snoops to table walker

This patch simplifies the overall CPU by changing the TLB caches such
that they do not forward snoops to the table walker port(s). Note that
only ARM and X86 are affected.

There is no reason for the ports to snoop as they do not actually take
any action, and from a performance point of view we are better of not
snooping more than we have to.

Should it at a later point be required to snoop for a particular TLB
design it is easy enough to add it back.

10807:dac26eb4cb64 29-Apr-2015 Nilay Vaish <nilay@cs.wisc.edu>

cpu: o3: replace issueLatency with bool pipelined

Currently, each op class has a parameter issueLat that denotes the cycles after
which another op of the same class can be issued. As of now, this latency can
either be one cycle (fully pipelined) or same as execution latency of the op
(not at all pipelined). The fact that issueLat is a parameter of type Cycles
makes one believe that it can be set to any value. To avoid the confusion, the
parameter is being renamed as 'pipelined' with type boolean. If set to true,
the op would execute in a fully pipelined fashion. Otherwise, it would execute
in an unpipelined fashion.

10803:a91eb7b4a442 23-Apr-2015 bpotter <brandon.potter@amd.com>

config: enable setting SE-mode environment variables from file

10789:e94c22bd9ef1 20-Apr-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Remove memory aliases and rely on class name

Instead of maintaining two lists, rely entirely on the class
name. There is really no point in causing unecessary confusion.

10786:ee82c2c30421 14-Apr-2015 Malek Musleh <malek.musleh@gmail.com>

config, cpu: fix progress interval for switched CPUs
This patch ensures that the CPU progress Event is triggered for the new set of
switched_cpus that get scheduled (e.g. during fast-forwarding). it also avoids
printing the interval state if the cpu is currently switched out.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10785:f56c10663a01 13-Apr-2015 Dibakar Gope <gope@wisc.edu>

cpu: re-organizes the branch predictor structure.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10780:46070443051e 08-Apr-2015 Curtis Dunham <Curtis.Dunham@arm.com>

config: Support full-system with SST's memory system

This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.

10772:8a7285d6197e 27-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

arm, configs: Do not forward snoops from I cache

This fix simply tells the I cache to not forward snoops to the fetch
unit (since there is really no reason to do so).

10759:37fd40f8300f 23-Mar-2015 Steve Reinhardt <steve.reinhardt@amd.com>

config: expand '~' and '~user' in paths

10757:8a4040874157 23-Mar-2015 Curtis Dunham <Curtis.Dunham@arm.com>

config: Add ability to exit simulation after initialization

When using gem5 as a slave simulator, it will not advance the
clock on its own and depends on the master simulator calling
simulate(). This new option lets us use the Python scripts
to do all the configuration while stopping short of actually
simulating anything.

10750:30efc3828bb4 19-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Add soak test for memtest.py

This patch adds a random option to memtest.py which allows the user to
easily test valid random tree topologies. The patch also adds a
wrapper script to run soak tests using the newly introduced option.

We also adjust the progress interval and progress limit check to make
the output less noisy, and avoid false positives.

Bring on the pain.

10747:3fe41011333d 19-Mar-2015 Chris Emmons <Chris.Emmons@arm.com>

config: Specify OS type and release on command line

This patch enables users to speficy --os-type on the command
line. This option is used to take specific actions for an OS type,
such as changing the kernel command line. This patch is part of the
Android KitKat enablement.

10743:062c820aef24 19-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Fix DRAM rank option in sweep script

Align with changes in the common bits.

10735:071996521ce6 09-Mar-2015 Rizwana Begum <rb639@drexel.edu>

config: Fix for 'android' lookup in disk name
This patch modifies FSConfig.py to look for 'android' only in disk
image name. Before this patch, 'android' was searched in full
disk path.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10720:67b3e74de9ae 02-Mar-2015 Andreas Hansson <andreas.hansson@arm.com>

mem: Move crossbar default latencies to subclasses

This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the different uses in the system. We
use the crossbar in a wide range of places: interfacing cores to the
L2, as a system interconnect, connecting I/O and peripherals,
etc. Needless to say, these crossbars have very different performance,
and the clock frequency alone is not enough to distinguish these
scenarios.

Instead of trying to capture every possible case, this patch
introduces dedicated subclasses for the three primary use-cases:
L2XBar, SystemXBar and IOXbar. More can be added if needed, and the
defaults can be overridden.

10706:4206946d60fe 26-Feb-2015 Jason Power <power.jg@gmail.com>

Ruby: Update backing store option to propagate through to all RubyPorts

Previously, the user would have to manually set access_backing_store=True
on all RubyPorts (Sequencers) in the config files.
Now, instead there is one global option that each RubyPort checks on
initialization.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10705:c6cb94a14fea 16-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Add memcheck stress test

This is a rather unfortunate copy of the memtest.py example script,
that actually stresses the system with true sharing as opposed to the
false sharing of the MemTest. To do so it uses TrafficGen instances to
generate the reads/writes, and MemCheckerMonitor combined with the
MemChecker to check the validity of the read/written values.

As a bonus, this script also enables the addition of prefetchers, and
the traffic is created to have a mix of random addresses and linear
strides. We use the TaggedPrefetcher since the packets do not have a
request with a PC.

At the moment the code is almost identical to the memtest.py script,
and no effort has been made to factor out the construction of the
tree. The challenge is that the instantiation and connection of the
testers and monitors is done as part of the tree building.

10697:71c40e5c8bd4 16-Jan-2015 Curtis Dunham <Curtis.Dunham@arm.com>

config: add --root-device machine parameter

In case /dev/sda1 is not actually the boot partition for an image,
we can override it on the command line or in a benchmark definition.

10690:4972ada74310 11-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Revamp memtest to allow testers on any level

This patch revamps the memtest example script and allows for the
insertion of testers at any level in the cache hierarchy. Previously
all created topologies placed testers only at the very top, and the
tree was thus entirely symmetric. With the changes made, it is possible
to not only place testers at the leaf caches (L1), but also to connect
testers at the L2, L3 etc.

As part of the changes the object hierarchy is also simplified to
ensure that the visual representation from the DOT printing looks
sensible. Using SubSystems to group the objects is one of the key
features.

10688:22452667fd5c 11-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

cpu: Tidy up the MemTest and make false sharing more obvious

The MemTest class really only tests false sharing, and as such there
was a lot of old cruft that could be removed. This patch cleans up the
tester, and also makes it more clear what the assumptions are. As part
of this simplification the reference functional memory is also
removed.

The regression configs using MemTest are updated to reflect the
changes, and the stats will be bumped in a separate patch. The example
config will be updated in a separate patch due to more extensive
re-work.

In a follow-on patch a new tester will be introduced that uses the
MemChecker to implement true sharing.

10682:3d17366c0423 05-Feb-2015 Steve Reinhardt <steve.reinhardt@amd.com>

config: rename 'file' var

Rename uses of 'file' as a local variable to avoid conflict
with the built-in type of the same name.

10681:c35efeacc933 05-Feb-2015 Steve Reinhardt <steve.reinhardt@amd.com>

config: make M5_PATH a real search path

Although you can put a list of colon-separated directory names
in M5_PATH, the current code just takes the first one that
exists and assumes all files must live there. This change
makes the code search the specified list of directories
for each individual binary or disk image that's requested.

The main motivation is that the x86/Alpha binaries and the
ARM binaries are in separate downloads, and thus naturally
end up in separate directories. With this change, you can
have M5_PATH point to those two directories, then run any
FS regression test without changing M5_PATH. Currently,
you either have to merge the two download directories
or change M5_PATH (or do something else I haven't figured out).

10677:5935ab1ddd7a 03-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Add XOR hashing to the DRAM channel interleaving

This patch uses the recently added XOR hashing capabilities for the
DRAM channel interleaving. This avoids channel biasing due to strided
access patterns.

10675:bb7cd7193edc 03-Feb-2015 Andreas Hansson <andreas.hansson@arm.com>

config: Adjust DRAM channel interleaving defaults

This patch changes the DRAM channel interleaving default behaviour to
be more representative. The default address mapping (RoRaBaCoCh) moves
the channel bits towards the least significant bits, and uses 128 byte
as the default channel interleaving granularity.

These defaults can be overridden if desired, but should serve as a
sensible starting point for most use-cases.

10667:e17949745150 30-Jan-2015 Malek Musleh <malek.musleh@gmail.com>

config: arm: fix os_flags
Fix the makeArmSystem routine to reflect recent changes that support kernel
commandline option when running android. Without this fix, trying to run
android encounters a 'reference before assignment' error.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10652:e5936c2d53a0 20-Jan-2015 Malek Musleh <malek.musleh@gmail.com>

config, ruby: connect dma to network
DMA Controller was not being connected to the network for the MESI_Three_Level
protocol as was being done in the other protocol config files. Without this
patch, this protocol segfaults during startup.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10650:a6fe75e8296b 20-Jan-2015 Andreas Hansson <andreas.hansson@arm.com>

scons: Do not build the InOrderCPU

One step closer to shifting focus to the MinorCPU.

10635:ab05a080d7c5 03-Jan-2015 Anthony Gutierrez <atgutier@umich.edu>

arm: fix build_drive_system when not using default options

when trying to dual boot on arm build_drive_system will only use the default
values for the dtb file, number of processors, and disk image. if you are using
the non-default files by passing values on the command line for example, or by
making a new entry in Benchmarks.py, the build config scripts will still look
for the default files. this will lead to the wrong system files being used, or
the simulator will fail if you do not have them.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10630:64618b7c57b2 03-Jan-2015 Nilay Vaish <nilay@cs.wisc.edu>

configs: ruby: removes bug introduced by 05b5a6cf3521

10620:74834c49fbbe 23-Dec-2014 Andreas Hansson <andreas.hansson@arm.com>

config: Expose the DRAM ranks as a command-line option

This patch gives the user direct influence over the number of DRAM
ranks to make it easier to tune the memory density without affecting
the bandwidth (previously the only means of scaling the device count
was through the number of channels).

The patch also adds some basic sanity checks to ensure that the number
of ranks is a power of two (since we rely on bit slices in the address
decoding).

10613:9d0aef7a9b2e 23-Dec-2014 Marco Elver <Marco.Elver@ARM.com>

config: Add --memchecker option

This patch adds the --memchecker option, to denote that a MemChecker
should be instantiated for the system. The exact usage of the MemChecker
depends on the system configuration.

For now CacheConfig.py makes use of the option, adding MemCheckerMonitor
instances between CPUs and D-Caches.

Note, however, that currently this only provides limited checking on a
running system; other parts of the system, such as I/O devices are not
monitored, and may cause warnings to be issued by the monitor.

10608:427f988fe6e5 23-Dec-2014 Dam Sunwoo <dam.sunwoo@arm.com>

config: Add options to take/resume from SimPoint checkpoints

More documentation at http://gem5.org/Simpoints

Steps to profile, generate, and use SimPoints with gem5:

1. To profile workload and generate SimPoint BBV file, use the
following option:

--simpoint-profile --simpoint-interval <interval length>

Requires single Atomic CPU and fastmem.
<interval length> is in number of instructions.

2. Generate SimPoint analysis using SimPoint 3.2 from UCSD.
(SimPoint 3.2 not included with this flow.)

3. To take gem5 checkpoints based on SimPoint analysis, use the
following option:

--take-simpoint-checkpoint=<simpoint file path>,<weight file
path>,<interval length>,<warmup length>

<simpoint file> and <weight file> is generated by SimPoint analysis
tool from UCSD. SimPoint 3.2 format expected. <interval length> and
<warmup length> are in number of instructions.

4. To resume from gem5 SimPoint checkpoints, use the following option:

--restore-simpoint-checkpoint -r <N> --checkpoint-dir <simpoint
checkpoint path>

<N> is (SimPoint index + 1). E.g., "-r 1" will resume from SimPoint
#0.

10594:4fdc929c0aaa 04-Dec-2014 Gabe Black <gabeblack@google.com>

config: Add two options for setting the kernel command line.

Both options accept template which will, through python string formatting,
have "mem", "disk", and "script" values substituted in from the mdesc.
Additional values can be used on a case by case basis by passing them as
keyword arguments to the fillInCmdLine function. That makes it possible to
have specialized parameters for a particular ISA, for instance.

The first option lets you specify the template directly, and the other lets
you specify a file which has the template in it.

10591:fea29fc045ee 04-Dec-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby: mi protocol: correct master slave setting for dma
In the MI protocol, the master slave connection between the dma controller
and network was being set incorrectly. This patch corrects it.

10588:145c436a3854 03-Dec-2014 Gabe Black <gabeblack@google.com>

config: Get rid of some extra spaces around default arguments.

10555:9f456b5cc474 23-Nov-2014 Alexandru Dutu <alexandru.dutu@amd.com>

config, kvm: Enabling KvmCPU in SE mode
This patch modifies se.py such that it can now use kvm cpu model.

10551:d60a9bb99038 23-Nov-2014 Steve Reinhardt <steve.reinhardt@amd.com>

Backed out prior changeset f9fb64a72259

Back out use of importlib to avoid implicitly creating
dependency on Python 2.7.

10550:f9fb64a72259 23-Nov-2014 Gabe Black <gabeblack@google.com>

config: ruby: Get rid of an "eval" and an "exec" operating on generated code.

We can get the same result using importlib.

10547:b61dc895269a 18-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

configs: small fix to ruby portion of fs.py and se.py
In fs.py the io port controller was being attached to the iobus multiple
times. This should be done only once. In se.py, the the option use_map
was being set which no longer exists.

10529:05b5a6cf3521 06-Nov-2014 Marc Orr <morr@cs.wisc.edu>

x86 isa: This patch attempts an implementation at mwait.

Mwait works as follows:
1. A cpu monitors an address of interest (monitor instruction)
2. A cpu calls mwait - this loads the cache line into that cpu's cache.
3. The cpu goes to sleep.
4. When another processor requests write permission for the line, it is
evicted from the sleeping cpu's cache. This eviction is forwarded to the
sleeping cpu, which then wakes up.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10525:77787650cbbc 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: provide a backing store
Ruby's functional accesses are not guaranteed to succeed as of now. While
this is not a problem for the protocols that are currently in the mainline
repo, it seems that coherence protocols for gpus rely on a backing store to
supply the correct data. The aim of this patch is to make this backing store
configurable i.e. it comes into play only when a particular option:
--access-backing-store is invoked.

The backing store has been there since M5 and GEMS were integrated. The only
difference is that earlier the system used to maintain the backing store and
ruby's copy was write-only. Sometime last year, we moved to data being
supplied supplied by ruby in SE mode simulations. And now we have patches on
the reviewboard, which remove ruby's copy of memory altogether and rely
completely on the system's memory to supply data. This patch adds back a
SimpleMemory member to RubySystem. This member is used only if the option:
access-backing-store is set to true. By default, the memory would not be
accessed.

10524:fff17530cef6 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.


common/MemConfig.py
example/fs.py
example/ruby_direct_test.py
example/ruby_mem_test.py
example/ruby_random_test.py
example/se.py
ruby/MESI_Three_Level.py
ruby/MESI_Two_Level.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/RubySlicc_Defines.sm
/gem5/src/mem/protocol/RubySlicc_Types.sm
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/network/MessageBuffer.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/structures/Cache.py
/gem5/src/mem/ruby/structures/DirectoryMemory.py
/gem5/src/mem/ruby/structures/MemoryControl.cc
/gem5/src/mem/ruby/structures/MemoryControl.hh
/gem5/src/mem/ruby/structures/MemoryControl.py
/gem5/src/mem/ruby/structures/MemoryNode.cc
/gem5/src/mem/ruby/structures/MemoryNode.hh
/gem5/src/mem/ruby/structures/MemoryVector.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.cc
/gem5/src/mem/ruby/structures/RubyMemoryControl.hh
/gem5/src/mem/ruby/structures/RubyMemoryControl.py
/gem5/src/mem/ruby/structures/SConscript
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
10519:7a3ad4b09ce4 06-Nov-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.

10512:b423e1d0735e 30-Oct-2014 Ali Saidi <Ali.Saidi@ARM.com>

arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.

10507:f33fab6214c4 30-Oct-2014 Ali Saidi <Ali.Saidi@ARM.com>

arm: fix bare-metal memory setup.

The bare-metal configuration option still configured memory with the old scheme
that no-longer works. This change unifies the code so there aren't any differences.

10458:64809024b924 16-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

config: Add the ability to read a config file using C++ and Python

This patch adds the ability to load in config.ini files generated from
gem5 into another instance of gem5 built without Python configuration
support. The intended use case is for configuring gem5 when it is a
library embedded in another simulation system.

A parallel config file reader is also provided purely in Python to
demonstrate the approach taken and to provided similar functionality
for as-yet-unknown use models. The Python configuration file reader
can read both .ini and .json files.

C++ configuration file reading:

A command line option has been added for scons to enable C++ configuration
file reading: --with-cxx-config

There is an example in util/cxx_config that shows C++ configuration in action.
util/cxx_config/README explains how to build the example.

Configuration is achieved by the object CxxConfigManager. It handles
reading object descriptions from a CxxConfigFileBase object which
wraps a config file reader. The wrapper class CxxIniFile is provided
which wraps an IniFile for reading .ini files. Reading .json files
from C++ would be possible with a similar wrapper and a JSON parser.

After reading object descriptions, CxxConfigManager creates
SimObjectParam-derived objects from the classes in the (generated with this
patch) directory build/ARCH/cxx_config

CxxConfigManager can then build SimObjects from those SimObjectParams (in an
order dictated by the SimObject-value parameters on other objects) and bind
ports of the produced SimObjects.

A minimal set of instantiate-replacing member functions are provided by
CxxConfigManager and few of the member functions of SimObject (such as drain)
are extended onto CxxConfigManager.

Python configuration file reading (configs/example/read_config.py):

A Python version of the reader is also supplied with a similar interface to
CxxConfigFileBase (In Python: ConfigFile) to config file readers.

The Python config file reading will handle both .ini and .json files.

The object construction strategy is slightly different in Python from the C++
reader as you need to avoid objects prematurely becoming the children of other
objects when setting parameters.

Port binding also needs to be strictly in the same port-index order as the
original instantiation.

10442:cd2daa931a54 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function. This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.

10440:1e3497e20cd4 11-Oct-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: moesi hammer: correct typo in master-slave assignment

10438:08fa6ad59594 16-Jul-2014 Jiuyue Ma <majiuyue@ncic.ac.cn>

config, x86: Ensure that PCI devs get bridged to the memory bus

This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by
reserve anything between the end of memory and 3GB if memory is less
than 3GB. It also statically bridge these address range to the IO bus,
which guaranty access to pci address space will pass though bridge to
iobus.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10437:caec4a7b8b74 16-Jul-2014 Jiuyue Ma <majiuyue@ncic.ac.cn>

config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable

This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for
X86 platform. Because PCI device get config space address using
Pc::calcPciConfigAddr() which requires "assert(bus==0)".
This fixes PCI interrupt routing and discovery on Linux.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10405:7a618c07e663 20-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.

10392:0100f00a229e 20-Sep-2014 Wendy Elsasser <wendy.elsasser@arm.com>

cpu: Update DRAM traffic gen

Add new DRAM_ROTATE mode to traffic generator.
This mode will generate DRAM traffic that rotates across
banks per rank, command types, and ranks per channel

The looping order is illustrated below:
for (ranks per channel)
for (command types)
for (banks per rank)
// Generate DRAM Command Series

This patch also adds the read percentage as an input argument to the
DRAM sweep script. If the simulated read percentage is 0 or 100, the
middle for loop does not generate additional commands. This loop is
used only when the read percentage is set to 50, in which case the
middle loop will toggle between read and write commands.

Modified sweep.py script, which generates DRAM traffic.
Added input arguments and support for new DRAM_ROTATE mode.
The script now has input arguments for:
1) Read percentage
2) Number of ranks
3) Address mapping
4) Traffic generator mode (DRAM or DRAM_ROTATE)

The default values are:
100% reads, 1 rank, RoRaBaCoCh address mapping, and DRAM traffic gen mode

For the DRAM traffic mode, added multi-rank support.

10381:ab8b8601b6ff 20-Sep-2014 Dam Sunwoo <dam.sunwoo@arm.com>

cpu: use probes infrastructure to do simpoint profiling

Instead of having code embedded in cpu model to do simpoint profiling use
the probes infrastructure to do it.

10358:644b615fbe6a 03-Sep-2014 Ali Saidi <Ali.Saidi@ARM.com>

arm: Support >2GB of memory for AArch64 systems

10357:1aff1376921e 03-Sep-2014 Ali Saidi <Ali.Saidi@ARM.com>

arm: Assume we have a kernel that supports pci devices

Change the default kernel for AArch64 and since it supports PCI devices
remove the hack that made it use CF. Unfortunately, there isn't really
a half-way here and we need to switch. Current users will get an error
message that the kernel isn't found and hopefully go download a new
kernel that supports PCI.

10353:dfebd39c48a7 03-Sep-2014 Geoffrey Blake <Geoffrey.Blake@arm.com>

config: Refactor RealviewEMM to fit into new config system

This eliminates some default devices and adds in helper functions
to connect the devices defined here to associate with the proper
clock domains.

10327:5b6279635c49 03-Sep-2014 Mitch Hayenga <mitch.hayenga@arm.com>

cpu: Change writeback modeling for outstanding instructions

As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().

10323:5169ebd26163 03-Sep-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Add utility script to plot DRAM efficiency sweep

This patch adds basic functionality to quickly visualise the output
from the DRAM efficiency script. There are some unfortunate hacks
needed to communicate the needed information from one script to the
other, and we fall back on (ab)using the simout to do this.

As part of this patch we also trim the efficiency sweep to stop at 512
bytes as this should be sufficient for all forseeable DRAMs.

10311:ad9c042dce54 01-Sep-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.


ruby/MESI_Three_Level.py
ruby/MESI_Two_Level.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Network_test.py
ruby/Ruby.py
/gem5/src/mem/protocol/MESI_Three_Level-L0cache.sm
/gem5/src/mem/protocol/MESI_Three_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/Network_test-cache.sm
/gem5/src/mem/protocol/Network_test-dir.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/PerfectSwitch.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Throttle.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.cc
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/python/swig/pyobject.cc
10300:ed3816dae6d5 01-Sep-2014 Emilio Castillo <castilloe@unican.es>, Nilay Vaish <nilay@cs.wisc.edu>

ruby: Fixes clock domains in configuration files

This patch fixes scripts related to ruby by adding the ruby clock domain.
Now the L1 controllers and the Sequencer shares the cpu clock domain,
while the rest of the components use the ruby clock domain.

Before this patch, running simulations with the cpu clock set at 2GHz or
1GHz will output the same time results and could distort power measurements.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10270:763f76d5dea7 10-Aug-2014 Radhika Jagtap <radhika.jagtap@ARM.com>

config: Fix cache latency param in mem test

This patch fixes the cache latency in mem test which is split into two params,
hit and response latency as per BaseCache.

10262:f3e9fe1600d6 28-Jul-2014 Anthony Gutierrez <atgutier@umich.edu>

arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2

the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache.

10259:ebb376f73dd2 23-Jul-2014 Andrew Bardsley <Andrew.Bardsley@arm.com>

cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036


/gem5/build_opts/ALPHA
/gem5/build_opts/ARM
common/CpuConfig.py
/gem5/src/base/trace.hh
/gem5/src/cpu/SConscript
/gem5/src/cpu/TimingExpr.py
/gem5/src/cpu/minor/MinorCPU.py
/gem5/src/cpu/minor/SConscript
/gem5/src/cpu/minor/SConsopts
/gem5/src/cpu/minor/activity.cc
/gem5/src/cpu/minor/activity.hh
/gem5/src/cpu/minor/buffers.hh
/gem5/src/cpu/minor/cpu.cc
/gem5/src/cpu/minor/cpu.hh
/gem5/src/cpu/minor/decode.cc
/gem5/src/cpu/minor/decode.hh
/gem5/src/cpu/minor/dyn_inst.cc
/gem5/src/cpu/minor/dyn_inst.hh
/gem5/src/cpu/minor/exec_context.hh
/gem5/src/cpu/minor/execute.cc
/gem5/src/cpu/minor/execute.hh
/gem5/src/cpu/minor/fetch1.cc
/gem5/src/cpu/minor/fetch1.hh
/gem5/src/cpu/minor/fetch2.cc
/gem5/src/cpu/minor/fetch2.hh
/gem5/src/cpu/minor/func_unit.cc
/gem5/src/cpu/minor/func_unit.hh
/gem5/src/cpu/minor/lsq.cc
/gem5/src/cpu/minor/lsq.hh
/gem5/src/cpu/minor/pipe_data.cc
/gem5/src/cpu/minor/pipe_data.hh
/gem5/src/cpu/minor/pipeline.cc
/gem5/src/cpu/minor/pipeline.hh
/gem5/src/cpu/minor/scoreboard.cc
/gem5/src/cpu/minor/scoreboard.hh
/gem5/src/cpu/minor/stats.cc
/gem5/src/cpu/minor/stats.hh
/gem5/src/cpu/minor/trace.hh
/gem5/src/cpu/pred/SConscript
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/timing_expr.cc
/gem5/src/cpu/timing_expr.hh
/gem5/src/doc/inside-minor.doxygen
/gem5/src/sim/SConscript
/gem5/src/sim/TickedObject.py
/gem5/src/sim/ticked_object.cc
/gem5/src/sim/ticked_object.hh
/gem5/util/minorview.py
/gem5/util/minorview/__init__.py
/gem5/util/minorview/blobs.py
/gem5/util/minorview/colours.py
/gem5/util/minorview/minor.pic
/gem5/util/minorview/model.py
/gem5/util/minorview/parse.py
/gem5/util/minorview/point.py
/gem5/util/minorview/view.py
10243:cfb6b578a89a 30-Jun-2014 Anthony Gutierrez <atgutier@umich.edu>

arm: make the bi-mode predictor the default for O3_ARM_v7a_BP

the branch predictor used in the Cortex-A15 is a bi-mode style predictor,
see:

http://arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf
and
http://nvidia.com/docs/IO/116757/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf

this patch makes the bi-mode predictor the default for the ARM O3 CPU.

10224:54d3ef2009a2 15-May-2014 Anthony Gutierrez <atgutier@umich.edu>

config: remove unecessary assignment of etherlink interfaces

in makeDualRoot() the etherlink interfaces are set using the tsunami interface
however, they are set again a few lines later based on whether or not the system
is a realview or tsunami system; the original assignment is always overwritten
or there will be a fatal. this seems like an artifact from when tsunami was the
only type of system capable of running with the dual option.

10219:4161cfba9658 09-May-2014 Andreas Hansson <andreas.hansson@arm.com>

config: Bump DRAM sweep bus speed to match DDR4 config

This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.

10162:43bc3665c52b 19-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby: remove memory controller from network test
It is not in use and not required as such.

10161:ae43fc4d78cb 14-Apr-2014 Anthony Gutierrez <atgutier@umich.edu>

arm: set default kernels for VExpress_EMM and VExpress_EMM64

10159:ca6f1407f8f8 10-Apr-2014 Gedare Bloom <gedare@rtems.org>

config: add num-work-ids command line option
Adds the parameter --num-work-ids to Options.py and reads the parameter
into the System params in Simulation.py. This parameter enables setting
the number of possible work items to different than 16. Support for this
parameter already exists in src/sim/System.py, so this changeset only
affects the Python config files.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

10150:240969297314 01-Apr-2014 Nilay Vaish <nilay@cs.wisc.edu>

configs: use SimpleMemory when using ruby in se mode
A recent changeset altered the default memory class to DRAMCtrl. In se mode,
ruby uses the physical memory to check if a given address is within the bounds
of the physical memory. SimpleMemory is enough for this. Moreover,
SimpleMemory does not check whether it is connected or not, something which
DRAMCtrl does.

10146:27dfed4c8403 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Rename SimpleDRAM to a more suitable DRAMCtrl

This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).

As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.

10145:d19f759b7340 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Change memory defaults to be more representative

Make the default memory type DDR3-1600 x64, and use the open-adaptive
page policy. This change is aiming to ensure that users by default are
using a realistic memory system.

10139:45d16673b95a 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

config: Add a DRAM efficiency-sweep script

This patch adds a configuration that simplifies evaluation of DRAM
controller configurations by automating a sweep of stride size and
bank parallelism. It works in a rather unconventional way, as it needs
to print the traffic generator stimuli based on the memory
organisation. Hence, it starts by configuring the memory, then it
prints a traffic-generator config file, and loads it.

The resulting stats have one period per data point, identified by the
stride size, and the number of banks being used.

10136:ba1ed063e3af 23-Mar-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: More descriptive address-mapping scheme names

This patch adds the row bits to the name of the address mapping
schemes to make it more clear that all the current schemes places the
row bits as the most significant bits.

10122:1268f1fd2714 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: convert network interfaces into clocked objects
This helps in configuring the network interfaces from the python script and
these objects no longer rely on the network object for the timing information.

10120:f5ceb3c3edb6 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby: rename _cpu_ruby_ports to _cpu_ports

10119:6f3f839bb496 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: fs.py: move creating of test/drive systems to functions
The code that creates test and drive systems is being moved to separate
functions so as to make the code more readable. Ultimately the two
functions would be combined so that the replicated code is eliminated.

10118:5e1f04b4d5e4 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: remove ruby_fs.py

The patch removes the ruby_fs.py file. The functionality is being moved to
fs.py. This would being ruby fs simulations in line with how ruby se
simulations are started (using --ruby option). The alpha fs config functions
are being combined for classing and ruby memory systems. This required
renaming the piobus in ruby to iobus. So, we will have stats being renamed
in the stats file for ruby fs regression.

10117:37e333de580f 20-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: no piobus in se mode
Piobus was recently added to se scripts for ruby so that the interrupt
controller can be connected to something (required since the interrupt
controller sends address range messages). This patch removes the piobus
and instead, the pio port of ruby port will now ignore the range change
messages in se mode.

10116:d61a59beb670 17-Mar-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby: remove piobus from protocols
This patch removes the piobus from the protocol config files. The ports
are now connected to the piobus in the Ruby.py file.

10092:c0db268f811b 24-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: correct errors in changeset 4eec7bdde5b0
Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch.
Firstly, we create interrupt controllers in the se mode, but no piobus was
being created. RubyPort, which earlier used to ignore range changes now
forwards those to the piobus. The lack of piobus resulted in segmentation
fault. This patch creates a piobus even in se mode. It is not created only
when some tester is running. Secondly, I had missed out on modifying port
connections for other coherence protocols.

10090:4eec7bdde5b0 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly. Therefore the packets between the io devices and the interrupt
controller do not go through ruby. This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination. Note that the patch does not make these packets go through the
ruby network. That would happen in a subsequent patch.

10088:eca928d8a4ab 23-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: topologies: slight code refactor

10083:2beea2a439b4 21-Feb-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby_random_test: updates due to recent unrelated changes

10071:6234ea863e76 18-Feb-2014 Anthony Gutierrez <atgutier@umich.edu>

arm: armv8 boot options to enable v8

Modifies FSConfig.py to enable ARMv8 compatibility.
To boot gem5 with ARMv8:
Download the v8 kernel, .dtb file, and root FS from: http://gem5.org/Download
Download the ARMv8 toolchain, and add the bin dir to your path:
http://www.linaro.org/engineering/engineering-projects/armv8
Build gem5 for ARM
Build the v8 bootloader (in gem5/system/arm/aarch64_bootloader)
Make script in gem5/system/arm/aarch64_bootloader will require v8 toolchain,
drop the produced boot_emm.arm64 in $(M5_PATH)/binaries/
Run:
$ build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_EMM64 \
--kernel=/path/to/kernel/vmlinux-linaro-tracking \
--dtb-filename=/path/to/dtb/rtsm_ve-aemv8a.dtb \
--disk-image=/path/to/img/linaro-minimal-armv8.img

10066:06a33d872798 18-Feb-2014 Andreas Hansson <andreas.hansson@arm.com>

mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.

10056:33db5d81c2cb 31-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: correct bug in x86 drive sys instantiation

10046:8b7425bd3196 28-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

x86: add a warning about the number of memory controllers
When memory size > 3GB, print a warning that twice the number of memory
controllers would be created.

10041:fae4550d2103 27-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

config: allow more than 3GB of memory for x86 simulations
This patch edits the configuration files so that x86 simulations can have
more than 3GB of memory. It also corrects a bug in the MemConfig.py script.

10037:5cac77888310 24-Jan-2014 ARM gem5 Developers

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black


common/FSConfig.py
common/O3_ARM_v7a.py
common/Options.py
common/cpu2000.py
example/fs.py
example/se.py
/gem5/ext/libelf/elf_common.h
/gem5/src/arch/arm/ArmISA.py
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/arm/SConscript
/gem5/src/arch/arm/decoder.cc
/gem5/src/arch/arm/decoder.hh
/gem5/src/arch/arm/faults.cc
/gem5/src/arch/arm/faults.hh
/gem5/src/arch/arm/insts/branch64.cc
/gem5/src/arch/arm/insts/branch64.hh
/gem5/src/arch/arm/insts/data64.cc
/gem5/src/arch/arm/insts/data64.hh
/gem5/src/arch/arm/insts/fplib.cc
/gem5/src/arch/arm/insts/fplib.hh
/gem5/src/arch/arm/insts/macromem.cc
/gem5/src/arch/arm/insts/macromem.hh
/gem5/src/arch/arm/insts/mem.cc
/gem5/src/arch/arm/insts/mem64.cc
/gem5/src/arch/arm/insts/mem64.hh
/gem5/src/arch/arm/insts/misc.cc
/gem5/src/arch/arm/insts/misc.hh
/gem5/src/arch/arm/insts/misc64.cc
/gem5/src/arch/arm/insts/misc64.hh
/gem5/src/arch/arm/insts/neon64_mem.hh
/gem5/src/arch/arm/insts/pred_inst.hh
/gem5/src/arch/arm/insts/static_inst.cc
/gem5/src/arch/arm/insts/static_inst.hh
/gem5/src/arch/arm/insts/vfp.cc
/gem5/src/arch/arm/insts/vfp.hh
/gem5/src/arch/arm/interrupts.cc
/gem5/src/arch/arm/interrupts.hh
/gem5/src/arch/arm/intregs.hh
/gem5/src/arch/arm/isa.cc
/gem5/src/arch/arm/isa.hh
/gem5/src/arch/arm/isa/bitfields.isa
/gem5/src/arch/arm/isa/decoder/aarch64.isa
/gem5/src/arch/arm/isa/decoder/arm.isa
/gem5/src/arch/arm/isa/decoder/decoder.isa
/gem5/src/arch/arm/isa/decoder/thumb.isa
/gem5/src/arch/arm/isa/formats/aarch64.isa
/gem5/src/arch/arm/isa/formats/branch.isa
/gem5/src/arch/arm/isa/formats/formats.isa
/gem5/src/arch/arm/isa/formats/fp.isa
/gem5/src/arch/arm/isa/formats/mem.isa
/gem5/src/arch/arm/isa/formats/misc.isa
/gem5/src/arch/arm/isa/formats/neon64.isa
/gem5/src/arch/arm/isa/formats/uncond.isa
/gem5/src/arch/arm/isa/formats/unimp.isa
/gem5/src/arch/arm/isa/includes.isa
/gem5/src/arch/arm/isa/insts/aarch64.isa
/gem5/src/arch/arm/isa/insts/branch.isa
/gem5/src/arch/arm/isa/insts/branch64.isa
/gem5/src/arch/arm/isa/insts/data.isa
/gem5/src/arch/arm/isa/insts/data64.isa
/gem5/src/arch/arm/isa/insts/div.isa
/gem5/src/arch/arm/isa/insts/fp.isa
/gem5/src/arch/arm/isa/insts/fp64.isa
/gem5/src/arch/arm/isa/insts/insts.isa
/gem5/src/arch/arm/isa/insts/ldr.isa
/gem5/src/arch/arm/isa/insts/ldr64.isa
/gem5/src/arch/arm/isa/insts/m5ops.isa
/gem5/src/arch/arm/isa/insts/macromem.isa
/gem5/src/arch/arm/isa/insts/mem.isa
/gem5/src/arch/arm/isa/insts/misc.isa
/gem5/src/arch/arm/isa/insts/misc64.isa
/gem5/src/arch/arm/isa/insts/neon.isa
/gem5/src/arch/arm/isa/insts/neon64.isa
/gem5/src/arch/arm/isa/insts/neon64_mem.isa
/gem5/src/arch/arm/isa/insts/str.isa
/gem5/src/arch/arm/isa/insts/str64.isa
/gem5/src/arch/arm/isa/insts/swap.isa
/gem5/src/arch/arm/isa/operands.isa
/gem5/src/arch/arm/isa/templates/basic.isa
/gem5/src/arch/arm/isa/templates/branch64.isa
/gem5/src/arch/arm/isa/templates/data64.isa
/gem5/src/arch/arm/isa/templates/macromem.isa
/gem5/src/arch/arm/isa/templates/mem.isa
/gem5/src/arch/arm/isa/templates/mem64.isa
/gem5/src/arch/arm/isa/templates/misc.isa
/gem5/src/arch/arm/isa/templates/misc64.isa
/gem5/src/arch/arm/isa/templates/neon.isa
/gem5/src/arch/arm/isa/templates/neon64.isa
/gem5/src/arch/arm/isa/templates/templates.isa
/gem5/src/arch/arm/isa/templates/vfp.isa
/gem5/src/arch/arm/isa/templates/vfp64.isa
/gem5/src/arch/arm/isa_traits.hh
/gem5/src/arch/arm/linux/linux.cc
/gem5/src/arch/arm/linux/linux.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/process.hh
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/linux/system.hh
/gem5/src/arch/arm/locked_mem.hh
/gem5/src/arch/arm/miscregs.cc
/gem5/src/arch/arm/miscregs.hh
/gem5/src/arch/arm/nativetrace.cc
/gem5/src/arch/arm/pagetable.hh
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/process.hh
/gem5/src/arch/arm/registers.hh
/gem5/src/arch/arm/remote_gdb.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/stage2_lookup.cc
/gem5/src/arch/arm/stage2_lookup.hh
/gem5/src/arch/arm/stage2_mmu.cc
/gem5/src/arch/arm/stage2_mmu.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/table_walker.cc
/gem5/src/arch/arm/table_walker.hh
/gem5/src/arch/arm/tlb.cc
/gem5/src/arch/arm/tlb.hh
/gem5/src/arch/arm/types.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/utility.hh
/gem5/src/arch/arm/vtophys.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/arm/SConscript
/gem5/src/dev/arm/generic_timer.cc
/gem5/src/dev/arm/generic_timer.hh
/gem5/src/dev/arm/gic_pl390.cc
/gem5/src/dev/arm/vgic.cc
/gem5/src/dev/arm/vgic.hh
/gem5/src/sim/System.py
/gem5/src/sim/process.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/system/arm/aarch64_bootloader/LICENSE.txt
/gem5/system/arm/aarch64_bootloader/boot.S
/gem5/system/arm/aarch64_bootloader/makefile
/gem5/util/cpt_upgrader.py
/gem5/util/m5/m5op_arm_A64.S
10012:ec5a5bfb941d 10-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: move all statistics to stats.txt, eliminate ruby.stats

10008:5176f0a71e56 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add a three level MESI protocol.

The first two levels (L0, L1) are private to the core, the third level (L2)is
possibly shared. The protocol supports clustered designs. For example, one
can have two sets of two cores. Each core has an L0 and L1 cache. There are
two L2 controllers where each set accesses only one of the L2 controllers.

10007:94d286db85c1 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: rename MESI_CMP_directory to MESI_Two_Level

This is because the next patch introduces a three level hierarchy.


/gem5/build_opts/ALPHA_MESI_CMP_directory
/gem5/build_opts/ALPHA_MESI_Two_Level
/gem5/build_opts/X86_MESI_CMP_directory
/gem5/build_opts/X86_MESI_Two_Level
ruby/MESI_CMP_directory.py
ruby/MESI_Two_Level.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MESI_CMP_directory.slicc
/gem5/src/mem/protocol/MESI_Two_Level-L1cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-L2cache.sm
/gem5/src/mem/protocol/MESI_Two_Level-dir.sm
/gem5/src/mem/protocol/MESI_Two_Level-dma.sm
/gem5/src/mem/protocol/MESI_Two_Level-msg.sm
/gem5/src/mem/protocol/MESI_Two_Level.slicc
/gem5/src/mem/protocol/SConsopts
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
/gem5/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
/gem5/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
/gem5/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
/gem5/util/regress
10006:8fa94dcfd545 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove cntrl_id from python config scripts.

10004:5d8b72563869 04-Jan-2014 Nilay Vaish <nilay@cs.wisc.edu>

ruby: some small changes

10003:459491344fcf 03-Jan-2014 Steve Reinhardt <steve.reinhardt@amd.com>

config, x86: move kernel specification from tests to FSConfig.py

For some reason, the default x86 kernel is specified in
tests/configs/x86_generic.py and not in configs/common/FSConfig.py,
where the kernels for all the other ISAs are. This means that
running configs/example/fs.py for x86 fails because no kernel
is specified. Moving the specification over fixes this problem.

There is another problem that this uncovers, which is that going
past the init stage (i.e., past where the regression test stops)
fails because the fsck test on the disk device fails, but that's
a separate issue.

9994:1aa497ac86b2 20-Dec-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: mesi: remove owner and sharer fields from directory tags

The directory controller should not have the sharer field since there is
only one level 2 cache. Anyway the field was not in use. The owner field
was being used to track the l2 cache version (in case of distributed l2) that
has the cache block under consideration. The information is not required
since the version of the level 2 cache can be obtained from a subset of the
address bits.

9982:b2bfc23f932c 15-Nov-2013 Anthony Gutierrez <atgutier@umich.edu>

cpu: allow the fetch buffer to be smaller than a cache line

the current implementation of the fetch buffer in the o3 cpu
is only allowed to be the size of a cache line. some
architectures, e.g., ARM, have fetch buffers smaller than a cache
line, see slide 22 at:
http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf

this patch allows the fetch buffer to be set to values smaller
than a cache line.

9935:cc9dc514036e 17-Oct-2013 Dam Sunwoo <dam.sunwoo@arm.com>

util: Streamline .apc project convertsion script

This Python script generates an ARM DS-5 Streamline .apc project based
on gem5 run. To successfully convert, the gem5 runs needs to be run
with the context-switch-based stats dump option enabled (The guest
kernel also needs to be patched to allow gem5 interrogate its task
information.) See help for more information.

9929:d6f0e70fd0d4 17-Oct-2013 Ali Saidi <Ali.Saidi@ARM.com>

arm, config: Fix a small issue with the dtb file being specified

9928:9d3b979cd3ed 17-Oct-2013 Ali Saidi <Ali.Saidi@ARM.com>

config: Fix memtest example script

9909:0679c3554ba3 09-Oct-2013 Nilay Vaish <nilay@cs.wisc.edu>

config: correct example ruby scripts
A couple of recent changesets added/deleted/edited some variables
that are needed for running the example ruby scripts. This changeset
edits these scripts to bring them to a working state.

9907:8bddb3879c16 07-Oct-2013 Nilay Vaish <nilay@cs.wisc.edu>

config: set cwd for processes in se.py

9898:2935441b0870 29-Sep-2013 Andreas Sandberg <andreas@sandberg.pp.se>

x86: Add support for m5ops through a memory mapped interface

In order to support m5ops in virtualized environments, we need to use
a memory mapped interface. This changeset adds support for that by
reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR
interface for m5ops. The mapping is done in the
X86ISA::TLB::finalizePhysical() which means that it just works for all
of the CPU models, including virtualized ones.

9891:19fa1dfd583f 30-Sep-2013 Andreas Sandberg <andreas@sandberg.pp.se>

config: Add a 'kvm' CPU alias

Add a CPU alias, 'kvm', for the first available KVM-accelerated CPU
model.

9872:ad7d5f966b74 17-Sep-2013 Joel Hestness <jthestness@gmail.com>

configs: Fix ruby_fs.py cache line size

Recent changes added setting of system-wide cache line size and these settings
occur in the top-level configs (se.py and fs.py). This setting also needs to
take place in ruby_fs.py. This change sets the cache line size as appropriate.

9870:e147cc305061 12-Sep-2013 Andreas Hansson <andreas.hansson@arm.com>

config: Add voltage domain to Ruby example scripts

This patch adds the minimum required voltage domain configuration to
the Ruby example scripts.

9867:650fc966ed78 11-Sep-2013 Joel Hestness <jthestness@gmail.com>

config: Initialize and check cpt_starttick

The previous changeset (9816) that fixes the use of max ticks introduced the
variable cpt_starttick, which is used for setting the relative max tick.
Unfortunately, with checkpointing at an instruction count or with simpoints,
the checkpoint tick is not stored conveniently, so to ensure that cpt_starttick
is initialized, set it to 0. Also, if using --rel-max-tick, check the use of
instruction counts or simpoints to warn the user that the max tick setting does
not include the checkpoint ticks.

9862:54d6728d99cf 06-Sep-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: correct naming of routers

The routers are created before the network class. This results in the routers
becoming children of the first link they are connected to and they get generic
names like int_node and node_b. This patch creates the network object first
and passes it to the topology creation function. Now the routers are children
of the network object and names are much more sensible.

9845:3f6e2f267aba 26-Aug-2013 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Fix configuration files for bare-metal binaries.

9841:69c158420c51 20-Aug-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add option for number of transitions per cycle
The number of transitions per cycle that a controller can carry out is
a proxy for the number of ports that a controller has. This value is
currently 32 which is way too high. The patch introduces an option
for the number of ports and uses this option in the protocol files
to set the number of transitions. The default value is being set to
4. None of the se regressions change. Ruby stats for the fs regression
change and are being updated.

9836:4411b4e0c03a 19-Aug-2013 Andreas Hansson <andreas.hansson@arm.com>

config: Command line support for multi-channel memory

This patch adds support for specifying multi-channel memory
configurations on the command line, e.g. 'se/fs.py
--mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it
enhances the functionality of MemConfig and moves the existing
makeMultiChannel class method from SimpleDRAM to the support scripts.

The se/fs.py example scripts are updated to make use of the new
feature.

9835:cc7a7fc71c42 19-Aug-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Change AbstractMemory defaults to match the common case

This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.

9827:f47274776aa0 19-Aug-2013 Akash Bagdia <akash.bagdia@arm.com>

power: Add voltage domains to the clock domains

This patch adds the notion of voltage domains, and groups clock
domains that operate under the same voltage (i.e. power supply) into
domains. Each clock domain is required to be associated with a voltage
domain, and the latter requires the voltage to be explicitly set.

A voltage domain is an independently controllable voltage supply being
provided to section of the design. Thus, if you wish to perform
dynamic voltage scaling on a CPU, its clock domain should be
associated with a separate voltage domain.

The current implementation of the voltage domain does not take into
consideration cases where there are derived voltage domains running at
ratio of native voltage domains, as with the case where there can be
on-chip buck/boost (charge pumps) voltage regulation logic.

The regression and configuration scripts are updated with a generic
voltage domain for the system, and one for the CPUs.

9826:014ff1fbff6d 19-Aug-2013 Andreas Hansson <andreas.hansson@arm.com>

config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.


common/FSConfig.py
example/fs.py
example/ruby_fs.py
ruby/MESI_CMP_directory.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Network_test.py
ruby/Ruby.py
/gem5/tests/configs/alpha_generic.py
/gem5/tests/configs/arm_generic.py
/gem5/tests/configs/base_config.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing-ruby.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/pc-switcheroo-full.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/realview-switcheroo-atomic.py
/gem5/tests/configs/realview-switcheroo-full.py
/gem5/tests/configs/realview-switcheroo-o3.py
/gem5/tests/configs/realview-switcheroo-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/tsunami-switcheroo-full.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
/gem5/tests/configs/x86_generic.py
9816:971507cbbe65 18-Jul-2013 Joel Hestness <jthestness@gmail.com>

Configs: Fix up maxtick and maxtime

This patch contains three fixes to max tick options handling in Options.py and
Simulation.py:

1) Since the global simulator frequency isn't bound until m5.instantiate()
is called, the maxtick resolution needs to happen after this call, since
changes to the global frequency will cause m5.simulate() to misinterpret the
maxtick value. Shuffling this also requires tweaking the checkpoint directory
handling to signal the checkpoint restore tick back to run(). Fixing this
completely and correctly will require storing the simulation frequency into
checkpoints, which is beyond the scope of this patch.

2) The maxtick option in Options.py was defaulted to MaxTicks, so the old code
would always skip over the maxtime part of the conditionals at the beginning
of run(). Change the maxtick default to None, and set the maxtick local
variable in run() appropriately.

3) To clarify whether max ticks settings are relative or absolute, split the
maxtick option into separate options, for relative and absolute. Ensure that
these two options and the maxtime option are handled appropriately to set the
maxtick variable in Simulation.py.

9815:3b3b94536547 18-Jul-2013 Andreas Hansson <andreas.hansson>

config: Update script to set cache line size on system

This patch changes the config scripts such that they do not set the
cache line size per cache instance, but rather for the system as a
whole.

9800:5fdd91246b7b 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

configs: rearrange the available options in Options.py
It also changes the instantiation of physmem in se.py so as to make
use of the memory size supplied by the mem_size option.

9798:52679402e09c 28-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: check for compatibility between mem size and num dirs
The configuration scripts provided for ruby assume that the available
physical memory is equally distributed amongst the directory controllers.
But there is no check to ensure this assumption has been adhered to. This
patch adds the required check.

9793:6e6cefc1db1f 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

sim: Add the notion of clock domains to all ClockedObjects

This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.

9791:39c75548bcd4 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Rename clock option to Ruby clock

This patch changes the 'clock' option to 'ruby-clock' as it is only
used by Ruby.

9790:ccc428657233 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Add a system clock command-line option

This patch adds a 'sys_clock' command-line option and use it to assign
clocks to the system during instantiation.

As part of this change, the default clock in the System class is
removed and whenever a system is instantiated a system clock value
must be set. A default value is provided for the command-line option.

The configs and tests are updated accordingly.

9789:233420718e61 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Add a CPU clock command-line option

This patch adds a 'cpu_clock' command-line option and uses the value
to assign clocks to components running at the CPU speed (L1 and L2
including the L2-bus). The configuration scripts are updated
accordingly.

The 'clock' option is left unchanged in this patch as it is still used
by a number of components. In follow-on patches the latter will be
disambiguated further.

9788:5558ee8dd7d9 27-Jun-2013 Akash Bagdia <akash.bagdia@arm.com>

config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

9756:0b4a08751b42 13-Jun-2013 Nilay Vaish <nilay@cs.wisc.edu>

config: Do not instantiate membus when using ruby
This patch moves the instantiation of system.membus in se.py to the area of
code where classic memory system has been dealt with. Ruby does not require
this bus and hence it should not be instantiated.

9736:20ae86ebd4c2 03-Jun-2013 Andreas Sandberg <andreas@sandberg.pp.se>

config: Add missing CPUs to --restore-with-cpu

The --restore-with-cpu option didn't use CpuConfig.cpu_names() to
determine which CPU names are valid, instead it used a static list of
known CPU names. This changeset makes the option parsing code use the
CPU list from the CpuConfig module instead.

9728:7daeab1685e9 30-May-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: More descriptive DRAM config names

This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.

Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.

9709:fe54045c8670 30-May-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Add a LPDDR3-1600 configuration

This patch adds a typical (leaning towards fast) LPDDR3 configuration
based on publically available data. As expected, it looks very similar
to the LPDDR2-S4 configuration, only with a slightly lower burst time.

9707:1305bec2733f 30-May-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Avoid explicitly zeroing the memory backing store

This patch removes the explicit memset as it is redundant and causes
the simulator to touch the entire space, forcing the host system to
allocate the pages.

Anonymous pages are mapped on the first access, and the page-fault
handler is responsible for zeroing them. Thus, the pages are still
zeroed, but we avoid touching the entire allocated space which enables
us to use much larger memory sizes as long as not all the memory is
actually used.

9697:f037e7b4a827 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: moesi hammer: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.

9696:744fb905297c 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: mesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.

9695:df1d9fee32a5 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: moesi cmp token: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.

9694:692776126391 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: moesi cmp directory: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.

9693:647f6624c46a 21-May-2013 Nilay Vaish <nilay@cs.wisc.edu>

configs: ruby: pass the option use_map to directory controller
The option was not being passed to directory controllers for the protocols
MOESI_CMP_token and MOESI_CMP_directory. This was resulting in an error
while instantiating the directory controller as it tries to access the
wrong type of memory.

9691:b1be1df904c9 14-May-2013 Anthony Gutierrez <atgutier@umich.edu>

cpu: remove local/globalHistoryBits params from branch pred

having separate params for the local/globalHistoryBits and the
local/globalPredictorSize can lead to inconsistencies if they
are not carefully set. this patch dervies the number of bits
necessary to index into the local/global predictors based on
their size.

the value of the localHistoryTableSize for the ARM O3 CPU has been
increased to 1024 from 64, which is more accurate for an A15 based
on some correlation against A15 hardware.

9677:773aae0990ae 23-Apr-2013 Marco Elver <marco.elver@ed.ac.uk>

config: Fix mem-type option not used in ruby_fs script
This fixes missing mem-type arguments to makeLinuxAlphaRubySystem and
makeLinuxX86System after a recent changeset allowing mem-type to be
configured via options missed fixing these calls.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9665:6dbdeee787cc 22-Apr-2013 Andreas Hansson <andreas.hansson@arm.com>

config: Add a mem-type config option to se/fs scripts

This patch enables selection of the memory controller class through a
mem-type command-line option. Behind the scenes, this option is
treated much like the cpu-type, and a similar framework is used to
resolve the valid options, and translate the short-hand description to
a valid class.

The regression scripts are updated with a hardcoded memory class for
the moment. The best solution going forward is probably to get the
memory out of the makeSystem functions, but Ruby complicates things as
it does not connect the memory controller to the membus.

9653:5307d06e1d0e 22-Apr-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

config: Add a KVM VM to systems with KVM CPUs

KVM-based CPUs need a KVM VM object in the system to manage
system-global KVM stuff (VM creation, interrupt delivery, memory
managment, etc.). This changeset adds a VM to the system if KVM has
been enabled at compile time (the BaseKvmCPU object exists) and a
KVM-based CPU has been selected at runtime.

9647:5b6b315472e7 22-Apr-2013 Dam Sunwoo <dam.sunwoo@arm.com>

cpu: generate SimPoint basic block vector profiles

This patch is based on http://reviews.m5sim.org/r/1474/ originally written by
Mitch Hayenga. Basic block vectors are generated (simpoint.bb.gz in simout
folder) based on start and end addresses of basic blocks.

Some comments to the original patch are addressed and hooks are added to create
and resume from checkpoints based on instruction counts dictated by external
SimPoint analysis tools.

SimPoint creation/resuming options will be implemented as a separate patch.

9638:a5f40a7aa41b 17-Apr-2013 Nilay Vaish <nilay@cs.wisc.edu>

config: ruby network test: remove piobus check

9634:37a6fb91f96d 09-Apr-2013 Joel Hestness <jthestness@gmail.com>

Configs: Fix handling of maxtick and take_checkpoints

In Simulation.py, calls to m5.simulate(num_ticks) will run the simulated system
for num_ticks after the current tick. Fix calls to m5.simulate in
scriptCheckpoints() and benchCheckpoints() to appropriately handle the maxticks
variable.

9626:3b51f4defa0d 02-Apr-2013 Anthony Gutierrez <atgutier@umich.edu>

rcs scripts: remove bbench.rcS

this run script shouldn't be used; bbench-ics.rcS or bbench-gb.rcS
should be used instead.

9622:d351a723eb02 28-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

x86: create space in bios memory map
As of now, we mark the top 1MB of memory space as unusable. Part of
it is actually usable and is required to be marked so by some of the
newer versions of linux kernel. This patch marks the top 639KB as usable.
This value was chosen by looking at QEMU's output for bios memory map.

9606:0a4b702628bd 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

config: return exit event instead of cause
changeset: a4739b6f799d made some changes that where an exit event
should have been returned in place of exit cause. This patch corrects
the error.

9594:219ad5fe8c04 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: convert Topology to regular class
The Topology class in Ruby does not need to inherit from SimObject class.
This patch turns it into a regular class. The topology object is now created
in the constructor of the Network class. All the parameters for the topology
class have been moved to the network class.

9593:9441ca79f3c8 22-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: network: move routers from topology to network

9577:91cac7c9c636 06-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: remove the functional copy of memory in se mode
This patch removes the functional copy of the memory that was maintained in
the se mode. Now ruby itself will provide the data.

9576:2c094ad4dc70 06-Mar-2013 Nilay Vaish <nilay@cs.wisc.edu>

ruby: garnet: fixed: implement functional access

9562:7f9d6e971ada 20-Feb-2013 Ali Saidi <saidi@eecs.umich.edu>

config: Fix --prog-interval command line option

9539:0ac00d9a8aaf 15-Feb-2013 Anthony Gutierrez <atgutier@umich.edu>

options: add command line option for dtb file

9522:9290a0198c50 15-Feb-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

config: Remove O3 dependencies

The default cache configuration script currently import the O3_ARM_v7a
model configuration, which depends on the O3 CPU. This breaks if gem5
has been compiled without O3 support. This changeset removes the
dependency by only importing the model if it is requested by the
user. As a bonus, it actually removes some code duplication in the
configuration scripts.

9521:1cd02decbfd3 15-Feb-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

config: Move CPU handover logic to m5.switchCpus()

CPU switching consists of the following steps:
1. Drain the system
2. Switch out old CPUs (cpu.switchOut())
3. Change the system timing mode to the mode the new CPUs require
4. Flush caches if switching to hardware virtualization
5. Inform new CPUs of the handover (cpu.takeOverFrom())
6. Resume the system

m5.switchCpus() previously only did step 2 & 5. Since information
about the new processors' memory system requirements is now exposed,
do all of the steps above.

This patch adds automatic memory system switching and flush (if
needed) to switchCpus(). Additionally, it adds optional draining to
switchCpus(). This has the following implications:

* changeToTiming and changeToAtomic are no longer needed, so they have
been removed.

* changeMemoryMode is only used internally, so it is has been renamed
to be private.

* switchCpus requires a reference to the system containing the CPUs as
its first parameter.

WARNING: This changeset breaks compatibility with existing
configuration scripts since it changes the signature of
m5.switchCpus().

9520:ea7c03ae2d5e 15-Feb-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

config: Cleanup CPU configuration

The CPUs supported by the configuration scripts used to be
hard-coded. This was not ideal for several reasons. For example, the
configuration scripts depend on all CPU models even though only a
subset might have been compiled.

This changeset adds a new module to the configuration scripts that
automatically discovers the available CPU models from the compiled
SimObjects. As a nice bonus, the use of introspection allows us to
automatically generate a list of available CPU models suitable for
printing. This list is augmented with the Python doc string from the
underlying class if available.

9518:8faae62af8c3 15-Feb-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

cpu: Add CPU metadata om the Python classes

The configuration scripts currently hard-code the requirements of each
CPU. This is clearly not optimal as it makes writing new configuration
scripts painful and adding new CPU models requires existing scripts to
be updated. This patch adds the following class methods to the base
CPU and all relevant CPUs:

* memory_mode -- Return a string describing the current memory mode
(invalid/atomic/timing).

* require_caches -- Does the CPU model require caches?

* support_take_over -- Does the CPU support CPU handover?

9494:50da272a1300 10-Feb-2013 Andreas Sandberg <andreas@sandberg.pp.se>

config: Don't call sys.exit in interactive mode in run()

The run() method in Simulation.py used to call sys.exit() when the
simulator exits. This is undesirable when user has requested the
simulator to be run in interactive mode since it causes the simulator
to exit rather than entering the interactive Python environment.

9489:172dbcb74a0e 31-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

mem: Add DDR3 and LPDDR2 DRAM controller configurations

This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.

9480:d059f8a95a42 24-Jan-2013 Nilay Vaish <nilay@cs.wisc.edu>, Timothy Jones <timothy.jones@cl.cam.ac.uk>

branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.

9468:721718c62859 14-Jan-2013 Malek Musleh <malek.musleh@gmail.com>

config: move ruby objects under ruby_system in obj hierarchy
This patch moves the contollers to be children of the ruby_system instead of
'system' under the python object hierarchy. This is so that these objects
can inherit some of the ruby_system's parameter values without resorting to
calling a global system pointer during run-time.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9460:5532a1642108 08-Jan-2013 Ali Saidi <saidi@eecs.umich.edu>

config: Fix issue with changeset: a4739b6f799d.

9457:a4739b6f799d 08-Jan-2013 Lluís Vilanova <vilanova@ac.upc.edu>

util: add m5_fail op.

Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully.

For example, one can use:

/path/to/benchmark args || /sbin/m5 fail 1

and thus ensure gem5 will exit with an error if the benchmark fails.

9433:34971d2e0019 07-Jan-2013 Andreas Sandberg <Andreas.Sandberg@ARM.com>

cpu: Rename defer_registration->switched_out

The defer_registration parameter is used to prevent a CPU from
initializing at startup, leaving it in the "switched out" mode. The
name of this parameter (and the help string) is confusing. This patch
renames it to switched_out, which should be more descriptive.

9408:10a84dceab25 07-Jan-2013 Andreas Hansson <andreas.hansson@arm.com>

config: Do not use hardcoded physmem in fs script

This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.

The change is needed to allow interleaved memory controllers in the
system.

9384:877293183bdf 07-Jan-2013 Andreas Sandberg <Andreas.Sandberg@arm.com>

arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.

9366:bf8eb26c7b7e 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: add support for prefetching to MESI protocol

9365:644be05ee7c2 11-Dec-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: modify the directed tester to read/write streams
The directed tester supports only generating only read or only write accesses. The
patch modifies the tester to support streams that have both read and write accesses.

9360:515891d9057a 06-Dec-2012 Erik Tomusk <E.Tomusk@sms.ed.ac.uk>

TournamentBP: Fix some bugs with table sizes and counters
globalHistoryBits, globalPredictorSize, and choicePredictorSize are decoupled.
globalHistoryBits controls how much history is kept, global and choice
predictor sizes control how much of that history is used when accessing
predictor tables. This way, global and choice predictors can actually be
different sizes, and it is no longer possible to walk off the predictor arrays
and cause a seg fault.

There are now individual thresholds for choice, global, and local saturating
counters, so that taken/not taken decisions are correct even when the
predictors' counters' sizes are different.

The interface for localPredictorSize has been removed from TournamentBP because
the value can be calculated from localHistoryBits.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

9357:94383c5124d2 19-Nov-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Fix description of checkpoint option from cycle to tick

This patch merely updates the description of the "take-checkpoints"
option to reflect that it is specified in ticks and not in cycles.

9344:7f966113afd1 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

python: Rename doDrain()->drain() and make it do the right thing

There is no point in exporting the old drain() method in
Simulate.py. It should only be used internally by doDrain(). This
patch moves the old drain() method into doDrain() and renames
doDrain() to drain().

9326:96ae1c545fb5 02-Nov-2012 Andreas Sandberg <Andreas.Sandberg@arm.com>

Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming

Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming
based on the assumption that the system does not need draining when
running in atomic mode. This is a false assumption since at least the
System class requires the system to be drained before it allows
switching of memory modes. This patch reverts that part of the
changeset.

9321:7f0464326b2b 30-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Unify caches used in regressions and adjust L2 MSHRs

This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.

9319:ab0a36d082bb 27-Oct-2012 Malek Musleh <malek.musleh@gmail.com>

ruby: set the is_icache param for caches
This patch sets the is_icache param for the L1 caches used in
the MESI and the MOESI CMP directory protocols.

9318:dec0b284ded9 27-Oct-2012 Jason Power <power.jg@gmail.com>, Joel Hestness <hestness@cs.wisc.edu>

Ruby: Use block size in configuring directory bits in address
This patch replaces hard coded values used in Ruby's configuration files
for setting directory bits with values based on the block size in use.

9317:2daeea4bce1b 26-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Add a check for fastmem only used with Atomic CPU

This patch adds an additional check to ensure that the fastmem option
is only used if the system is using the Atomic CPU.

9316:4e2dc4b01c50 26-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Remove unused mem_size in fs.py

This patch removes a segment of dead code that is never used.

9315:2e00867b5001 26-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Fix the cache class naming in regression scripts

This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.

9311:227d19399b51 25-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Use SimpleDRAM in full-system, and with o3 and inorder

This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.

9310:aa7bf10e822a 25-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

config: Use shared cache config for regressions

This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.

9302:c2e70a9bc340 15-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.

With this patch applied, functional writes always succeed. But functional
reads can still fail.


example/ruby_mem_test.py
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-msg.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-msg.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-msg.sm
/gem5/src/mem/protocol/Network_test-msg.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/protocol/RubySlicc_MemControl.sm
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/buffers/MessageBufferNode.hh
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/simple/PerfectSwitch.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/Switch.cc
/gem5/src/mem/ruby/network/simple/Switch.hh
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Message.hh
/gem5/src/mem/ruby/slicc_interface/NetworkMessage.hh
/gem5/src/mem/ruby/slicc_interface/RubyRequest.cc
/gem5/src/mem/ruby/slicc_interface/RubyRequest.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/RubyMemoryControl.cc
/gem5/src/mem/ruby/system/RubyMemoryControl.hh
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/slicc/ast/TypeDeclAST.py
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/SymbolTable.py
/gem5/src/mem/slicc/symbols/Type.py
9288:3d6da8559605 15-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

Mem: Use cycles to express cache-related latencies

This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.


common/Caches.py
common/O3_ARM_v7a.py
example/fs.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/base.cc
/gem5/src/mem/cache/base.hh
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/prefetch/Prefetcher.py
/gem5/src/mem/cache/prefetch/base.cc
/gem5/src/mem/cache/prefetch/base.hh
/gem5/src/mem/cache/prefetch/ghb.cc
/gem5/src/mem/cache/prefetch/ghb.hh
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/prefetch/tagged.cc
/gem5/src/mem/cache/prefetch/tagged.hh
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
9284:f4ff625eae56 15-Oct-2012 Andreas Hansson <andreas.hansson@arm.com>

Regression: Use CPU clock and 32-byte width for L1-L2 bus

This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.

Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.

A separate patch will update the stats.

9274:ba635023d4bb 02-Oct-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.

9268:a0ca00815cc4 28-Sep-2012 Malek Musleh <malek.musleh@gmail.com>

Configs: SE script fix for Alpha and Ruby simulations

PIO interrupt port is only present for x86. Do not attempt to connect
for other ISAs.

9267:f8c85a7d109f 27-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Configs: Fix memtest cache latency to match new parameters

This patch changes the memtest config to use the new response latency
of the cache model.

9266:6ed55550d19e 27-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Configs: Fix memtest.py by moving the system port

The memtest.py script used to connect the system port directly to the
SimpleMemory, but the latter is now single ported. Since the system
port is not used for anything in this particular example, a quick fix
is to attach it to the functional bus instead.

9263:066099902102 25-Sep-2012 Mrinmoy Ghosh <mrinmoy.ghosh@arm.com>

Cache: add a response latency to the caches

In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.

9232:3bb99fab80d4 19-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

AddrRange: Simplify AddrRange params Python hierarchy

This patch simplifies the Range object hierarchy in preparation for an
address range class that also allows striping (e.g. selecting a few
bits as matching in addition to the range).

To extend the AddrRange class to an AddrRegion, the first step is to
simplify the hierarchy such that we can make it as lean as possible
before adding the new functionality. The only class using Range and
MetaRange is AddrRange, and the three classes are now collapsed into
one.

9222:dfc6a4ba338c 12-Sep-2012 Joel Hestness <hestness@cs.wisc.edu>

se.py Ruby: Connect TLB walker ports
In order to ensure correct functionality of switch CPUs, the TLB walker ports
must be connected to the Ruby system in x86 simulation.

This fixes x86 assertion failures that the TLB walker ports are not connected
during the CPU switch process.

9221:4f54b0f229b5 12-Sep-2012 Joel Hestness <hestness@cs.wisc.edu>

Standard Switch: Drain the system before switching CPUs
When switching from an atomic CPU to any of the timing CPUs, a drain is
unnecessary since no events are scheduled in atomic mode. However, when
trying to switch CPUs starting with a timing CPU, there may be events
scheduled. This change ensures that all events are drained from the system
by calling m5.drain before switching CPUs.

9217:d3772fe85fa6 11-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

se.py: removes error in passing options to a binary

9215:a67412670f37 11-Sep-2012 Andreas Hansson <andreas.hansson@arm.com>

Checkpoint: Pass maxtick to avoid undefined variable

This patch fixes a bug in scriptCheckpoints, where maxtick was used
undefined. The bug caused checkpointing by means of --take-checkpoints
to fail.

9197:0281650db548 09-Sep-2012 Nilay Vaish <nilay@cs.wisc.edu>

se.py: support specifying multiple programs via command line
This patch allows for specifying multiple programs via command line. It also
adds an option for specifying whether to use of SMT. But SMT does not work for
the o3 cpu as of now.

9164:d112473185ea 22-Aug-2012 Andreas Hansson <andreas.hansson@arm.com>

Bridge: Remove NACKs in the bridge and unify with packet queue

This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.

The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).

As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.

A bit of tidying up has also been done as part of the simplifications.

Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.

9156:38dd0780322a 21-Aug-2012 Andreas Hansson <andreas.hansson@arm.com>

Checkpoint: Fix broken checkpointing functionality

This patch fixes the checkpointing by ensuring that the directory is
passer to the scriptCheckpoints function, and that the num_checkpoints
is not used before it is initialised.

9154:198352d722e4 17-Aug-2012 Jason Power <power.jg@gmail.com>

Ruby: Add RubySystem parameter to MemoryControl
This guarantees that RubySystem object is created before the MemoryController
object is created.

9151:a4faa7dde56c 15-Aug-2012 Anthony Gutierrez <atgutier@umich.edu>

configs: add option for repeatedly switching back-and-forth between cpu types.

This patch adds a --repeat-switch option that will enable repeat core
switching at a user defined period (set with --switch-freq option).
currently, a switch can only occur between like CPU types. inorder CPU
switching is not supported.

*note*
this patch simply allows a config that will perform repeat switching, it
does not fix drain/switchout functionality. if you run with repeat switching
you will hit assertion failures and/or your workload with hang or die.

9148:a7a72f42919e 10-Aug-2012 Jason Power <powerjg@cs.wisc.edu>

Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.

9140:cfd2a8364ea1 06-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.

9139:ee038fbbe5d2 06-Aug-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.

9129:b57966a6c512 23-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Config: Use clock option in se/fs script and pass to switch_cpus

This patch changes the se and fs script to use the clock option and
not simply set the CPUs clock to 2 GHz. It also makes a minor change
to the assignment of the switch_cpus clock to allow different clocks.

9120:48eeef8a0997 12-Jul-2012 Andreas Hansson <andreas.hansson@arm.com>

Mem: Make SimpleMemory single ported

This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.

9108:ad76a669e9d9 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: remove the cpu assumptions for the random tester

9100:3caf131d7a95 11-Jul-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: changes how Topologies are created

Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.

9070:fa77985a87c6 11-Jun-2012 Anthony Gutierrez <atgutier@umich.edu>

configs: add run scripts for ics/gb versions of android and bbench

1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.

2) An rcS script is added for BBench on ICS.

3) Separates benchmark entries and rcS scripts for GB/ICS

4) Removes the debugging output from the existing BBench run script. These
print statements were used for debugging and they seemed to confuse users
into believing they should see some terminal output.

9061:135aa8f54bc4 07-Jun-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: call to setWorkCountOptions() for all ISAs

9060:ee4104e628f3 07-Jun-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.

9059:95b525b1d3a0 07-Jun-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: changes to a couple of error msgs

9036:6385cf85bf12 31-May-2012 Andreas Hansson <andreas.hansson@arm.com>

Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.


common/CacheConfig.py
common/FSConfig.py
example/memtest.py
example/se.py
splash2/cluster.py
splash2/run.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/mem/Bus.py
/gem5/src/mem/SConscript
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/coherent_bus.cc
/gem5/src/mem/coherent_bus.hh
/gem5/src/mem/noncoherent_bus.cc
/gem5/src/mem/noncoherent_bus.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-checker.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
9006:431fcc41ae4a 16-May-2012 Andreas Hansson <andreas.hansson@arm.com>

Config: Fix a typo in the se.py script for setting fastmem

This patch changes a hardcoded index 0 to the appropriate CPU index so
that fastmem is set correctly for all the CPUs in the system.

8976:73b178a5d564 03-May-2012 Jayneel Gandhi <jayneel@cs.wisc.edu>

Config: Fix help msg for option --mem-size

8957:0bba1c59b4d1 17-Apr-2012 Jayneel Gandhi <jayneel@cs.wisc.edu>

SE Config: Changed se.py to support multithreaded mode
Multithreaded programs did not run by just specifying the binary once on the
command line of SE mode.The default mode is multi-programmed mode. Added
check in SE mode to run multi-threaded programs in case only one program is
specified with multiple CPUS. Default mode is still multi-programmed mode.

8956:1df031399919 16-Apr-2012 Jayneel Gandhi <jayneel@cs.wisc.edu>

Config: Add command line options for disk image and memory size
Added the options to Options.py for FS mode with backward compatibility. It is
good to provide an option to specify the disk image and the memory size from
command line since a lot of disk images are created to support different
benchmark suites as well as per user needs. Change in program also leads to
change in memory requirements. These options provide the interface to provide
both disk image and memory size from the command line and gives more
flexibility.

8939:4c84b2566d2f 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: set SimpleTiming as the default cpu

8932:1b2c17565ac8 06-Apr-2012 Brad Beckmann <Brad.Beckmann@amd.com>

rubytest: seperated read and write ports.

This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.

8931:7a1dfb191e3f 06-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.


common/FSConfig.py
example/memtest.py
example/ruby_direct_test.py
example/ruby_mem_test.py
example/ruby_network_test.py
example/ruby_random_test.py
example/se.py
ruby/MESI_CMP_directory.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Network_test.py
ruby/Ruby.py
splash2/cluster.py
splash2/run.py
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/remote_gdb.hh
/gem5/src/arch/arm/ArmSystem.py
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/remote_gdb.hh
/gem5/src/arch/arm/system.cc
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/remote_gdb.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/remote_gdb.hh
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/dev/alpha/backdoor.cc
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/ide_disk.hh
/gem5/src/mem/AbstractMemory.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/SConscript
/gem5/src/mem/SimpleMemory.py
/gem5/src/mem/abstract_mem.cc
/gem5/src/mem/abstract_mem.hh
/gem5/src/mem/cache/mshr.cc
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/simple_mem.cc
/gem5/src/mem/simple_mem.hh
/gem5/src/sim/System.py
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-checker.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-dummychecker.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8929:4148f9af0b70 05-Apr-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer
port twice. While making use of the Ruby memory system in FS mode, DMA
ports were assigned peer twice, once for the classic memory system
and once for the Ruby memory system. This patch removes this double
assignment of peer ports.

8928:051bc173ea72 05-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Fix the example configurations option parsing

This patch fixes the, currently broken, Ruby example scripts to
reflect the changes in the parsing of command-line options.

8926:570b44fe6e04 03-Apr-2012 Andreas Hansson <andreas.hansson@arm.com>

Atomic: Remove the physmem_port and access memory directly

This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.

8923:820111f58fbb 30-Mar-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Remove the physMemPort and instead access memory directly

This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).

8920:99083b5b7ed4 28-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.

8919:c1366a30d5eb 27-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Move setWorkCountOptions() to Simulation.py
The function is presently defined in FSConfig.py, which does not seem to be
the correct place for it.

8899:0541a014b811 16-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

ruby_fs.py: Add call to createInterruptController()

8898:f777750a00e2 16-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

FSConfig.py: fix a typo makeLinuxAlphaRubySystem

8896:6df06e5975c6 11-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.

8894:351585c17699 09-Mar-2012 Ali Saidi <saidi@eecs.umich.edu>

ARM: Fix memory starting at non-zero address and exceeding max mem for a system.

8887:20ea02da9c53 09-Mar-2012 Geoffrey Blake <geoffrey.blake@arm.com>

CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.

8883:c92153af04ac 09-Mar-2012 Ali Saidi <Ali.Saidi@ARM.com>

cache: Allow main memory to be at disjoint address ranges.

8870:f95c4042f2d0 01-Mar-2012 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add support for Versatile Express extended memory map

Also clean up how we create boot loader memory a bit.

8863:50ce4deacda9 01-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later

8862:dedd8be81731 01-Mar-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: make option ruby available always

8858:c68ae0f78d8e 26-Feb-2012 Gabe Black <gblack@eecs.umich.edu>

Make the IO bridge accept address headed to all the local APICs.

8847:ef8630054b5e 14-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.

8846:2eaf1809c6c6 14-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

Script: Fix the scripts that use the num_cpus cache parameter

This patch merely removes the use of the num_cpus cache parameter
which no longer exists after the introduction of the masterIds. The
affected scripts fail when trying to set the parameter. Note that this
patch does not update the regression stats.

8845:a230379caf65 14-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Fix master/slave ports in Ruby and non-regression scripts

This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.

8839:eeb293859255 13-Feb-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Introduce the master/slave port roles in the Python classes

This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.


common/CacheConfig.py
common/FSConfig.py
example/fs.py
example/ruby_fs.py
example/se.py
ruby/Ruby.py
/gem5/src/arch/arm/ArmTLB.py
/gem5/src/arch/x86/X86LocalApic.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/arch/x86/interrupts.hh
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/networktest/NetworkTest.py
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/dev/Device.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Pci.py
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/arm/RealView.py
/gem5/src/dev/x86/I82094AA.py
/gem5/src/dev/x86/Pc.py
/gem5/src/dev/x86/SouthBridge.py
/gem5/src/dev/x86/i82094aa.hh
/gem5/src/dev/x86/intdev.hh
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/params.py
/gem5/src/sim/System.py
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
8836:922edffe734d 12-Feb-2012 Ali Saidi <saidi@eecs.umich.edu>

configs: fix minor config bugs posted on the mailing list

8831:6c08a877af8f 12-Feb-2012 Mrinmoy Ghosh <mrinmoy.ghosh@arm.com>

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

8815:deb3b3cff4a3 05-Feb-2012 Gabe Black <gblack@eecs.umich.edu>

X86: Rename the bridge which allows commnication back to the local APICs.

There was a collision with a name used in fs.py, and that causes that script
not to work when used with x86.

8810:00f0d0230596 01-Feb-2012 Ali Saidi <Ali.Saidi@ARM.com>

configs: More fixes for the memory system updates

8808:8af87554ad7e 31-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Merge with main repository.

8807:35e77c938919 29-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

Yet another merge with the main repository.

8803:f6c5785bc8fd 28-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Get rid of FULL_SYSTEM in the configs directory

8801:1a84c6a81299 28-Jan-2012 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Make SE vs. FS mode a runtime parameter.


common/FSConfig.py
example/fs.py
example/memtest.py
example/ruby_direct_test.py
example/ruby_fs.py
example/ruby_mem_test.py
example/ruby_network_test.py
example/ruby_random_test.py
example/se.py
splash2/cluster.py
splash2/run.py
/gem5/src/sim/Root.py
/gem5/src/sim/full_system.hh
/gem5/src/sim/root.cc
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/pc-o3-timing.py
/gem5/tests/configs/pc-simple-atomic.py
/gem5/tests/configs/pc-simple-timing.py
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-inorder.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
8732:fd510b6e124d 30-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

Ruby: Connect system port in Ruby network test

This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.

8729:9d7c1dc54954 28-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Enable O3 CPU and Ruby in FS mode

8725:73116cbeacba 26-Jan-2012 Ronald Dreslinski <rdreslin@umich.edu>

configs: actually add ARMv7a-like cpu/cache file

8724:7b4d80b26e35 26-Jan-2012 Ronald Dreslinski <rdreslin@umich.edu>

configs: A more realistic configuration of an ARM-like processor

8723:bbcc7afd82cb 25-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Fix fs.py by specifying the range size rather than end

This patch fixes the currently broken fs.py by specifying the size of
the bridge range rather than the end address. This effectively
subtracts one when determining the address range for the IO bridge
(from IO bus to membus), and thus avoids the overlapping ranges.

8718:062bf3879857 23-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Enable using O3 CPU and Ruby in SE mode

8717:5c253f1031d7 23-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and
replacements from the L1 cache of the Ruby memory system to the O3 CPU. The
implementation adds a list of ports to RubyPort. Whenever a replacement or an
invalidation is performed, the L1 cache forwards this to all the ports, which
is the LSQ in case of the O3 CPU.

8714:cd48e2802644 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Removing the default port peer from Python ports

In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.

8713:2f1a3e335255 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Make the bus bridge unidirectional and fixed address range

This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.

In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.

8706:b1838faf3bcc 17-Jan-2012 Andreas Hansson <andreas.hansson@arm.com>

MEM: Add port proxies instead of non-structural ports

Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy


common/FSConfig.py
example/se.py
ruby/Ruby.py
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/linux/process.cc
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/linux/system.hh
/gem5/src/arch/alpha/linux/threadinfo.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/stacktrace.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/system.hh
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/arch/alpha/utility.cc
/gem5/src/arch/alpha/vtophys.cc
/gem5/src/arch/alpha/vtophys.hh
/gem5/src/arch/arm/linux/process.cc
/gem5/src/arch/arm/linux/system.cc
/gem5/src/arch/arm/process.cc
/gem5/src/arch/arm/stacktrace.cc
/gem5/src/arch/arm/system.cc
/gem5/src/arch/arm/system.hh
/gem5/src/arch/arm/utility.cc
/gem5/src/arch/arm/vtophys.cc
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/power/linux/process.cc
/gem5/src/arch/power/process.cc
/gem5/src/arch/sparc/linux/syscalls.cc
/gem5/src/arch/sparc/process.cc
/gem5/src/arch/sparc/solaris/process.cc
/gem5/src/arch/sparc/system.cc
/gem5/src/arch/sparc/system.hh
/gem5/src/arch/sparc/utility.cc
/gem5/src/arch/sparc/vtophys.cc
/gem5/src/arch/x86/bios/intelmp.cc
/gem5/src/arch/x86/bios/intelmp.hh
/gem5/src/arch/x86/bios/smbios.cc
/gem5/src/arch/x86/bios/smbios.hh
/gem5/src/arch/x86/linux/syscalls.cc
/gem5/src/arch/x86/linux/system.cc
/gem5/src/arch/x86/process.cc
/gem5/src/arch/x86/stacktrace.cc
/gem5/src/arch/x86/system.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/elf_object.hh
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/base/loader/object_file.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/cpu/checker/thread_context.hh
/gem5/src/cpu/inorder/cpu.cc
/gem5/src/cpu/inorder/cpu.hh
/gem5/src/cpu/inorder/resources/cache_unit.cc
/gem5/src/cpu/inorder/resources/cache_unit.hh
/gem5/src/cpu/inorder/thread_context.cc
/gem5/src/cpu/inorder/thread_context.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/cpu.hh
/gem5/src/cpu/o3/lsq.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/o3/thread_context_impl.hh
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/simple/atomic.cc
/gem5/src/cpu/simple/atomic.hh
/gem5/src/cpu/simple/timing.cc
/gem5/src/cpu/simple/timing.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/cpu/thread_state.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/simple_disk.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_events.cc
/gem5/src/mem/SConscript
/gem5/src/mem/fs_translating_port_proxy.cc
/gem5/src/mem/fs_translating_port_proxy.hh
/gem5/src/mem/port.hh
/gem5/src/mem/port_impl.hh
/gem5/src/mem/port_proxy.hh
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPortProxy.cc
/gem5/src/mem/ruby/system/RubyPortProxy.hh
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/se_translating_port_proxy.cc
/gem5/src/mem/se_translating_port_proxy.hh
/gem5/src/mem/translating_port.cc
/gem5/src/mem/translating_port.hh
/gem5/src/mem/vport.cc
/gem5/src/mem/vport.hh
/gem5/src/sim/arguments.hh
/gem5/src/sim/process.cc
/gem5/src/sim/process.hh
/gem5/src/sim/process_impl.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/src/sim/system.cc
/gem5/src/sim/system.hh
/gem5/src/sim/vptr.hh
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/memtest.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-atomic-mp.py
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-mp.py
/gem5/tests/configs/simple-timing-ruby.py
/gem5/tests/configs/simple-timing.py
8690:26998f7e3461 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Use map option for selecting b/w sparse and memory vector

8689:ec5f79b99ac3 11-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Add support for restoring using a timing CPU
Currently there is an assumption that restoration from a checkpoint will
happen by first restoring to an atomic CPU and then switching to a timing
CPU. This patch adds support for directly restoring to a timing CPU. It
adds a new option '--restore-with-cpu' which is used to specify the type
of CPU to which the checkpoint should be restored to. It defaults to
'atomic' which was the case before.

8681:db978f3bcf51 10-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby: remove the files related to the tracer
The Ruby Tracer is out of date with the changes that are being carried
out to support checkpointing. Hence, it needs to be removed.

8671:7945abdd05cb 10-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Remove short option string for cpu type

8661:2d791d07c59b 09-Jan-2012 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add support for running multiple systems

8659:78f27ef5e919 09-Jan-2012 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add support for initparam m5 op

8657:776bc26ee1d4 09-Jan-2012 Ali Saidi <Ali.Saidi@ARM.com>

cpu2000: Add missing art benchmark to all

8653:15d4da9d2042 07-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Ruby Cache: Add param for marking caches as instruction only

8649:c3e7a961c727 05-Jan-2012 Nilay Vaish <nilay@cs.wisc.edu>

Config: Add an option of type 'choice' for cpu type
This patch adds a new option for cpu type. This option is of type 'choice'
which is similar to a C++ enum, except that it takes string values as
possible choices. Following options are being removed -- detailed, timing,
inorder.

8643:2f18d1ab589f 15-Dec-2011 Anthony Gutierrez <atgutier@umich.edu>

ARM: Update config files for Android/BBench images available on website.

8638:e8a093d1e131 01-Dec-2011 gloh

config: command line option to specify ruby output file

8635:23ba076b2cca 01-Dec-2011 Chris Emmons <chris.emmons@arm.com>

VNC: Add support for capturing frame buffer to file each time it is changed.

When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory. Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

8631:8c038d4cd210 01-Dec-2011 Chander Sudanthi <chander.sudanthi@arm.com>

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

8612:df3b7a1e883f 04-Nov-2011 Tushar Krishna <tushar@csail.mit.edu>

GARNET: adding a fault model for resilient on-chip network research.

This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.

8604:ccf744c70583 29-Oct-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby FS: Add the options for kernel and simulation script
These options were missing from the script ruby_fs.py. This patch adds these
options to the script.

8595:1f3c96b5d85e 19-Oct-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Fix small bug in config script that prevents android from booting

8528:1f95c9a0bb2f 19-Aug-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add some MP regressions and clean up the disk images and kernels a bit


common/Benchmarks.py
common/FSConfig.py
/gem5/tests/SConscript
/gem5/tests/configs/realview-o3-dual.py
/gem5/tests/configs/realview-o3.py
/gem5/tests/configs/realview-simple-atomic-dual.py
/gem5/tests/configs/realview-simple-atomic.py
/gem5/tests/configs/realview-simple-timing-dual.py
/gem5/tests/configs/realview-simple-timing.py
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
/gem5/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
/gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
8525:5f3fe76e7950 19-Aug-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add VExpress_E support with PCIe to gem5

8524:1ddd1aa0e55b 19-Aug-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add support for Versatile Express boards

8482:353abb676fa2 02-Aug-2011 Nilay Vaish<nilay@cs.wisc.edu>

Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.

8477:4a6c166f61f7 26-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Fix instantiations of DMA controller and sequencer
The patch on Ruby functional accesses made changes to the process of
instantiating controllers and sequencers. The DMA controller and
sequencer was not updated, hence this patch.

8475:248a1a32e31b 25-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Fix dma controller configs/ruby/MI_example.py
The dma controller in configs/ruby/MI_example.py was not being set correctly.
This patch fixes it.

8467:82ff928182c5 11-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

se.py: Fixes the way ruby's options are added

8446:be8f4157c8f4 03-Jul-2011 Nilay Vaish<nilay@cs.wisc.edu>

Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.

8437:94c7423ecd87 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>

config: removed unnecessary slashes
This patch removes unnecessary slashes from a couple of python scripts.

8436:5648986156db 30-Jun-2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu>

Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.


example/ruby_direct_test.py
example/ruby_fs.py
example/ruby_mem_test.py
example/ruby_network_test.py
example/ruby_random_test.py
example/se.py
ruby/MESI_CMP_directory.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Ruby.py
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/protocol/MESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MI_example-cache.sm
/gem5/src/mem/protocol/MI_example-dir.sm
/gem5/src/mem/protocol/MI_example-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_directory-dma.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L1cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-L2cache.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dir.sm
/gem5/src/mem/protocol/MOESI_CMP_token-dma.sm
/gem5/src/mem/protocol/MOESI_hammer-cache.sm
/gem5/src/mem/protocol/MOESI_hammer-dir.sm
/gem5/src/mem/protocol/MOESI_hammer-dma.sm
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
/gem5/src/mem/slicc/ast/MemberExprAST.py
/gem5/tests/configs/memtest-ruby.py
/gem5/tests/configs/rubytest-ruby.py
/gem5/tests/configs/simple-timing-mp-ruby.py
/gem5/tests/configs/simple-timing-ruby.py
8354:26be660e365a 17-Jun-2011 Gedare Bloom <gedare@gwmail.gwu.edu>

ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.

8323:fd20dcf1a9aa 23-May-2011 Steve Reinhardt <steve.reinhardt@amd.com>

config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children. This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration. At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation. For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().

8322:19949c6de823 23-May-2011 Steve Reinhardt <steve.reinhardt@amd.com>

config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.

8318:3f37cc5d25bc 23-May-2011 Korey Sewell <ksewell@umich.edu>

configs: missed spot progress-interval change

8312:de2451e66935 21-May-2011 Tushar Krishna <tushar@csail.mit.edu>

configs: remove -p from ruby_network_test.py

A recent patch broke the ruby network tester by adding -p inside Options.py
which conflicts with the -p inside ruby_network_test.py.
Have removed -p from ruby_network_test.py

8311:7b42aba8e5f2 20-May-2011 Korey Sewell <ksewell@umich.edu>

configs: cleanup redundant/unused options
maxinsts & max_inst redundant
prog_intvl and profile seem redundant, but profile looks to be unused
add -p option for progress intervals

8293:db269e704d07 07-May-2011 Tushar Krishna <tushar@csail.mit.edu>

NetworkTest: added sim_cycles parameter to the network tester.

The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly pass --maxticks from the
command line as before. If fixed_pkts is enabled, the tester only
injects maxpackets number of packets, else it keeps injecting till sim_cycles.
The tester also works with zero command line arguments now.

8287:45f3ac6b6a1c 04-May-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Configure bootloader parameters

8258:7c377f5162f8 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

8257:7226aebb77b4 28-Apr-2011 Brad Beckmann <Brad.Beckmann@amd.com>

network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.


ruby/MESI_CMP_directory.py
ruby/MI_example.py
ruby/MOESI_CMP_directory.py
ruby/MOESI_CMP_token.py
ruby/MOESI_hammer.py
ruby/Network_test.py
ruby/Ruby.py
/gem5/src/mem/protocol/RubySlicc_Exports.sm
/gem5/src/mem/ruby/network/BasicLink.cc
/gem5/src/mem/ruby/network/BasicLink.hh
/gem5/src/mem/ruby/network/BasicLink.py
/gem5/src/mem/ruby/network/BasicRouter.cc
/gem5/src/mem/ruby/network/BasicRouter.hh
/gem5/src/mem/ruby/network/BasicRouter.py
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/Topology.cc
/gem5/src/mem/ruby/network/Topology.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/SConscript
/gem5/src/mem/ruby/network/orion/NetworkPower.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/topologies/Crossbar.py
/gem5/src/mem/ruby/network/topologies/Mesh.py
/gem5/src/mem/ruby/network/topologies/MeshDirCorners.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
8246:914389024c33 20-Apr-2011 Nathan Binkert <nate@binkert.org>

python: fix another bug from changes to main.py

8212:134bd699967a 04-Apr-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Include IDE/CF controller by default in PBX model.

Frame buffer and boot linux:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit
Linux from a CF card:
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit
Run Android
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android
Run MP
./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38

8211:5275c2fbe957 04-Apr-2011 Anthony Gutierrez <atgutier@umich.edu>

Sim: Fix Simulation.py to allow more than 1 core for standard switching.

This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.

8184:a8d64545cda6 28-Mar-2011 Somayeh Sardashti <somayeh@cs.wisc.edu>

This patch supports cache flushing in MOESI_hammer

8183:1333bd6cc2eb 28-Mar-2011 Nilay Vaish<nilay@cs.wisc.edu>

Config: Import math in MI_example.py

8180:d8587c913ccf 25-Mar-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed cache index setting

8171:19444b1f092c 21-Mar-2011 Tushar Krishna <tushar@csail.mit.edu>

This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.

8169:89cd8302abd3 20-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

configs: combine ruby_se.py and se.py to avoid all that code duplication

8168:5cbb0a68dce1 20-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

enable x86 workloads on se.py

8167:f596091c854d 20-Mar-2011 Lisa Hsu <Lisa.Hsu@amd.com>

se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads. Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.

8145:21e4f3a569fb 17-Mar-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Bare metal system should have 256MB of RAM.

8134:b01a51ff05fa 17-Mar-2011 Ali Saidi <Ali.Saidi@ARM.com>

Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.

8088:ac1bd3d1aa54 24-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

Configs: Explicitly import env in Benchmarks.py

env was being implicitly imported into Benchmarks.py through SysPaths.py.
This change brings it in explicitly in the file where it's used.

8061:08e91664adac 23-Feb-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Clarifies creation of Linux and baremetal ARM systems.

makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified. Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.

8057:5a8208fa1600 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

configs: cache: add cache line size option

8056:8fe2d7ff1111 23-Feb-2011 Korey Sewell <ksewell@umich.edu>

configs: set default cache params
It's confusing (especially to new users), when you are setting some standard
parameters (as defined in Options.py) and they aren't reflected in the simulations
so we might as well link the settings in CacheConfig.py to those in Options.py

7949:e59dac494020 11-Feb-2011 Ali Saidi <Ali.Saidi@ARM.com>

VNC: Add VNC server to M5

7938:685719afafe6 08-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

memtest: due to contention increase, increased deadlock threshold

7937:bb6411d45356 08-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

config: fixed minor bug connecting dma devices to ruby

7925:6823ef6d7a9f 07-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

X86, Config: Move the setting of work count options to a separate function.

This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.

7920:39c86a8306d2 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

boot: script that creates a checkpoint after Linux boot up

7917:d9afb18a5008 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: numa bit fix for sparse memory

7914:eee5bb0fb8ea 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

m5: added work completed monitoring support

7905:00ad807ed2ca 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: x86 fs config support

7904:6f5299ff8260 07-Feb-2011 Brad Beckmann <Brad.Beckmann@amd.com>

MOESI_hammer: Added full-bit directory support

7877:19beb0676222 03-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.

7876:189b9b258779 03-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.

7869:e9edb137c872 02-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Change how the default disk image gets set up.

The disk image to use was always being forced to a particular value. This
change changes what disk image is selected as the default based on the
architecture being built. In the future, a more sophisticated system might be
used that selected a path based on certain rules instead of relying on one off
file names.

7868:6029008db669 01-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.

7861:4ebff121cc0e 19-Jan-2011 Gabe Black <gblack@eecs.umich.edu>

Time: Add a mechanism to prevent M5 from running faster than real time.

M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.

7832:de7601e6e19d 10-Jan-2011 Nathan Binkert <nate@binkert.org>

ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace


ruby/Ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/buffers/MessageBuffer.cc
/gem5/src/mem/ruby/buffers/MessageBuffer.hh
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Debug.py
/gem5/src/mem/ruby/common/Global.cc
/gem5/src/mem/ruby/common/Global.hh
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/common/Set.cc
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/filters/BulkBloomFilter.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/Throttle.cc
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
/gem5/src/mem/ruby/storebuffer/storebuffer.cc
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/tester/DeterministicDriver.cc
/gem5/src/mem/ruby/tester/RaceyDriver.cc
/gem5/src/mem/ruby/tester/RaceyPseudoThread.cc
/gem5/src/mem/ruby/tester/test_framework.cc
/gem5/src/mem/slicc/symbols/StateMachine.py
/gem5/src/mem/slicc/symbols/Type.py
7809:9d94b886c61b 03-Jan-2011 Nilay Vaish<nilay@cs.wisc.edu>

Ruby: Add option for random seed to Ruby.py
This patch adds an option to the script Ruby.py for setting the parameter
m_random_seed used for randomizing delays in the memory system. The option
can be specified as "--random_seed <seed value>".

7787:af976dd0c6e7 07-Dec-2010 Ali Saidi <Ali.Saidi@ARM.com>

Configs: Automatically choose the correct hello world binary.

7766:1252ec1c8714 17-Nov-2010 Gabe Black <gblack@eecs.umich.edu>

Config: Change misleading "cycle" message to say "tick".

Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".

7750:0731d632db76 15-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Add support for a dumb IDE controller

7730:982b4c6c1470 08-Nov-2010 Ali Saidi <Ali.Saidi@ARM.com>

Mem: Finish half-baked support for mmaping file in physmem.

Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.

7716:fa706473bcd5 22-Oct-2010 Gabe Black <gblack@eecs.umich.edu>

Configs: Stop setting the "mem" parameter in splash2 config files.

This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.

7663:abb78217021f 30-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: fixed numa high bit setting bug

7662:b4d3a30575a1 30-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: minor fix to probe filter index setting

7661:b03534522b91 29-Aug-2010 Nathan Binkert <nate@binkert.org>

ruby: None, not none

7656:dd4d229b716d 26-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

memtest: scale associativity and mshrs according to config
Use the actual fanouts in the tree specification to scale
cache associativity and mshrs instead of dumb constants.

7635:a322932de08f 24-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: changed ruby config file names to be consistent

7634:9a469388e8b3 24-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: remove ruby's requirement on the timing cmd line param

Since ruby only works in timing mode, explicitly requiring the timing cmd line
param to be specified is not necessary.

7633:d8112aa18a1b 24-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: fixed ruby dma device connections

7632:acf43d6bbc18 24-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.


example/determ_test.py
example/memtest-ruby.py
example/ruby_direct_test.py
example/rubytest.py
ruby/MOESI_hammer.py
/gem5/src/cpu/directedtest/DirectedGenerator.cc
/gem5/src/cpu/directedtest/DirectedGenerator.hh
/gem5/src/cpu/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/directedtest/RubyDirectedTester.py
/gem5/src/cpu/directedtest/SConscript
/gem5/src/cpu/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/memtest/MemTest.py
/gem5/src/cpu/memtest/SConscript
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/rubytest/Check.cc
/gem5/src/cpu/rubytest/Check.hh
/gem5/src/cpu/rubytest/CheckTable.cc
/gem5/src/cpu/rubytest/CheckTable.hh
/gem5/src/cpu/rubytest/RubyTester.cc
/gem5/src/cpu/rubytest/RubyTester.hh
/gem5/src/cpu/rubytest/RubyTester.py
/gem5/src/cpu/rubytest/SConscript
/gem5/src/cpu/testers/directedtest/DirectedGenerator.cc
/gem5/src/cpu/testers/directedtest/DirectedGenerator.hh
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.cc
/gem5/src/cpu/testers/directedtest/InvalidateGenerator.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.cc
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.hh
/gem5/src/cpu/testers/directedtest/RubyDirectedTester.py
/gem5/src/cpu/testers/directedtest/SConscript
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.cc
/gem5/src/cpu/testers/directedtest/SeriesRequestGenerator.hh
/gem5/src/cpu/testers/memtest/MemTest.py
/gem5/src/cpu/testers/memtest/SConscript
/gem5/src/cpu/testers/memtest/memtest.cc
/gem5/src/cpu/testers/memtest/memtest.hh
/gem5/src/cpu/testers/rubytest/Check.cc
/gem5/src/cpu/testers/rubytest/Check.hh
/gem5/src/cpu/testers/rubytest/CheckTable.cc
/gem5/src/cpu/testers/rubytest/CheckTable.hh
/gem5/src/cpu/testers/rubytest/RubyTester.cc
/gem5/src/cpu/testers/rubytest/RubyTester.hh
/gem5/src/cpu/testers/rubytest/RubyTester.py
/gem5/src/cpu/testers/rubytest/SConscript
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/Sequencer.cc
7586:da93206873dc 23-Aug-2010 Ali Saidi <Ali.Saidi@arm.com>

ARM: Add configuration for Linux/Full System

7566:6919df046bba 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Recycle latency fix for hammer

Patch allows each individual message buffer to have different recycle latencies
and allows the overall recycle latency to be specified at the cmd line. The
patch also adds profiling info to make sure no one processor's requests are
recycled too much.

7564:3559d47839a1 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added probe filter support to hammer

7563:406e98960def 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed DirectoryMemory's numa_high_bit configuration

This fix includes the off-by-one bit selection bug for numa mapping.

7561:02a9a597fce4 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Disable migratory sharing for token and hammer

This patch allows one to disable migratory sharing for those cache blocks that
are accessed by atomic requests. While the implementations are different
between the token and hammer protocols, the motivation is the same. For
Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that
have been locked by LL accesses. Therefore, locked blocks should not transfer
write permissions when responding to these load requests. Instead, only they
only transfer read permissions so that the subsequent SC access can possibly
succeed.

7557:bd48f4547e77 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Improved try except blocks in ruby creation

Replaced the sys.exit in the try-except blocks with raise so that the python
call stack will be printed

7555:ccd55d73c75d 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: added cmd options to control ruby debug

7553:fcdd99057b8a 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Resurrected Ruby's deterministic tests

Added the request series and invalidate deterministic tests as new cpu models
and removed the no longer needed ruby tests

7551:b10ee98aea91 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reduced ruby latencies

The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.

7544:90c5eb6a5e66 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

memtest: Memtester support for DMA

This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch. Since Ruby does not work in atomic
mode, the atomic mode options are removed.

7541:1e1f63dfd130 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: Improve ruby simobject names

This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.

7539:9ca6602c5345 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added token broadcast config params to cmd options

7538:5691b9dd51f4 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: reorganized how ruby specifies command-line options

7535:7f8213cb2337 20-Aug-2010 Brad Beckmann <Brad.Beckmann@amd.com>

config: moved python protocol config files

Moved the python protocol config files back to their original location to avoid
addToPath calls.

7534:c76a14014c27 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.

7531:f5e86115a07a 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

sim: fold checkpoint restore code into instantiate()
The separate restoreCheckpoint() call is gone; just pass
the checkpoint dir as an optional arg to instantiate().
This change is a precursor to some more extensive
reworking of the startup code.

7530:89b6893554f5 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

configs: clean up checkpoint code in Simulation.py
Small change to clean up some redundant code.
Should not have any functional impact.

7525:722f2ad014a7 17-Aug-2010 Steve Reinhardt <steve.reinhardt@amd.com>

sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.

7515:82453f1b46c5 09-Aug-2010 Nathan Binkert <nate@binkert.org>

None, not none

7489:26cd0ad262d0 06-Jul-2010 Steve Reinhardt <steve.reinhardt@amd.com>

util: add a script for testing checkpointing
See comments in util/checkpoint-tester.py for details.

7416:e1a7a9f33a00 02-Jun-2010 Ali Saidi <Ali.Saidi@ARM.com>

ARM: fix sizes of structs for ARM Linux

7069:edde97a6ea7c 19-Apr-2010 Nathan Binkert <nate@binkert.org>

config: fix assertion for x86 in FSConfig.py

7032:9f938aea1942 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Reorganized Ruby topology and protocol files

7031:3b9335a18b4c 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

added sparse memory support to hammer

7027:46b02e79bf2c 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Adds configurable bit selection for numa mapping

7025:9adf5b0ccc79 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby support for sparse memory

The patch includes direct support for the MI example protocol.

7018:1c6d209888d7 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: removed ruby.config from configs/example

7015:6c91d41dfc12 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Python config files now sets a unique id for each sequencer

7014:441317194b08 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: fixed how ruby_fs creates phsyical memory

Now ruby_fs creates physical memory of the right size.

7011:8b38d35e8ffc 22-Mar-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added a mesh network with directories at the corners

The patch creates a specific mesh network where directories are at the corners.
The patch is a good example of how to create an arbitrary network, similar to
the old file specified network, while leveraging scripts and loops when
possible.

6995:f2b4d8bea5d3 27-Feb-2010 Gabe Black <gblack@eecs.umich.edu>

Config: Fix fs.py's call to CacheConfig.config_cache.

6981:aba5f7216636 25-Feb-2010 Lisa Hsu <Lisa.Hsu@amd.com>

configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.

6978:ab05e20dc4a7 23-Feb-2010 Lisa Hsu <Lisa.Hsu@amd.com>

cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).

6924:bb6be90ec74b 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: ruby_se.py updated to new config system

6923:1a46c5d58ede 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed if else statement in create_system

Based on Steve's suggestion, the ugly if-elif statement and multiple protocol
module import calls are removed and replaced with exec statements using the
protocol string.

6919:dd45a54732aa 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: memtest-ruby updated to the new config system

6918:9b57f0108bc8 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted Garnet to M5 configuration


common/Options.py
ruby/Ruby.py
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/NetworkHeader.hh
/gem5/src/mem/ruby/network/garnet/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
/gem5/src/mem/ruby/network/garnet/flexible-pipeline/SConscript
/gem5/src/mem/ruby/system/System.cc
6916:a421f60f0e87 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added a mesh topology

6915:13e4df0df905 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: MESI_CMP_directory updated to the new config system

6911:1fdbff869ff4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: MOESI_CMP_directory updated to the new config system

6908:0e1d7624e641 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: MOESI_CMP_token updates to use the new config system

6906:35da51c349e2 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: MI_example updates to use the new config system

6905:12390db623b4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Memory size consistency check

Ruby's memory is now sized according to the size of M5 physical memory.

6903:27f47cf65ab7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: convert to M5 MemorySize
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.

6899:f8057af86bf7 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: added the GEMS ruby tester

6897:cfeb3d9563dd 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: cleaned up ruby profilers
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.

6896:649e40aad897 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Removed RubySystem::getNumberOfSequencers
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable

6893:9cdf9b65d946 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: FS support using the new configuration system

6892:6a2db6c8a9b1 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester). This
code works for memory tester, but have not tested fs mode.

6889:323cd43a3c46 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system. Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector. Eventually this support should be removed from the main
profiler and go into a separate object. Each memory controller should have
a pointer to that new mem_cntrl profile object.

6888:de8e755aca4f 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Converted MOESI_hammer dma cntrl to new config system

6887:b10cae7bacf4 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added the cache profiler to the new config system

6883:f57e272cf8a1 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.

6882:898047a3672c 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.

6881:5a61a8a9009a 29-Jan-2010 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: connects sm queues to the network

6880:a9e3c07205a8 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.

6879:c07cf29b5a33 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Add support for generating topologies in Python.

6876:a658c315512c 29-Jan-2010 Steve Reinhardt <steve.reinhardt@amd.com>

ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.


example/memtest-ruby.py
/gem5/src/mem/SConscript
/gem5/src/mem/ruby/SConscript
/gem5/src/mem/ruby/common/Debug.cc
/gem5/src/mem/ruby/common/Debug.hh
/gem5/src/mem/ruby/common/Debug.py
/gem5/src/mem/ruby/common/SConscript
/gem5/src/mem/ruby/config/MESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MI_example-homogeneous.rb
/gem5/src/mem/ruby/config/MI_example.rb
/gem5/src/mem/ruby/config/MOESI_CMP_directory.rb
/gem5/src/mem/ruby/config/MOESI_CMP_token.rb
/gem5/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
/gem5/src/mem/ruby/config/MOESI_hammer.rb
/gem5/src/mem/ruby/config/SConscript
/gem5/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
/gem5/src/mem/ruby/config/assert.rb
/gem5/src/mem/ruby/config/cfg.rb
/gem5/src/mem/ruby/config/defaults.rb
/gem5/src/mem/ruby/config/libruby_cfg_test.cc
/gem5/src/mem/ruby/config/print_cfg.rb
/gem5/src/mem/ruby/config/util.rb
/gem5/src/mem/ruby/eventqueue/RubyEventQueue.cc
/gem5/src/mem/ruby/libruby.cc
/gem5/src/mem/ruby/network/Network.cc
/gem5/src/mem/ruby/network/Network.hh
/gem5/src/mem/ruby/network/Network.py
/gem5/src/mem/ruby/network/SConscript
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh
/gem5/src/mem/ruby/network/garnet-fixed-pipeline/SConscript
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh
/gem5/src/mem/ruby/network/garnet-flexible-pipeline/SConscript
/gem5/src/mem/ruby/network/orion/SConscript
/gem5/src/mem/ruby/network/simple/HierarchicalSwitchTopology.hh
/gem5/src/mem/ruby/network/simple/PtToPtTopology.hh
/gem5/src/mem/ruby/network/simple/SConscript
/gem5/src/mem/ruby/network/simple/SimpleNetwork.cc
/gem5/src/mem/ruby/network/simple/SimpleNetwork.hh
/gem5/src/mem/ruby/network/simple/SimpleNetwork.py
/gem5/src/mem/ruby/network/simple/Topology.cc
/gem5/src/mem/ruby/network/simple/Topology.hh
/gem5/src/mem/ruby/network/simple/Torus2DTopology.hh
/gem5/src/mem/ruby/profiler/Profiler.cc
/gem5/src/mem/ruby/profiler/Profiler.hh
/gem5/src/mem/ruby/profiler/Profiler.py
/gem5/src/mem/ruby/profiler/SConscript
/gem5/src/mem/ruby/recorder/SConscript
/gem5/src/mem/ruby/recorder/Tracer.cc
/gem5/src/mem/ruby/recorder/Tracer.hh
/gem5/src/mem/ruby/recorder/Tracer.py
/gem5/src/mem/ruby/slicc_interface/AbstractController.hh
/gem5/src/mem/ruby/slicc_interface/Controller.py
/gem5/src/mem/ruby/slicc_interface/SConscript
/gem5/src/mem/ruby/system/Cache.py
/gem5/src/mem/ruby/system/CacheMemory.cc
/gem5/src/mem/ruby/system/CacheMemory.hh
/gem5/src/mem/ruby/system/DMASequencer.cc
/gem5/src/mem/ruby/system/DMASequencer.hh
/gem5/src/mem/ruby/system/DirectoryMemory.cc
/gem5/src/mem/ruby/system/DirectoryMemory.hh
/gem5/src/mem/ruby/system/DirectoryMemory.py
/gem5/src/mem/ruby/system/MemoryControl.cc
/gem5/src/mem/ruby/system/MemoryControl.hh
/gem5/src/mem/ruby/system/MemoryControl.py
/gem5/src/mem/ruby/system/RubyPort.cc
/gem5/src/mem/ruby/system/RubyPort.hh
/gem5/src/mem/ruby/system/RubySystem.py
/gem5/src/mem/ruby/system/SConscript
/gem5/src/mem/ruby/system/Sequencer.cc
/gem5/src/mem/ruby/system/Sequencer.hh
/gem5/src/mem/ruby/system/Sequencer.py
/gem5/src/mem/ruby/system/System.cc
/gem5/src/mem/ruby/system/System.hh
6802:e649cb8af113 19-Dec-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Record the memory mode when building an X86 system.

6796:daf49a57df75 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

m5: improvements to the ruby_fs.py file

6776:463aab78c057 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

m5: Added option to take a checkpoint at the end of simulation

6769:630a3d0b7eb7 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

m5: Moved profile option since Simulation depends on it.

6767:71b272bd988e 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.

6765:b5101309174d 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.

6760:12da457d6e5c 18-Nov-2009 Brad Beckmann <Brad.Beckmann@amd.com>

ruby: Ruby memtest python script.

6679:a1d8c53d92b8 16-Oct-2009 Brad Beckmann <Brad.Beckmann@amd.com>

removed libruby file reference from ruby_se.py

6654:4c84e771cca7 22-Sep-2009 Nathan Binkert <nate@binkert.org>

python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.


/gem5/SConstruct
common/Caches.py
common/FSConfig.py
common/Simulation.py
example/fs.py
example/memtest.py
example/ruby_se.py
example/se.py
splash2/cluster.py
splash2/run.py
/gem5/src/SConscript
/gem5/src/arch/mips/BISystem.py
/gem5/src/arch/mips/MipsCPU.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/x86/X86TLB.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/CheckerCPU.py
/gem5/src/cpu/inorder/InOrderCPU.py
/gem5/src/cpu/memtest/MemTest.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/ozone/OzoneCPU.py
/gem5/src/cpu/ozone/OzoneChecker.py
/gem5/src/cpu/ozone/SimpleOzoneCPU.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/dev/Uart.py
/gem5/src/mem/Bus.py
/gem5/src/python/SConscript
/gem5/src/python/m5/SimObject.py
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/environment.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/params.py
/gem5/src/python/m5/simulate.py
/gem5/src/python/m5/smartdict.py
/gem5/src/python/m5/ticks.py
/gem5/src/python/m5/trace.py
/gem5/src/python/m5/util/__init__.py
/gem5/src/python/m5/util/convert.py
/gem5/src/python/m5/util/jobfile.py
/gem5/src/python/m5/util/misc.py
/gem5/src/python/m5/util/smartdict.py
/gem5/src/sim/System.py
/gem5/tests/configs/inorder-timing.py
/gem5/tests/configs/o3-timing-mp-ruby.py
/gem5/tests/configs/o3-timing-mp.py
/gem5/tests/configs/o3-timing-ruby.py
/gem5/tests/configs/o3-timing.py
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-o3-dual.py
/gem5/tests/configs/tsunami-o3.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/configs/twosys-tsunami-simple-atomic.py
/gem5/tests/long/00.gzip/test.py
/gem5/tests/long/10.mcf/test.py
/gem5/tests/long/20.parser/test.py
/gem5/tests/long/30.eon/test.py
/gem5/tests/long/40.perlbmk/test.py
/gem5/tests/long/50.vortex/test.py
/gem5/tests/long/60.bzip2/test.py
/gem5/tests/long/70.twolf/test.py
6642:0b72f4f7c814 16-Sep-2009 Korey Sewell <ksewell@umich.edu>

inorder-configs: update se.py
fix bug with 'numThreads=len(workloads)' which was counting characters of command-line not counting threads as intended.
Update numThreads for inorder/o3 cases and default to 1 for all other cases.

6641:59f08019c39a 16-Sep-2009 Korey Sewell <ksewell@umich.edu>

configs: add maxinsts option on command line
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.

6636:8c68656b8564 15-Sep-2009 Steve Reinhardt <steve.reinhardt@amd.com>

Add an I/O cache to FS config even if there's just an "L2" cache.

6391:af82c0870667 26-Jul-2009 Korey Sewell <ksewell@umich.edu>

se-configs: edit se.py to account for non-O3CPU workloads

6387:70172be3f986 25-Jul-2009 Korey Sewell <ksewell@umich.edu>

o3-smt: enforce numThreads parameter for SMT SE mode

6174:7e5c7412ac89 05-May-2009 Korey Sewell <ksewell@umich.edu>

cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well

6165:2d26c346f1be 11-May-2009 Daniel Sanchez <sanchezd@stanford.edu>

ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t

6144:e330f7bc22ef 05-May-2009 Korey Sewell <ksewell@umich.edu>

cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well

6135:9327451a8e7a 26-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.

6122:9af6fb59752f 16-Jul-2008 Steve Reinhardt <Steve.Reinhardt@amd.com>

mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.

6107:52a5e1c63380 21-Apr-2009 Steve Reinhardt <steve.reinhardt@amd.com>

Minor tweaks for future Ruby compatibility.

6074:76c2b55fce6d 19-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Actually put the PCI INTA entry into the MP tables.

6072:2372a164604f 19-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Make E820 report nice, round (and correct) numbers.

6044:3b23e5fc76e4 19-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Automatically make the IO APIC in an N CPU system have id N+1.

6028:137a2b89eed4 15-Apr-2009 Steve Reinhardt <steve.reinhardt@amd.com>

configs: Allow M5_CPU2000 env var to set CPU2K binary path.
It would be nice to have a more comprehensive mechanism
but this is a big improvement over manually editing the script.

5918:c3d88393a1f3 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add IRQ4 to the Intel MP tables.

5869:acbe11bbfe68 10-Feb-2009 Korey Sewell <ksewell@umich.edu>

Configs: Add support for the InOrder CPU model

5847:02e0e93d1ba7 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Find the natural lpj for this configuration.

5845:c88856b98084 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add a root device to the kernel command line.

5843:a2c317cefcf8 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Configure the first PCI interrupt.

5841:08c65e29e57e 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Hook in a hard drive image.

5840:6481e40d21eb 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Take out the IDE noprobe kernel arguments.

5833:5a07c4e3249b 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Plug in an IDE controller.

5828:5975aa055dc8 01-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add some interrupt info to the intel MP tables.

5822:05ffa2c3c800 30-Jan-2009 Ali Saidi <saidi@eecs.umich.edu>

Errors: Print a URL with a hash of the format string to find more information about an error.

5819:f4a1bcc3b7bc 25-Jan-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Prevent Linux for probing for non-existant IDE controllers.

5644:2c54b5aa7769 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add entries for the IO APIC to the MP table.

5641:51b7b8cf8083 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add an Intel MP table to the simulation.

5638:dc073dc6358b 11-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Rename the PC device to Pc.

5615:1c4b9b1aa500 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Turn SMBios structures into simobjects.

5613:0d14611ee1bb 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System.

5543:3af77710f397 10-Sep-2008 Ali Saidi <saidi@eecs.umich.edu>

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs


common/Benchmarks.py
/gem5/src/arch/alpha/aout_machdep.h
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/floatregfile.hh
/gem5/src/arch/alpha/ipr.cc
/gem5/src/arch/alpha/ipr.hh
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/linux.cc
/gem5/src/arch/alpha/linux/linux.hh
/gem5/src/arch/alpha/miscregfile.hh
/gem5/src/arch/alpha/osfpal.cc
/gem5/src/arch/alpha/pagetable.hh
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/alpha/remote_gdb.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tlb.cc
/gem5/src/arch/alpha/tru64/process.cc
/gem5/src/arch/alpha/tru64/tru64.cc
/gem5/src/arch/alpha/tru64/tru64.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/isa_specific.hh
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/linux/linux.cc
/gem5/src/arch/sparc/linux/linux.hh
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/remote_gdb.cc
/gem5/src/arch/sparc/solaris/solaris.cc
/gem5/src/arch/sparc/solaris/solaris.hh
/gem5/src/arch/sparc/sparc_traits.hh
/gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
/gem5/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py
/gem5/src/arch/x86/isa/insts/general_purpose/semaphores.py
/gem5/src/arch/x86/isa/insts/general_purpose/system_calls.py
/gem5/src/arch/x86/linux/linux.hh
/gem5/src/arch/x86/remote_gdb.cc
/gem5/src/base/bitunion.hh
/gem5/src/base/crc.cc
/gem5/src/base/fast_alloc.cc
/gem5/src/base/fast_alloc.hh
/gem5/src/base/inifile.hh
/gem5/src/base/loader/aout_object.cc
/gem5/src/base/loader/coff_sym.h
/gem5/src/base/loader/coff_symconst.h
/gem5/src/base/loader/ecoff_object.cc
/gem5/src/base/loader/elf_object.cc
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.hh
/gem5/src/base/loader/symtab.hh
/gem5/src/base/remote_gdb.cc
/gem5/src/base/res_list.hh
/gem5/src/base/stats/flags.hh
/gem5/src/base/stats/mysql.cc
/gem5/src/base/time.hh
/gem5/src/base/trace.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/cpu/o3/alpha/dyn_inst.hh
/gem5/src/cpu/o3/mips/dyn_inst.hh
/gem5/src/cpu/o3/regfile.hh
/gem5/src/cpu/ozone/back_end.hh
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/inorder_back_end.hh
/gem5/src/cpu/ozone/lsq_unit_impl.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/dev/alpha/access.h
/gem5/src/dev/etherdump.cc
/gem5/src/dev/mips/access.h
/gem5/src/dev/ns_gige.hh
/gem5/src/dev/pcidev.cc
/gem5/src/dev/pcireg.h
/gem5/src/dev/sinicreg.hh
/gem5/src/kern/linux/linux.hh
/gem5/src/kern/operatingsystem.hh
/gem5/src/kern/solaris/solaris.hh
/gem5/src/kern/tru64/mbuf.hh
/gem5/src/kern/tru64/tru64.hh
/gem5/src/kern/tru64/tru64_syscalls.cc
/gem5/src/mem/cache/blk.hh
/gem5/src/mem/cache/builder.cc
/gem5/src/mem/cache/prefetch/stride.cc
/gem5/src/mem/cache/prefetch/stride.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/dram.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/SimObject.py
/gem5/src/sim/async.hh
/gem5/src/sim/debug.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/insttracer.hh
/gem5/src/sim/process.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/serialize.hh
/gem5/src/sim/sim_events.hh
/gem5/src/sim/syscall_emul.cc
/gem5/src/sim/syscall_emul.hh
/gem5/util/m5/m5op_alpha.S
/gem5/util/m5/m5ops.h
/gem5/util/term/term.c
5514:9a903bf83a33 23-Jul-2008 Michael Adler <Michael.Adler@intel.com>

process: separate stderr from stdout
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout. The
new default maintains stdout and stderr going to the host. Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.

5478:ca055528a3b3 17-Jun-2008 Nathan Binkert <nate@binkert.org>

Rename SimConsole to Terminal since it makes more sense

5457:08bd3709d482 13-Jun-2008 Ali Saidi <saidi@eecs.umich.edu>

Scripts: Check for the appropriate build type as soon as possible.

5450:25e395a87745 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the e820 table manually or automatically configurable from python.

5416:26aa7cf1be28 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Force the kernel to use a certain loops per jiffy instead of calculating it.

5412:771996f1d68e 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the amount of system memory match the hardcoded e820 info.

5411:d517a2f5f2a6 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the regular console use the serial port as well.

5389:215d8a8c97df 25-Mar-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Change the Opteron platform to be the PC platform.

5378:7c058e69f257 15-Mar-2008 Ali Saidi <saidi@eecs.umich.edu>

Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist

5371:dce5a8655829 29-Feb-2008 Lisa Hsu <hsul@eecs.umich.edu>

Error out if -s is used without --caches (instead of saying you must specify a
CPU).

5370:b16ec4d7e77c 29-Feb-2008 Ali Saidi <saidi@eecs.umich.edu>

Configs: Make sure options don't conflict

5369:9358355117b0 28-Feb-2008 Ali Saidi <saidi@eecs.umich.edu>

Configs: Fix some bugs we introduced in the simpoints code

5361:e379019a1abd 27-Feb-2008 Rick Strong <rstrong@cs.ucsd.edu>

Configs: Make using Simpoints easier with some config files that support them easily

5357:eecb5fd0be62 26-Feb-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Get PCI config space to work, and adjust address space prefix numbering scheme.

5353:487d6f3291d7 22-Feb-2008 Vilas Sridharan <vilas.sridharan@gmail.com>

add instruction count fast forwaing and max instruction options

5347:f15b21a5bd2e 14-Feb-2008 Ali Saidi <saidi@eecs.umich.edu>

Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.

5330:a1db38b0d8e8 21-Jan-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Use the existing boot_osflags instead of duplicating it.

5323:75f7e6366a41 12-Jan-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the IO ports work using extra physical address lines. Add a serial port.

5311:9ed42a2315ae 18-Dec-2007 Ali Saidi <saidi@eecs.umich.edu>

Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.

5299:e61b9f2a9732 02-Dec-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Move startup code to the system object to initialize a Linux system.

5266:cd03d3753a8d 16-Nov-2007 Korey Sewell <ksewell@umich.edu>

Accidently kept hardcoded memory value in merge. Remove that and now ALPHA_FS quick regressions pass

5263:e059fb430ef3 16-Nov-2007 Korey Sewell <ksewell@umich.edu>

compile-time fix for setMipsOptions function

5256:723d4c11ac26 15-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Configs: Fix for benchmarks that don't use getopt.

5255:79825caee5fd 15-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Config: Fix some errors in the splash2 config file.

5254:c555f8b07345 15-Nov-2007 Korey Sewell <ksewell@umich.edu>

fix MIPS headers

5253:0ecd2477b9f3 15-Nov-2007 Korey Sewell <ksewell@umich.edu>

add setMipsOptions function for MIPS usage

5222:bb733a878f85 13-Nov-2007 Korey Sewell <ksewell@umich.edu>

Add in files from merge-bare-iron, get them compiling in FS and SE mode


/gem5/build_opts/MIPS_FS
common/FSConfig.py
example/fs.py
/gem5/src/arch/alpha/regfile.hh
/gem5/src/arch/isa_parser.py
/gem5/src/arch/mips/BISystem.py
/gem5/src/arch/mips/MipsCPU.py
/gem5/src/arch/mips/MipsSystem.py
/gem5/src/arch/mips/MipsTLB.py
/gem5/src/arch/mips/SConscript
/gem5/src/arch/mips/SConsopts
/gem5/src/arch/mips/bare_iron/system.cc
/gem5/src/arch/mips/bare_iron/system.hh
/gem5/src/arch/mips/constants.hh
/gem5/src/arch/mips/dsp.cc
/gem5/src/arch/mips/dsp.hh
/gem5/src/arch/mips/dt_constants.hh
/gem5/src/arch/mips/faults.cc
/gem5/src/arch/mips/faults.hh
/gem5/src/arch/mips/idle_event.cc
/gem5/src/arch/mips/idle_event.hh
/gem5/src/arch/mips/interrupts.cc
/gem5/src/arch/mips/interrupts.hh
/gem5/src/arch/mips/isa/base.isa
/gem5/src/arch/mips/isa/bitfields.isa
/gem5/src/arch/mips/isa/decoder.isa
/gem5/src/arch/mips/isa/formats/basic.isa
/gem5/src/arch/mips/isa/formats/branch.isa
/gem5/src/arch/mips/isa/formats/control.isa
/gem5/src/arch/mips/isa/formats/dsp.isa
/gem5/src/arch/mips/isa/formats/formats.isa
/gem5/src/arch/mips/isa/formats/fp.isa
/gem5/src/arch/mips/isa/formats/int.isa
/gem5/src/arch/mips/isa/formats/mem.isa
/gem5/src/arch/mips/isa/formats/mt.isa
/gem5/src/arch/mips/isa/formats/noop.isa
/gem5/src/arch/mips/isa/formats/tlbop.isa
/gem5/src/arch/mips/isa/formats/trap.isa
/gem5/src/arch/mips/isa/formats/unimp.isa
/gem5/src/arch/mips/isa/formats/unknown.isa
/gem5/src/arch/mips/isa/formats/util.isa
/gem5/src/arch/mips/isa/includes.isa
/gem5/src/arch/mips/isa/main.isa
/gem5/src/arch/mips/isa/operands.isa
/gem5/src/arch/mips/isa_traits.hh
/gem5/src/arch/mips/kernel_stats.hh
/gem5/src/arch/mips/linux/aligned.hh
/gem5/src/arch/mips/linux/hwrpb.hh
/gem5/src/arch/mips/linux/linux.cc
/gem5/src/arch/mips/linux/linux.hh
/gem5/src/arch/mips/linux/process.cc
/gem5/src/arch/mips/linux/process.hh
/gem5/src/arch/mips/linux/system.cc
/gem5/src/arch/mips/linux/system.hh
/gem5/src/arch/mips/linux/thread_info.hh
/gem5/src/arch/mips/linux/threadinfo.hh
/gem5/src/arch/mips/locked_mem.hh
/gem5/src/arch/mips/mips_core_specific.cc
/gem5/src/arch/mips/mips_core_specific.hh
/gem5/src/arch/mips/mmaped_ipr.hh
/gem5/src/arch/mips/mt.hh
/gem5/src/arch/mips/mt_constants.hh
/gem5/src/arch/mips/pagetable.cc
/gem5/src/arch/mips/pagetable.hh
/gem5/src/arch/mips/pra_constants.hh
/gem5/src/arch/mips/predecoder.hh
/gem5/src/arch/mips/process.cc
/gem5/src/arch/mips/process.hh
/gem5/src/arch/mips/regfile.cc
/gem5/src/arch/mips/regfile.hh
/gem5/src/arch/mips/regfile/float_regfile.cc
/gem5/src/arch/mips/regfile/float_regfile.hh
/gem5/src/arch/mips/regfile/int_regfile.cc
/gem5/src/arch/mips/regfile/int_regfile.hh
/gem5/src/arch/mips/regfile/misc_regfile.cc
/gem5/src/arch/mips/regfile/misc_regfile.hh
/gem5/src/arch/mips/regfile/regfile.cc
/gem5/src/arch/mips/regfile/regfile.hh
/gem5/src/arch/mips/remote_gdb.hh
/gem5/src/arch/mips/stacktrace.cc
/gem5/src/arch/mips/stacktrace.hh
/gem5/src/arch/mips/syscallreturn.hh
/gem5/src/arch/mips/system.cc
/gem5/src/arch/mips/system.hh
/gem5/src/arch/mips/tlb.cc
/gem5/src/arch/mips/tlb.hh
/gem5/src/arch/mips/types.hh
/gem5/src/arch/mips/utility.cc
/gem5/src/arch/mips/utility.hh
/gem5/src/arch/mips/vtophys.cc
/gem5/src/arch/mips/vtophys.hh
/gem5/src/base/SConscript
/gem5/src/base/loader/hex_file.cc
/gem5/src/base/loader/hex_file.cc~
/gem5/src/base/loader/hex_file.hh
/gem5/src/base/loader/object_file.cc
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/base.hh
/gem5/src/cpu/o3/thread_context.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple/base.hh
/gem5/src/cpu/simple_thread.hh
/gem5/src/cpu/static_inst.hh
/gem5/src/cpu/thread_context.hh
/gem5/src/dev/mips/Malta.py
/gem5/src/dev/mips/MipsConsole.py
/gem5/src/dev/mips/SConscript
/gem5/src/dev/mips/access.h
/gem5/src/dev/mips/console
/gem5/src/dev/mips/console.cc
/gem5/src/dev/mips/console.hh
/gem5/src/dev/mips/malta.cc
/gem5/src/dev/mips/malta.hh
/gem5/src/dev/mips/malta_cchip.cc
/gem5/src/dev/mips/malta_cchip.hh
/gem5/src/dev/mips/malta_io.cc
/gem5/src/dev/mips/malta_io.hh
/gem5/src/dev/mips/malta_pchip.cc
/gem5/src/dev/mips/malta_pchip.hh
/gem5/src/dev/mips/maltareg.h
/gem5/src/mem/physical.cc
/gem5/src/mem/request.hh
/gem5/src/sim/system.cc
5211:f7412cfae319 03-Nov-2007 Ali Saidi <saidi@eecs.umich.edu>

Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if that isn't set use cwd.

5185:d970c1ec39c9 25-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Checkpoints: Change Simulation.py to not go crazy if the simulation ends before the number of checkpoints requested are created.

5142:73aa4932b65b 08-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Configuration: Move iocache outside of processors loop so it works for MP systems

5133:a88763dd4a84 07-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Adjust the config scripts for x86 fs.

5073:1916291dcfda 12-Sep-2007 Ali Saidi <saidi@eecs.umich.edu>

Checkpointing: Fix directory regex

5072:ff0e3c84a1de 12-Sep-2007 Ali Saidi <saidi@eecs.umich.edu>

Checkpointing: Force drain/resume when switching a CPU

5056:11789c986e14 05-Sep-2007 Ali Saidi <saidi@eecs.umich.edu>

Configuration: Fix example script to only create one L2 if --l2cache and -nX are given as parameters.

Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de]

4982:723f5ce7f7b0 16-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

PCI: Move PCI Configuration data into devices now that we can inherit parameters.

4981:33fabf3473a5 16-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

Devices: Make EtherInts connect in the same way memory ports currently do.

4972:ee5b7df7f436 12-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

Regression: fix configuration for SPARC_FS

4968:f1c856d8c460 08-Aug-2007 Vincentius Robby <acolyte@umich.edu>

Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.

4965:ad0e792a5c78 10-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

4895:d36959284fbc 15-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Fix up a bunch of multilevel coherence issues.
Atomic mode seems to work. Timing is closer but not there yet.

4893:3439144e474a 15-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Fix problem with unset max_loads in memtest.
Also make default 0, and make that mean run forever.

4892:298bc09b72fa 15-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Punt on old -n/-c memtest args.
Also added comments to document treespec format.

4891:02babad9bfce 15-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

Add --force-bus option to memtest.py.

4890:5fbfbcd22796 15-Jul-2007 Steve Reinhardt <stever@eecs.umich.edu>

New tree-based algorithm for creating more complex cache hierarchies.

4876:a18cedc19da5 30-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Get rid of remaining traces of obsolete CoherenceProtocol object.

4847:41126ac89de7 01-Aug-2007 Gabe Black <gblack@eecs.umich.edu>

Fix how the "cmd" parameter is set in se.py and remove hack in x86 process initialization code.

4837:4e5c7f774548 01-Aug-2007 Ali Saidi <saidi@eecs.umich.edu>

Configuration: Update the drive systems kernel as well as the testsys kernel with cmd line option.

4672:cc97e595e07d 27-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Get rid of coherence protocol object.

4628:17b3ce796176 21-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Getting closer...

configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.

4627:2766d5cfbd9d 17-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2

configs/example/memtest.py:
Hand merge redundant changes.

4626:ed8aacb19c03 17-Jun-2007 Steve Reinhardt <stever@eecs.umich.edu>

More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.


example/memtest.py
/gem5/src/cpu/memtest/memtest.cc
/gem5/src/cpu/memtest/memtest.hh
/gem5/src/mem/bridge.cc
/gem5/src/mem/bus.cc
/gem5/src/mem/bus.hh
/gem5/src/mem/cache/base_cache.cc
/gem5/src/mem/cache/base_cache.hh
/gem5/src/mem/cache/cache.cc
/gem5/src/mem/cache/cache.hh
/gem5/src/mem/cache/cache_blk.hh
/gem5/src/mem/cache/cache_builder.cc
/gem5/src/mem/cache/cache_impl.hh
/gem5/src/mem/cache/coherence/coherence_protocol.cc
/gem5/src/mem/cache/coherence/coherence_protocol.hh
/gem5/src/mem/cache/coherence/simple_coherence.hh
/gem5/src/mem/cache/miss/SConscript
/gem5/src/mem/cache/miss/blocking_buffer.cc
/gem5/src/mem/cache/miss/blocking_buffer.hh
/gem5/src/mem/cache/miss/miss_buffer.cc
/gem5/src/mem/cache/miss/miss_buffer.hh
/gem5/src/mem/cache/miss/miss_queue.cc
/gem5/src/mem/cache/miss/miss_queue.hh
/gem5/src/mem/cache/miss/mshr.cc
/gem5/src/mem/cache/miss/mshr.hh
/gem5/src/mem/cache/miss/mshr_queue.cc
/gem5/src/mem/cache/miss/mshr_queue.hh
/gem5/src/mem/cache/prefetch/base_prefetcher.cc
/gem5/src/mem/cache/tags/fa_lru.cc
/gem5/src/mem/cache/tags/fa_lru.hh
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/iic.hh
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/lru.hh
/gem5/src/mem/cache/tags/split.cc
/gem5/src/mem/cache/tags/split.hh
/gem5/src/mem/cache/tags/split_lifo.cc
/gem5/src/mem/cache/tags/split_lifo.hh
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/cache/tags/split_lru.hh
/gem5/src/mem/packet.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/physical.cc
/gem5/src/mem/physical.hh
/gem5/src/mem/tport.cc
4555:7db37af44eb6 10-Jun-2007 Nathan Binkert <binkertn@umich.edu>

the cmd argument is supposed to be an array of parameters, not one string

4549:42b30b2529e1 10-Jun-2007 Nathan Binkert <binkertn@umich.edu>

More realistic parameters

4520:c118873326c7 04-Jun-2007 Ali Saidi <saidi@eecs.umich.edu>

fix SPARC....

configs/common/FSConfig.py:
fix SPARC

4486:aaeb03a8a6e1 27-May-2007 Nathan Binkert <binkertn@umich.edu>

Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.


common/FSConfig.py
/gem5/src/arch/alpha/AlphaSystem.py
/gem5/src/arch/alpha/AlphaTLB.py
/gem5/src/arch/alpha/SConscript
/gem5/src/arch/sparc/SConscript
/gem5/src/arch/sparc/SparcSystem.py
/gem5/src/arch/sparc/SparcTLB.py
/gem5/src/cpu/BaseCPU.py
/gem5/src/cpu/FuncUnit.py
/gem5/src/cpu/IntrControl.py
/gem5/src/cpu/SConscript
/gem5/src/cpu/memtest/MemTest.py
/gem5/src/cpu/memtest/SConscript
/gem5/src/cpu/o3/FUPool.py
/gem5/src/cpu/o3/FuncUnitConfig.py
/gem5/src/cpu/o3/O3CPU.py
/gem5/src/cpu/o3/O3Checker.py
/gem5/src/cpu/o3/SConscript
/gem5/src/cpu/ozone/OzoneCPU.py
/gem5/src/cpu/ozone/OzoneChecker.py
/gem5/src/cpu/ozone/SConscript
/gem5/src/cpu/ozone/SimpleOzoneCPU.py
/gem5/src/cpu/simple/AtomicSimpleCPU.py
/gem5/src/cpu/simple/SConscript
/gem5/src/cpu/simple/TimingSimpleCPU.py
/gem5/src/dev/BadDevice.py
/gem5/src/dev/Device.py
/gem5/src/dev/DiskImage.py
/gem5/src/dev/Ethernet.py
/gem5/src/dev/Ide.py
/gem5/src/dev/Pci.py
/gem5/src/dev/Platform.py
/gem5/src/dev/SConscript
/gem5/src/dev/SimConsole.py
/gem5/src/dev/SimpleDisk.py
/gem5/src/dev/Uart.py
/gem5/src/dev/alpha/AlphaConsole.py
/gem5/src/dev/alpha/SConscript
/gem5/src/dev/alpha/Tsunami.py
/gem5/src/dev/sparc/SConscript
/gem5/src/dev/sparc/T1000.py
/gem5/src/mem/Bridge.py
/gem5/src/mem/Bus.py
/gem5/src/mem/MemObject.py
/gem5/src/mem/PhysicalMemory.py
/gem5/src/mem/SConscript
/gem5/src/mem/cache/BaseCache.py
/gem5/src/mem/cache/SConscript
/gem5/src/mem/cache/coherence/CoherenceProtocol.py
/gem5/src/mem/cache/coherence/SConscript
/gem5/src/mem/cache/tags/Repl.py
/gem5/src/mem/cache/tags/SConscript
/gem5/src/python/SConscript
/gem5/src/python/m5/objects/AlphaConsole.py
/gem5/src/python/m5/objects/AlphaTLB.py
/gem5/src/python/m5/objects/BadDevice.py
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/BaseCache.py
/gem5/src/python/m5/objects/Bridge.py
/gem5/src/python/m5/objects/Bus.py
/gem5/src/python/m5/objects/CoherenceProtocol.py
/gem5/src/python/m5/objects/Device.py
/gem5/src/python/m5/objects/DiskImage.py
/gem5/src/python/m5/objects/Ethernet.py
/gem5/src/python/m5/objects/FUPool.py
/gem5/src/python/m5/objects/FuncUnit.py
/gem5/src/python/m5/objects/FuncUnitConfig.py
/gem5/src/python/m5/objects/Ide.py
/gem5/src/python/m5/objects/IntrControl.py
/gem5/src/python/m5/objects/MemObject.py
/gem5/src/python/m5/objects/MemTest.py
/gem5/src/python/m5/objects/O3CPU.py
/gem5/src/python/m5/objects/OzoneCPU.py
/gem5/src/python/m5/objects/Pci.py
/gem5/src/python/m5/objects/PhysicalMemory.py
/gem5/src/python/m5/objects/Platform.py
/gem5/src/python/m5/objects/Process.py
/gem5/src/python/m5/objects/Repl.py
/gem5/src/python/m5/objects/Root.py
/gem5/src/python/m5/objects/SimConsole.py
/gem5/src/python/m5/objects/SimpleDisk.py
/gem5/src/python/m5/objects/SimpleOzoneCPU.py
/gem5/src/python/m5/objects/SparcTLB.py
/gem5/src/python/m5/objects/System.py
/gem5/src/python/m5/objects/T1000.py
/gem5/src/python/m5/objects/Tsunami.py
/gem5/src/python/m5/objects/Uart.py
/gem5/src/sim/Process.py
/gem5/src/sim/Root.py
/gem5/src/sim/SConscript
/gem5/src/sim/System.py
4476:19ae7f38237e 22-May-2007 Steve Reinhardt <stever@eecs.umich.edu>

memtest.py:
Make clocks more reasonable.
Fix bug in sense of options.timing flag.

configs/example/memtest.py:
Fix bug in sense of options.timing flag.
configs/example/memtest.py:
Make clocks more reasonable.

4467:cb5715e021ca 19-May-2007 Steve Reinhardt <stever@eecs.umich.edu>

PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.

4455:18ff8ee46de8 15-May-2007 Ali Saidi <saidi@eecs.umich.edu>

add an l2 cache option to se example config

configs/common/Options.py:
configs/example/fs.py:
move l2 cache option to Options.py

4454:8125c4b9e306 15-May-2007 Ali Saidi <saidi@eecs.umich.edu>

hopefully the final hacky change to make the bus bridge work ok
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
hopefully the final hacky change to make the bus bridge work ok

4452:9dfce80039cd 14-May-2007 Ali Saidi <saidi@eecs.umich.edu>

couple more bug fixes for intel nic

src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
couple more bug fixes

4444:0648bdc8d1c9 10-May-2007 Ali Saidi <saidi@eecs.umich.edu>

remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs

4432:5e55857abb01 07-May-2007 Ali Saidi <saidi@eecs.umich.edu>

fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

4418:aaa5828991b3 30-Apr-2007 Ali Saidi <saidi@eecs.umich.edu>

add a udp stream benchmark and a udp loopback benchmark

4417:067ba4a38aa2 30-Apr-2007 Ali Saidi <saidi@eecs.umich.edu>

make ping actually end

4407:e11a784de928 26-Apr-2007 Kevin Lim <ktlim@umich.edu>

Fix mutex test script for latest disk image.

4403:824f7311059c 23-Apr-2007 Ron Dreslinski <rdreslin@umich.edu>

Fix the splash2 run script

4388:0bb518a13d66 20-Apr-2007 Lisa Hsu <hsul@eecs.umich.edu>

spec-surge-client.rcS:
fix script to reflect new benchmark directory sturcture

configs/boot/spec-surge-client.rcS:
fix script to reflect new benchmark directory sturcture

4271:13ea06ef646d 22-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Fix mcf benchmark object so it gets the arguments it expects.

4167:ce5d0f62f13b 06-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.


common/FSConfig.py
common/Simulation.py
example/fs.py
/gem5/src/base/annotate.cc
/gem5/src/base/misc.cc
/gem5/src/base/pollevent.cc
/gem5/src/base/pollevent.hh
/gem5/src/base/trace.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/pc_event.cc
/gem5/src/cpu/static_inst.cc
/gem5/src/dev/etherbus.cc
/gem5/src/dev/etherdump.cc
/gem5/src/dev/etherlink.cc
/gem5/src/dev/ide_disk.cc
/gem5/src/dev/pcidev.cc
/gem5/src/kern/tru64/tru64.hh
/gem5/src/mem/cache/cache_blk.hh
/gem5/src/mem/cache/miss/mshr.cc
/gem5/src/mem/cache/tags/iic.cc
/gem5/src/mem/cache/tags/lru.cc
/gem5/src/mem/cache/tags/split_lifo.cc
/gem5/src/mem/cache/tags/split_lru.cc
/gem5/src/mem/packet.hh
/gem5/src/mem/request.hh
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/convert.py
/gem5/src/python/m5/event.py
/gem5/src/python/m5/main.py
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/PhysicalMemory.py
/gem5/src/python/m5/objects/Root.py
/gem5/src/python/m5/params.py
/gem5/src/python/m5/ticks.py
/gem5/src/python/swig/core.i
/gem5/src/python/swig/event.i
/gem5/src/sim/builder.cc
/gem5/src/sim/core.cc
/gem5/src/sim/core.hh
/gem5/src/sim/eventq.cc
/gem5/src/sim/main.cc
/gem5/src/sim/root.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/tests/configs/t1000-simple-atomic.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
4132:a4ed11288493 05-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

4116:f6e3dc4655e9 02-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Keep around which input set was used for a benchmark, and make vortex work with SPARC.

4107:3ac1abf8e035 27-Feb-2007 Gabe Black <gblack@eecs.umich.edu>

Fix issue with twolf where the presence or absence of two files, smred.sav or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3"

4104:10b99ef0a7ff 03-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

Add Iob and remove the fake device

configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy

4103:785279436bdd 03-Mar-2007 Ali Saidi <saidi@eecs.umich.edu>

Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore


common/FSConfig.py
/gem5/src/arch/alpha/interrupts.hh
/gem5/src/arch/sparc/asi.cc
/gem5/src/arch/sparc/faults.cc
/gem5/src/arch/sparc/faults.hh
/gem5/src/arch/sparc/interrupts.hh
/gem5/src/arch/sparc/isa_traits.hh
/gem5/src/arch/sparc/miscregfile.cc
/gem5/src/arch/sparc/miscregfile.hh
/gem5/src/arch/sparc/regfile.cc
/gem5/src/arch/sparc/regfile.hh
/gem5/src/arch/sparc/tlb.cc
/gem5/src/arch/sparc/ua2005.cc
/gem5/src/base/bitfield.hh
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/intr_control.cc
/gem5/src/cpu/intr_control.hh
/gem5/src/dev/alpha/tsunami_cchip.cc
/gem5/src/dev/sparc/SConscript
/gem5/src/python/m5/objects/IntrControl.py
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
/gem5/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
4094:1950ef76ddf9 22-Feb-2007 Nathan Binkert <binkertn@umich.edu>

Get rid of the ConsoleListener SimObject and just fold the
relevant code directly into the SimConsole object. Now,
you can easily turn off the listen port by just specifying
0 as the port.

3999:ba54519a7a92 30-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

fix some checkpointing annoyances
-m works as you think it should
Ctrl-C actually ends the simulation now

3970:d54945bab95d 03-Jan-2007 Gabe Black <gblack@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem

3898:42a529d97cf2 09-Jan-2007 Ali Saidi <saidi@eecs.umich.edu>

add memory mapped disk device

configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript

3873:9c1773b9f603 23-Dec-2006 Nathan Binkert <binkertn@umich.edu>

Add options for setting the kernel to run and the
script to run

3823:1c8f87aa103e 06-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request

3819:8a9d3f3d3398 04-Dec-2006 Lisa Hsu <hsul@eecs.umich.edu>

automatically build sparc system or alpha system.

configs/example/fs.py:
make it an automatic system build for alpha vs. sparc.

3814:33bd4ec9d66a 04-Dec-2006 Ali Saidi <saidi@eecs.umich.edu>

More changes to get SPARC fs closer. Now at 1.2M cycles before difference

configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller

3812:eaa215123a26 30-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it

3751:b422ffec62c1 22-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it.

3745:70a265d01c87 20-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Add in rom/rams for the nvram, hypervisor description, and partition description.

3743:2061715f68d1 16-Nov-2006 Gabe Black <gblack@eecs.umich.edu>

Fixes for SPARC_FS

configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.

3690:28b3001a883d 30-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

netperf-maerts-client.rcS:
change /netperf/netperf to /netperf-bin/netperf
nat-netperf-maerts-client.rcS:
bad comment that went with the file - accidentally committed but probably doesn't matter, i ust eliminated an ivlb in the script.

configs/boot/nat-netperf-maerts-client.rcS:
replace netperf/netperf with netperf-bin/netperf
configs/boot/netperf-maerts-client.rcS:
change /netperf/netperf to /netperf-bin/netperf

3681:129a68314264 26-Nov-2006 Kevin Lim <ktlim@umich.edu>

Include check for making sure caches are enabled.

3671:c60eba24f33b 16-Nov-2006 Nathan Binkert <binkertn@umich.edu>

Implement a single config file to encompass all of the SPEC
CPU2000 stuff, and use it in all of the tests that currently
use SPEC

3668:bacb0a392e78 15-Nov-2006 Ron Dreslinski <rdreslin@umich.edu>

Add L2 cache option to fs.py --l2cache

3646:66853026ad52 13-Nov-2006 Ron Dreslinski <rdreslin@umich.edu>

Update splash2 config files

configs/splash2/run.py:
Fix MaxTick for splash configs
configs/splash2/cluster.py:
Add a config that allows clusters of CPU's to be attached to a single L1

3631:cebd6af96efd 09-Nov-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

3623:c37f82ace0fe 12-Nov-2006 Ron Dreslinski <rdreslin@umich.edu>

Update for maxtick in splash2/memtest configs

configs/example/memtest.py:
configs/splash2/run.py:
Update for maxtick

3584:8c3cdb2c001c 09-Nov-2006 Ali Saidi <saidi@eecs.umich.edu>

Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together

3514:b166ee5dce91 09-Nov-2006 Kevin Lim <ktlim@umich.edu>

Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.

configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

However the O3CPU must always use caches, so a check for that must still exist.

Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.

3511:8cb26619b6ec 08-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

simplify maxtick parsing in both the python and the c++.

configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc

3510:c529f0b16334 08-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

make rcS files read from the m5 source directory, not /dist.

3509:ff94a3eda992 08-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

change to os.path.join like nate wanted.

3481:14362d3b0756 01-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.

configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.

3480:c1ec938d2920 01-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache.

3478:b2372d54182c 01-Nov-2006 Lisa Hsu <hsul@eecs.umich.edu>

change name of 2nd switch_cpu so that ckpt recovery with multiple cpus doens't get confused.

3477:eaf445891a4e 31-Oct-2006 Kevin Lim <ktlim@umich.edu>

Fix up configs.

configs/common/Simulation.py:
Remove mem parameter.
configs/example/se.py:
Remove debug output that got included in my other push.

3476:0e26b5458236 31-Oct-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
Hand merge.

3449:97c98705ac4e 30-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

FSConfig.py:
Accidentally committed this last time

configs/common/FSConfig.py:
Accidentally committed this last time

3448:bb2632fa57dc 30-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

se.py, fs.py:
import Caches
Simulation.py:
Fix typo - L2Cache --> L1Cache

configs/common/Simulation.py:
Fix typo - L2Cache --> L1Cache
configs/example/fs.py:
configs/example/se.py:
import Caches

3447:258e3c319f6f 30-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

ensure that there is a "/" between the cptdir and the cpt.%d.

3445:5c5f90f5506c 30-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

decouple the switch option from the warmup period option - parsing was confused otherwise, oops.

3444:6abefa632e10 30-Oct-2006 Kevin Lim <ktlim@umich.edu>

Use some python os.path stuff to make it more flexible where we can execute this script from.

3410:ef75e2c78b2d 30-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

add some comments and make the warmup period in a switchover parameterizable.

configs/common/Options.py:
make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
add some comments and also make the warmup period an option.

3409:769707cf0664 27-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem

configs/example/fs.py:
configs/example/se.py:
hand merge

3402:db60546818d0 31-Oct-2006 Kevin Lim <ktlim@umich.edu>

Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.

configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.

3399:8206f6b9283e 26-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

configs/example/se.py:
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

3398:7f14cadf3afd 24-Oct-2006 Ali Saidi <saidi@eecs.umich.edu>

Fix fs.py. Lisa did you test this? Is there some wierd python version thing?

3395:49e674f2fb5d 27-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

factor out common run code from se.py and fs.py.

configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code

3394:0a6b4a7a6df6 23-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

warmup of 1B cpu cycles.

configs/example/fs.py:
configs/example/se.py:
warm up of 1B CPU cycles

3393:43e1a001a7ce 23-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem

3372:ccbe8a56f5b7 22-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add mutex test to Benchmarks.py.

3360:9a802e1085ec 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Add some default options, point it to the /dist version of the splash benchmarks

3358:f70480ec2642 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Clean up splash2 so it works in v2.0

configs/splash2/run.py:
Update the splash2 file

3355:f15cc71cdf09 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Give physical memory some latency to stress the system

3354:2ea739dd597c 20-Oct-2006 Ron Dreslinski <rdreslin@umich.edu>

Add a config file in the example with the memtester and some parser options.

3328:50b7be1f9ab6 19-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

First cut at LL/SC support in caches (atomic mode only).

configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).

3323:ca667530b8a0 23-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

make a lot of the same changes as to fs.py for checkpointing.

1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

3322:bccece90053b 23-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

changes regarding fs.py

1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.

configs/example/fs.py:
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

3314:1247da7b4d26 18-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add --caches option to add caches to server CPUs.

3312:dbaec4804adf 18-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Enable MP systems via cmd-line flag in fs.py.

configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).

3304:c5917aeb8e2f 17-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Rename 'Machine' to 'SysConfig'.
Clean up a little.

3231:ba2a74b94586 10-Oct-2006 Kevin Lim <ktlim@umich.edu>

Two minor fixes.

configs/common/SysPaths.py:
Undo accidental change.
src/SConscript:
Fix.

3230:e86a03911728 09-Oct-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.

3223:a2b6fa575c05 08-Oct-2006 Kevin Lim <ktlim@umich.edu>

Clean up configs.

configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.

3183:bd8f3870620f 09-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.

so you can restore by a command line like this:

m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3

configs/example/fs.py:
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.

3180:664fe611de8e 08-Oct-2006 Steve Reinhardt <stever@eecs.umich.edu>

Set cpu_id params (required by ll/sc code now).

3143:76c70c8bc5c8 06-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.

3133:ad45cbafebdd 05-Oct-2006 Lisa Hsu <hsul@eecs.umich.edu>

fix the argument to m5.simulate() on a checkpoint.

src/sim/stat_control.cc:
add curTick to reset stats printf.

3125:febd811bccc6 30-Sep-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zamp:./local/clean/o3-merge/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
Hand merge.


boot/micro_memlat.rcS
boot/micro_tlblat.rcS
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/freebsd/system.cc
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/arch/alpha/isa/mem.isa
/gem5/src/arch/alpha/isa_traits.hh
/gem5/src/arch/alpha/linux/system.cc
/gem5/src/arch/alpha/system.cc
/gem5/src/arch/alpha/tru64/system.cc
/gem5/src/cpu/base.cc
/gem5/src/cpu/base.hh
/gem5/src/cpu/base_dyn_inst.hh
/gem5/src/cpu/checker/cpu.hh
/gem5/src/cpu/checker/cpu_impl.hh
/gem5/src/cpu/o3/alpha/cpu_builder.cc
/gem5/src/cpu/o3/checker_builder.cc
/gem5/src/cpu/o3/commit_impl.hh
/gem5/src/cpu/o3/cpu.cc
/gem5/src/cpu/o3/fetch_impl.hh
/gem5/src/cpu/o3/iew.hh
/gem5/src/cpu/o3/iew_impl.hh
/gem5/src/cpu/o3/inst_queue.hh
/gem5/src/cpu/o3/inst_queue_impl.hh
/gem5/src/cpu/o3/lsq_impl.hh
/gem5/src/cpu/o3/lsq_unit.hh
/gem5/src/cpu/o3/lsq_unit_impl.hh
/gem5/src/cpu/o3/mem_dep_unit_impl.hh
/gem5/src/cpu/o3/rename.hh
/gem5/src/cpu/o3/rename_impl.hh
/gem5/src/cpu/o3/thread_state.hh
/gem5/src/cpu/o3/tournament_pred.cc
/gem5/src/cpu/o3/tournament_pred.hh
/gem5/src/cpu/ozone/checker_builder.cc
/gem5/src/cpu/ozone/cpu.hh
/gem5/src/cpu/ozone/cpu_builder.cc
/gem5/src/cpu/ozone/cpu_impl.hh
/gem5/src/cpu/ozone/front_end.hh
/gem5/src/cpu/ozone/front_end_impl.hh
/gem5/src/cpu/ozone/inorder_back_end_impl.hh
/gem5/src/cpu/ozone/inst_queue_impl.hh
/gem5/src/cpu/ozone/lw_back_end.hh
/gem5/src/cpu/ozone/lw_back_end_impl.hh
/gem5/src/cpu/ozone/lw_lsq.hh
/gem5/src/cpu/ozone/lw_lsq_impl.hh
/gem5/src/cpu/ozone/simple_params.hh
/gem5/src/cpu/ozone/thread_state.hh
/gem5/src/cpu/simple/base.cc
/gem5/src/cpu/simple_thread.cc
/gem5/src/cpu/thread_state.hh
/gem5/src/dev/ide_disk.hh
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/O3CPU.py
/gem5/src/python/m5/objects/OzoneCPU.py
/gem5/src/python/m5/objects/Root.py
/gem5/src/python/m5/objects/System.py
/gem5/src/sim/eventq.hh
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/pseudo_inst.hh
/gem5/src/sim/serialize.cc
/gem5/src/sim/stat_control.cc
/gem5/src/sim/stat_control.hh
/gem5/src/sim/system.hh
/gem5/util/m5/m5.c
/gem5/util/m5/m5op.S
3105:993f1abefd67 06-Sep-2006 Steve Reinhardt <stever@eecs.umich.edu>

Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.

3089:0ea2eb13c4de 11-Sep-2006 Ali Saidi <saidi@eecs.umich.edu>

add annotation code to m5

configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops

3088:d8a809416104 29-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add FULL_SYSTEM check to example/fs.py.

3087:e50b0686850d 29-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add missing cpu mem param to example/se.py.

configs/example/se.py:
Add missing cpu mem param.

3050:358a23f67bf6 21-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

fs.py:
Add temporary cpu.mem parameter settings.

configs/example/fs.py:
Add temporary cpu.mem parameter settings.

3046:fc3297be3869 20-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.

configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.

3032:dc687512802b 17-Aug-2006 Lisa Hsu <hsul@eecs.umich.edu>

make tree rcS files reflect what we've been actually using in /dist.

also, update all the rcS files so that they are in sync with the new linux-dist build system.

configs/boot/devtime.rcS:
configs/boot/iscsi-client.rcS:
configs/boot/iscsi-server.rcS:
configs/boot/micro_memlat.rcS:
configs/boot/micro_stream.rcS:
configs/boot/micro_tlblat.rcS:
configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-server.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/natbox-spec-surge.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-server.rcS:
configs/boot/netperf-stream-client.rcS:
configs/boot/netperf-stream-nt-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
configs/boot/nfs-server.rcS:
configs/boot/ping-client.rcS:
configs/boot/ping-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
make tree rcS files reflect what we've been actually using in /dist.

3025:00fe36086a14 16-Aug-2006 Ali Saidi <saidi@eecs.umich.edu>

add etherdump file option

3022:b3b379cb97ef 16-Aug-2006 Lisa Hsu <hsul@eecs.umich.edu>

Add in checkpointing in the frontend, so that when a checkpoint is called, the python handles it, and the simulation continues. Also, make it so that the cycle number is part of the cpt dir name, so that multiple checkpoints do not overwrite each other.

3005:ceb86e85d62d 16-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

Finish test clean-up & reorg.

configs/common/FSConfig.py:
Add default Machine() param
configs/example/fs.py:
configs/example/se.py:
make it work again
src/python/m5/objects/BaseCPU.py:
Make mem PhysicalMemory so that a Parent.any proxy works well
src/sim/process.cc:
Increase default stack size so we don't get an
'increasing stack' message on 'hello world'
tests/SConscript:
Add full list of current configs.
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
don't need SEConfig anymore
tests/quick/00.hello/test.py:
tests/quick/20.eio-short/test.py:
fix
tests/run.py:
move configs to separate dir


common/FSConfig.py
example/fs.py
example/se.py
test/fs.py
test/test.py
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/sim/process.cc
/gem5/tests/SConscript
/gem5/tests/configs/simple-atomic.py
/gem5/tests/configs/simple-timing.py
/gem5/tests/configs/tsunami-simple-atomic-dual.py
/gem5/tests/configs/tsunami-simple-atomic.py
/gem5/tests/configs/tsunami-simple-timing-dual.py
/gem5/tests/configs/tsunami-simple-timing.py
/gem5/tests/linux-boot/ref/alpha/atomic/config.ini
/gem5/tests/linux-boot/ref/alpha/atomic/config.out
/gem5/tests/linux-boot/ref/alpha/atomic/console.system.sim_console
/gem5/tests/linux-boot/ref/alpha/atomic/m5stats.txt
/gem5/tests/linux-boot/ref/alpha/atomic/stderr
/gem5/tests/linux-boot/ref/alpha/atomic/stdout
/gem5/tests/linux-mpboot/ref/alpha/atomic/config.ini
/gem5/tests/linux-mpboot/ref/alpha/atomic/config.out
/gem5/tests/linux-mpboot/ref/alpha/atomic/console.system.sim_console
/gem5/tests/linux-mpboot/ref/alpha/atomic/m5stats.txt
/gem5/tests/linux-mpboot/ref/alpha/atomic/stderr
/gem5/tests/linux-mpboot/ref/alpha/atomic/stdout
/gem5/tests/linux-mpboot/ref/alpha/timing/config.ini
/gem5/tests/linux-mpboot/ref/alpha/timing/config.out
/gem5/tests/linux-mpboot/ref/alpha/timing/console.system.sim_console
/gem5/tests/linux-mpboot/ref/alpha/timing/m5stats.txt
/gem5/tests/linux-mpboot/ref/alpha/timing/stderr
/gem5/tests/linux-mpboot/ref/alpha/timing/stdout
/gem5/tests/quick/00.hello/test.py
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
/gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
/gem5/tests/quick/10.linux-boot/test.py
/gem5/tests/quick/20.eio-short/test.py
/gem5/tests/run.py
/gem5/tests/simple-atomic.py
/gem5/tests/simple-timing.py
/gem5/tests/test-progs/hello/bin/mips/linux/hello
/gem5/tests/test-progs/hello/bin/mips/linux/hello_mips
/gem5/tests/test-progs/hello/bin/sparc/bin
/gem5/tests/test-progs/hello/bin/sparc/linux/hello
2998:1d5ea4e433f5 16-Aug-2006 Steve Reinhardt <stever@eecs.umich.edu>

More restructuring of regression tests.
Moving work back to zizzer...

configs/common/FSConfig.py:
configs/test/fs.py:
Move CPU connections out of makeLinuxAlphaSystem()
src/python/m5/objects/BaseCPU.py:
Create default TLBs in full system.
Move utility cache functions here.
src/python/m5/objects/O3CPU.py:
Add _mem_ports
tests/run.py:
Add binpath()
Change maxtick default to 'forever'
tests/simple-atomic.py:
Use connectmemPorts()
tests/simple-timing.py:
Fix up.


common/FSConfig.py
test/fs.py
test/hello
test/hello_mips
test/sparc_tests/hello_sparc
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/O3CPU.py
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr
/gem5/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
/gem5/tests/quick/00.hello/test.py
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.out
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr
/gem5/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
/gem5/tests/quick/20.eio-short/test.py
/gem5/tests/quick/eio1/ref/alpha/eio/detailed/config.ini
/gem5/tests/quick/eio1/ref/alpha/eio/detailed/config.out
/gem5/tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt
/gem5/tests/quick/eio1/ref/alpha/eio/detailed/stderr
/gem5/tests/quick/eio1/ref/alpha/eio/detailed/stdout
/gem5/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini
/gem5/tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out
/gem5/tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt
/gem5/tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr
/gem5/tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout
/gem5/tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini
/gem5/tests/quick/eio1/ref/alpha/eio/simple-timing/config.out
/gem5/tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt
/gem5/tests/quick/eio1/ref/alpha/eio/simple-timing/stderr
/gem5/tests/quick/eio1/ref/alpha/eio/simple-timing/stdout
/gem5/tests/quick/eio1/test.py
/gem5/tests/run.py
/gem5/tests/simple-atomic.py
/gem5/tests/simple-timing.py
/gem5/tests/test-progs/hello/bin/alpha/linux/hello
/gem5/tests/test-progs/hello/bin/mips/linux/hello_mips
/gem5/tests/test-progs/hello/bin/sparc/bin
2995:34553e4fd1ac 15-Aug-2006 Ali Saidi <saidi@eecs.umich.edu>

implement benchmark selection code

2969:d2f8f9a23082 27-Jul-2006 Kevin Lim <ktlim@umich.edu>

Clean up some more config stuff.

configs/common/FSConfig.py:
Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
Update for changed code.
src/python/m5/__init__.py:
Put makeList into m5.

2957:59556da364ae 23-Jul-2006 Kevin Lim <ktlim@umich.edu>

Fix up test.py

configs/test/test.py:
Fix up this config.

2955:7bdb681dfc55 22-Jul-2006 Gabe Black <gblack@eecs.umich.edu>

Reorganized SPARC binaries

2953:10e7700b27f6 22-Jul-2006 Kevin Lim <ktlim@umich.edu>

Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.

SConstruct:
Make test CPUs option non-sticky.
configs/common/FSConfig.py:
Be sure to set the memory mode.
configs/test/fs.py:
Wrong string.
tests/SConscript:
Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
Update output.

2952:b82b533b5f64 21-Jul-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
Hand merge.

2948:ae26cf37957c 20-Jul-2006 Ali Saidi <saidi@eecs.umich.edu>

Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz

configs/test/fs.py:
Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Enforce the timing cpu ticking at it's clock rate

2934:0b091d7d00f0 21-Jul-2006 Kevin Lim <ktlim@umich.edu>

Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.

configs/test/fs.py:
Pull out a lot of common code and put it into configs/common/FSConfig.py.

2931:871cb78cd6fa 21-Jul-2006 Kevin Lim <ktlim@umich.edu>

Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.

2925:7664c14086d1 19-Jul-2006 Kevin Lim <ktlim@umich.edu>

Update configs.

configs/test/test.py:
Update for changes to SEConfig.

2923:db8a876258df 14-Jul-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/fs.py:
configs/test/test.py:
SCCS merged

2920:73080b4a8cbb 12-Jul-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

configs/test/test.py:
Hand merge.

2917:4280efcc2967 12-Jul-2006 Kevin Lim <ktlim@umich.edu>

Initial try of consolidating configuration files so they can be shared more easily, especially across regression tests and simple examples.

configs/test/fs.py:
Pull a lot of the default options out of the config file now that they are in the Python objects themselves. Also merge this file with the single_fs.py, allowing one file to be used for both. Previously they differed only by the system they instantiated.
configs/test/test.py:
Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.

2902:695d4683916e 13-Jul-2006 Ali Saidi <saidi@eecs.umich.edu>

add system.mem_mode = ['timing', 'atomic']
update scripts acordingly

configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay

2889:9e367e03d656 10-Jul-2006 Nathan Binkert <binkertn@umich.edu>

Migrate most of main() and and all option parsing to python

configs/test/fs.py:
configs/test/test.py:
update for the new way that m5 deals with options
src/python/SConscript:
Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
python stuff.
src/python/m5/__init__.py:
redo the way options work.
Move them all to main.py
src/sim/main.cc:
Migrate more functionality for main() into python.
Namely option parsing
src/python/m5/attrdict.py:
A dictionary object that overrides attribute access to
do item access.
src/python/m5/main.py:
The new location for M5's option parsing, and the main()
routine to set up the simulation.

2882:811796e6dfeb 10-Jul-2006 Ron Dreslinski <rdreslin@umich.edu>

Update FS configs to use cpu connectors for ports

2856:89691405ec9c 07-Jul-2006 Ron Dreslinski <rdreslin@umich.edu>

Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory

configs/test/test.py:
Update to use new cpu getPort functionality
src/cpu/base.cc:
Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
Make sure the cache recognizes all port names

2846:89fbe74d8ea8 06-Jul-2006 Ali Saidi <saidi@eecs.umich.edu>

Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
change naming for pio port
break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
src/dev/sinic.cc:
remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
add idea of default responder to bus
src/python/m5/objects/Pci.py:
add config port for pci devices
add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

2833:14c66b81e7ce 03-Jul-2006 Korey Sewell <ksewell@umich.edu>

Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.

Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2"

I think I am a novice python magician now!!!!....

configs/test/test.py:
Added hook to check for SMT workloads. SMT is identified by adding a semicolon between
the workloads.

Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2"
(btw, We are back to working for this double hello world case)

I am a novice python magician now!!!!....

2807:79f9f813c9bd 27-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

Add help strings for options

2804:9a62879d10f1 26-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

Merge zizzer:/bk/newmem
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem

2801:26e01d3c7376 26-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

add python options for input file and command line options for live process

2787:1ed6ddeca640 18-Jun-2006 Korey Sewell <ksewell@umich.edu>

use 'tick' instead of 'cycle'

2784:6cff1a1c2935 18-Jun-2006 Ali Saidi <saidi@eecs.umich.edu>

minor device fixups

configs/test/SysPaths.py:
remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
move DmaReqState into DmaDevie

2774:26bd53d9b2bd 17-Jun-2006 Nathan Binkert <binkertn@umich.edu>

Make the system paths more configurable

configs/test/SysPaths.py:
Make the paths more configurable

2762:470f9e55fe54 17-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Add --outdir option. Didn't call it "-d" since
that's already being used for "detailed cpu".
Needed to add extra function for user script
to pass parsed options back to m5 module.

configs/test/fs.py:
configs/test/test.py:
Call setStandardOptions().
src/python/m5/__init__.py:
Add --outdir option.
Add setStandardOptions() so user script can
pass parsed options back to m5 module.
src/sim/main.cc:
Add SWIG-wrappable function to set output dir.

2758:2341f6fc73b7 16-Jun-2006 Kevin Lim <ktlim@umich.edu>

Update this with the same option as single_fs.py

2757:58e3a66e72f7 16-Jun-2006 Kevin Lim <ktlim@umich.edu>

Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

2755:483dfd490d7e 15-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

2753:5e20ecdb624f 14-Jun-2006 Korey Sewell <ksewell@umich.edu>

tried to undo change and it didnt work so might as well put it back

2752:bab8e4b448ce 14-Jun-2006 Korey Sewell <ksewell@umich.edu>

change back, BK is acting up

2751:4f7d9ca761f4 14-Jun-2006 Korey Sewell <ksewell@umich.edu>

add cycle to exit message

src/arch/mips/isa/formats/trap.isa:
Take out fix that tried to fix trap
instruction disassembly. It forces bad
compile ..
configs/test/test.py:
add 'cycle' to exit message

2740:1c2058745499 15-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Get Port stuff working with full-system scripts.
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.

configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.

2738:5d7a31c7fa29 13-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Move SimObject creation and Port connection loops
into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.

configs/test/fs.py:
configs/test/test.py:
Rewrite for new port connector syntax.
src/SConscript:
Remove unneeded files:
- mem/connector.*
- sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
Allow getPort() to take an optional index to
support vector ports (eventually).
src/python/m5/__init__.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
src/python/m5/config.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Add support for declaring and connecting MemObject
ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
ConfigNodes are gone; builder just gets the
name of a .ini file section now.
src/sim/main.cc:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Split remaining initialization operations into two parts,
loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
SimObject resolution done globally in Python now
(not via ConfigNode hierarchy).
src/sim/sim_object.cc:
Remove unneeded #include.

2733:e0eac8fc5774 16-Jun-2006 Kevin Lim <ktlim@umich.edu>

Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble.

First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.

Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.

SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.

Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.

2724:8affbecf6983 13-Jun-2006 Kevin Lim <ktlim@umich.edu>

Add in DetailedCPU to test.

2715:4032e02b525e 11-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Move LiveProcess::create() from arch-specific files
bcak to main LiveProcess, then automatically select
ISA based on object file type. Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().

configs/test/test.py:
Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
Move create() from arch-specific files back to
main LiveProcess, then automatically select ISA
based on object file type.

2712:aa0891b4a110 10-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Don't allow SimObject-valued class params to be set
after the class has been instantiated or subclassed.
This is one of the main situations that leads to
confusing results.

configs/test/fs.py:
Clean up to avoid modifying BaseCPU after it's been subclassed.

2710:33af9611cf2a 10-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Update scripts for testing ALPHA_FS and MIPS_SE.
Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.

configs/test/fs.py:
Port to new script interface/model.
configs/test/test.py:
Add support for running MIPS test(s) too via
command-line option.
src/arch/alpha/ev5.cc:
Fix include file.
src/arch/sparc/regfile.hh:
Make Bit64 a ULL constant to avoid compiler error.

2667:fe64b8353b1c 09-Jun-2006 Steve Reinhardt <stever@eecs.umich.edu>

Move main control from C++ into Python.
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.

SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.


/gem5/SConstruct
test/test.py
/gem5/src/SConscript
/gem5/src/arch/SConscript
/gem5/src/arch/alpha/ev5.cc
/gem5/src/arch/alpha/isa/decoder.isa
/gem5/src/cpu/base.cc
/gem5/src/cpu/o3/alpha_cpu_impl.hh
/gem5/src/cpu/trace/opt_cpu.cc
/gem5/src/cpu/trace/trace_cpu.cc
/gem5/src/python/SConscript
/gem5/src/python/m5/__init__.py
/gem5/src/python/m5/config.py
/gem5/src/python/m5/objects/AlphaConsole.py
/gem5/src/python/m5/objects/AlphaFullCPU.py
/gem5/src/python/m5/objects/AlphaTLB.py
/gem5/src/python/m5/objects/BadDevice.py
/gem5/src/python/m5/objects/BaseCPU.py
/gem5/src/python/m5/objects/BaseCache.py
/gem5/src/python/m5/objects/Bridge.py
/gem5/src/python/m5/objects/Bus.py
/gem5/src/python/m5/objects/CoherenceProtocol.py
/gem5/src/python/m5/objects/Device.py
/gem5/src/python/m5/objects/DiskImage.py
/gem5/src/python/m5/objects/Ethernet.py
/gem5/src/python/m5/objects/Ide.py
/gem5/src/python/m5/objects/IntrControl.py
/gem5/src/python/m5/objects/MemObject.py
/gem5/src/python/m5/objects/MemTest.py
/gem5/src/python/m5/objects/Pci.py
/gem5/src/python/m5/objects/PhysicalMemory.py
/gem5/src/python/m5/objects/Platform.py
/gem5/src/python/m5/objects/Process.py
/gem5/src/python/m5/objects/Repl.py
/gem5/src/python/m5/objects/Root.py
/gem5/src/python/m5/objects/SimConsole.py
/gem5/src/python/m5/objects/SimpleDisk.py
/gem5/src/python/m5/objects/System.py
/gem5/src/python/m5/objects/Tsunami.py
/gem5/src/python/m5/objects/Uart.py
/gem5/src/sim/eventq.cc
/gem5/src/sim/eventq.hh
/gem5/src/sim/host.hh
/gem5/src/sim/main.cc
/gem5/src/sim/pseudo_inst.cc
/gem5/src/sim/root.cc
/gem5/src/sim/serialize.cc
/gem5/src/sim/sim_events.cc
/gem5/src/sim/sim_events.hh
/gem5/src/sim/sim_exit.hh
/gem5/src/sim/syscall_emul.cc
2626:7083149c278b 17-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

Get basic full-system working with AtomicSimpleCPU.

SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.

2623:61d9e3f44b40 16-May-2006 Steve Reinhardt <stever@eecs.umich.edu>

Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.

2596:c5801c1088e2 07-May-2006 Korey Sewell <ksewell@umich.edu>

Minor changes for FP ... MIPS now works for floating-point programs...
Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions

arch/mips/isa_traits.hh:
fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
real hello world MIPS binary

2582:ab7177e8de39 28-Apr-2006 Gabe Black <gblack@eecs.umich.edu>

Changed the hello_sparc executable back to the cross compiled one

2577:65fd7f75bbe2 02-May-2006 Korey Sewell <ksewell@umich.edu>

Redo the FloatRegFile using unsigned integers
Edit the convert_and_round function which access FloatRegFile

arch/isa_parser.py:
recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
bit manipulation ourselves. We can just concern ourselves with values.

Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
float debug statement
arch/mips/isa_traits.cc:
add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
basic FP program
cpu/simple/cpu.hh:
spacing

2570:7ae3c61bd433 28-Apr-2006 Ali Saidi <saidi@eecs.umich.edu>

random mix of tidbits

configs/test/fs.py:
update fs.py to use a bus bridge
cpu/simple/cpu.hh:
cpu should just return that it doesn't snoop any address ranges
python/m5/objects/System.py:
move boot_osflags to system

2566:81f2c403dcc6 24-Apr-2006 Ali Saidi <saidi@eecs.umich.edu>

Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
add nics to fs.py
cpu/cpu_exec_context.cc:
remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
use new methods for accessing packet data
dev/ide_disk.cc:
add some more dprintfs
dev/io_device.cc:
delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
dUpdate for new packet methods to access data
dev/ns_gige.cc:
Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
update for new memory system
dev/sinic.cc:
dev/sinic.hh:
Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
Add methods to access data instead of accessing it directly.

2565:f81359e799ea 20-Apr-2006 Ali Saidi <saidi@eecs.umich.edu>

make ide disk work for newmem

SConscript:
compile ide devices
base/chunk_generator.hh:
add another parameter to the chuck generator called complete() which
returns the number of bytes transfered so far. Very useful for
adding to a pointer.
configs/test/fs.py:
Add ide disk to fs test configuration
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
update for new memory system
mem/bus.cc:
support devices that return multiple ranges
remove old ranges before using new info
mem/packet.hh:
make senderstate void* per steve's request that we use every
construct possible in C++
mem/physical.cc:
have memory stamp the packet with the time.
mem/physical.hh:
actually set the memory latency variable
python/m5/objects/Device.py:
Add DmaDevice
python/m5/objects/Ide.py:
Ide disk no longer has a physmem pointer
python/m5/objects/Pci.py:
update pci device for newmem
python/m5/objects/PhysicalMemory.py:
add latency parameter for physical memory
sim/byteswap.hh:
use fast architecture dependent byteswap calls if they exist

2556:71956169e66d 13-Apr-2006 Korey Sewell <ksewell@umich.edu>

update Hello World binary for mips... the old one did not have a newline

2549:ab9be1411b4e 12-Apr-2006 Ali Saidi <saidi@eecs.umich.edu>

fs now gets to the point where it would really like a filesystem.
Time to make the ide device work

arch/alpha/system.cc:
write the machine type and rev in the correct place
cpu/simple/cpu.cc:
reset the packet structure every time it's reused... wow the
simple cpu code for talking to memory is getting horrible.
dev/alpha_console.cc:
move the setAlphaAccess to startup() to make sure that the console
binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
More verbose bus tracing
mem/packet.hh:
Add a constructor to packet to set the result to unknown and a reset
method in the case it's being reused
mem/vport.hh:
don't need are own read/write methods since the base functional port
ones call writeBlob readBlob which do the translation for us

2533:a53cd2339911 06-Apr-2006 Ali Saidi <saidi@eecs.umich.edu>

a sparc binary that can be debugged

2526:5f75dd284194 06-Apr-2006 Gabe Black <gblack@eecs.umich.edu>

Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.

arch/isa_parser.py:
Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
Added SPARC traceflag
configs/test/hello_sparc:
Recompiled without -mflat
cpu/cpu_exec_context.cc:
Used the regfile clear function rather than memsetting to 0.

2516:adad56d7150f 31-Mar-2006 Gabe Black <gblack@eecs.umich.edu>

Fixes to SPARC for syscall emulation mode.

arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
A test program for SPARC which prints "Hello World!"

2514:849fc37c0544 29-Mar-2006 Ali Saidi <saidi@eecs.umich.edu>

update for connector magic

2498:23988f1c090b 25-Mar-2006 Ali Saidi <saidi@eecs.umich.edu>

update for objects having a bus

2474:177b1b416a2c 15-Mar-2006 Ali Saidi <saidi@eecs.umich.edu>

add translations for new sections that are mmapped or when the brk
is changed
Add a default machine width parameter
Arch based live processes

arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed

2473:3269b601f98f 15-Mar-2006 Korey Sewell <ksewell@umich.edu>

add mips simple test in config directory

configs/test/hello_mips:
hello world mips binary

2424:f2dae0cc8548 10-Mar-2006 Steve Reinhardt <stever@eecs.umich.edu>

Compiles now (with CPU_MODELS=SimpleCPU), but hangs
on execution.

configs/test/test.py:
Move test binary out of m5-test, don't depend on
m5-test/Benchmarks.
python/m5/objects/System.py:
Split out full-system-only parameters (lost in merge).
sim/system.cc:
Need to be able to instantiate System directly in SE mode
(lost in merge).
sim/system.hh:
A few more functions here are FS-only.
configs/test/hello:
Add in binary.

2418:d9abbbb22dfe 01-Mar-2006 Steve Reinhardt <stever@eecs.umich.edu>

More progress toward actually running a program.
See configs/test.py for test config (using simple
binary in my home directory on zizzer).

base/chunk_generator.hh:
Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
Fix roundDown to take integer alignments.
cpu/base.cc:
Register exec contexts regardless of state (not sure why
this check was in here in the first place).
mem/physical.cc:
Add breaks to switch.
python/m5/objects/BaseCPU.py:
Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
HierParams is gone.
python/m5/objects/PhysicalMemory.py:
mmu param is full-system only.
sim/process.cc:
Stack mapping request must be page-aligned and page-sized.
Don't delete objFile object in create since we are counting
on it being around for startup().

2366:9ef3fd6c979d 24-Aug-2006 Kevin Lim <ktlim@umich.edu>

Updates to configs to support various sampling forms, truncated execution forms.

2357:add41108b549 11-Aug-2006 Kevin Lim <ktlim@umich.edu>

Add in a bunch more stuff.

configs/boot/micro_memlat.rcS:
Update these scripts so they work (not sure why they broke)
configs/boot/micro_tlblat.rcS:
Update this script to use a different test.

2011:3aa85909e087 29-Nov-2005 Ali Saidi <saidi@eecs.umich.edu>

Add support for multiple streams being configured with the INITPARAM
variable

2000:116d36c17e06 22-Nov-2005 Nathan Binkert <binkertn@umich.edu>

Clean up the newly updated iscsi-client script

configs/boot/iscsi-client.rcS:
Clean up the newly updated iscsi-client script.
Reduce the writeback period so writes occur more frequently.

1942:b29baae4086b 09-Nov-2005 Lisa Hsu <hsul@eecs.umich.edu>

new rcS file for open-iscsi rather than the old linux-iscsi

1878:4a9c959b3e93 16-Sep-2005 Nathan Binkert <binkertn@umich.edu>

various changes to the boot scripts

configs/boot/iscsi-client.rcS:
configs/boot/nfs-client-dbench.rcS:
don't use the /proc/m5 stuff, use the m5 binary
configs/boot/nfs-client-nhfsstone.rcS:
set up checkpoints
change nhfsstone configuration
configs/boot/nfs-client.rcS:
use more memory
configs/boot/nfs-server.rcS:
change the writeback frequency
load a larger simulated disk image.
create more nfsd threads

1787:0dcbb68fbea8 13-Jun-2005 Nathan Binkert <binkertn@umich.edu>

Add NFS-dbench, and iscsi dbench benchmarks

1714:e83b18b0238d 04-Jun-2005 Steve Reinhardt <stever@eecs.umich.edu>

Clean up to work with recent python config changes.

configs/splash2/run.py:
parent is now Parent.
Need to explicitly instantiate classes.

1693:627f0d579dc1 01-Jun-2005 Steve Reinhardt <stever@eecs.umich.edu>

A few more config updates. Works with regression now.

configs/splash2/run.py:
Update file for new config changes.
python/m5/config.py:
- isParamContext() not defined any more
- fix bug with re-assigning vectors over scalars
and vice versa

1648:4214fd0ea44d 30-Apr-2005 Nathan Binkert <binkertn@umich.edu>

Cleanup rcS files. Make sure there are enough tracked connections.
Delay before singalling peer to make sure that the peer is ready

configs/boot/nat-netperf-server.rcS:
delay before singalling to make sure that the natbox is ready
configs/boot/nat-netperf-stream-client.rcS:
increase the number of tracked connections
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-smallb.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
increase the number of tracked connections
cleanup
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections
cleanup
configs/boot/natbox-spec-surge.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections

1645:4efe65fb0bce 28-Apr-2005 Ron Dreslinski <rdreslin@umich.edu>

Make ip_conntrack table size larger

1598:1bc90edc1a86 23-Mar-2005 Ali Saidi <saidi@eecs.umich.edu>

Add some new config files

1569:d98e324566b3 16-Mar-2005 Ron Dreslinski <rdreslin@umich.edu>

Fixed the super/parent change fpr splash2 benchmarks

configs/splash2/run.mpy:
Change super to parent

1516:2e7e1db672dd 11-Mar-2005 Ron Dreslinski <rdreslin@umich.edu>

Added config files for splash2 benchmarks. Parameters:
ROOTDIR = root directory of the splash2 code
NP = number of proccessors
BENCHMARK = name of the splash2 benchmark (Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig, OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial)
SYSTEM = Type of system to simulate detailed or simple

Note: They use MOESI protocol and do_events is enabled (Multiple L1's and a shared L2)

1446:71a5986f7d89 01-Mar-2005 Ali Saidi <saidi@eecs.umich.edu>

Updated Monet Configuration and validations tests

1434:663e4efbbad7 08-Mar-2005 Nathan Binkert <binkertn@umich.edu>

Fix the singalling from server to client so that the
benchmark begins properly.

configs/boot/nat-netperf-maerts-client.rcS:
Fix the echo message
configs/boot/nat-netperf-server.rcS:
Wait a second before signalling the natbox to make sure it's
had time to boot.
Fix echo message.

1425:6c591a4bd6e5 08-Mar-2005 Lisa Hsu <hsul@eecs.umich.edu>

make some changes to bonnie - now that the simulator uses more memory the old config didn't fit anymore in pools VM, this does fit.

1424:0b1fbe98da7d 05-Mar-2005 Lisa Hsu <hsul@eecs.umich.edu>

the client and server aren't rate-matched anymore and the timing of the netcats are off - add a sleep 1 to make it actually work.

1409:1793e6d9d16a 23-Feb-2005 Ali Saidi <saidi@eecs.umich.edu>

added two validation rcs files

1370:2063295aa1ab 03-Feb-2005 Ali Saidi <saidi@eecs.umich.edu>

Add Monet configuration, update p4 parameters, couple of typo fixes

dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.

1362:88a3afa44545 28-Jan-2005 Lisa Hsu <hsul@eecs.umich.edu>

make nat runs used vegas congestion avoidance implementation.

1268:f7d895970715 18-Nov-2004 Nathan Binkert <binkertn@umich.edu>

add a no touch stream benchmark clean up a little

1254:23bee9702f40 17-Nov-2004 Nathan Binkert <binkertn@umich.edu>

Reduce the amount of time we delay when dumping a checkpoint for
netperf runs

configs/boot/nat-netperf-maerts-client.rcS:
configs/boot/nat-netperf-stream-client.rcS:
configs/boot/netperf-maerts-client.rcS:
configs/boot/netperf-rr.rcS:
configs/boot/netperf-stream-client.rcS:
dont' delay for so long when dumping a checkpoint

1242:c7f56fec0cb2 17-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

fixed swap disk, now it doesn't have a partition table

1238:32fc21b02f44 17-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

Add the boot scripts for nfs tcp

1228:6a111cd15e97 12-Nov-2004 Ron Dreslinski <rdreslin@umich.edu>

Merge zizzer:/z/m5/Bitkeeper/m5
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean

1215:7fac56db1554 17-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

added small block nfs script

1198:03d7b4ccde82 16-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

skip the nfs charecter by charecter and re-write stuff

configs/boot/nfs-client.rcS:
skip the charecter and rewrite test

1196:5e20797f314a 16-Nov-2004 Lisa Hsu <hsul@eecs.umich.edu>

add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.

1187:bcc6d5a1f6e4 16-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

fixed for 768MB runs

1177:f8fe8072dc6d 15-Nov-2004 Nathan Binkert <binkertn@umich.edu>

Fix up the spec-surge benchmark

configs/boot/spec-surge-client.rcS:
change the number of connections and add stuff for the
file set size and checkpointing

1175:aaaf335c2daf 15-Nov-2004 Nathan Binkert <binkertn@umich.edu>

more whitespace fixes

configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
whitespace fixes

1174:39b083b96a64 15-Nov-2004 Nathan Binkert <binkertn@umich.edu>

more formatting

configs/boot/nfs-server.rcS:
fix whitespace

1173:457555fc3642 15-Nov-2004 Nathan Binkert <binkertn@umich.edu>

formatting

configs/boot/nfs-client.rcS:
fix whitespace

1172:485932298c56 15-Nov-2004 Nathan Binkert <binkertn@umich.edu>

cleanup the nfs server script

configs/boot/nfs-server.rcS:
don't need extra IP aliases

re-order the nfs daemons so they happen in the right order
and don't have the shell put them in the background since they
will auto detach anyway.

1160:ece5a439d929 13-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

patched nfs boot scripts

configs/boot/nfs-server.rcS:
made the partition size correct

1159:8322fba51266 13-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

fixed nfs scripts hopefully for the last time

configs/boot/nfs-client.rcS:
lucky #3

1142:f31491939594 12-Nov-2004 Lisa Hsu <hsul@eecs.umich.edu>

add surge and spec-surge readfiles. also make the naming system uniform, there were 3 different ways!!! i like ali's.

1141:21a12736d567 12-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

slightly different parameters for nfs script

1140:152abf03905a 12-Nov-2004 Ali Saidi <saidi@eecs.umich.edu>

Added nfs-client.rcS and nfs-server.rcS

1058:4717c6cc329d 11-Aug-2004 Nathan Binkert <binkertn@umich.edu>

commented script with various kernel parameter tweaks for better
network performance

1050:d462c4654cb4 10-Aug-2004 Nathan Binkert <binkertn@umich.edu>

tweak a bunch of kernel parameters to get better performance

999:d44f44443721 14-Jul-2004 Nathan Binkert <binkertn@umich.edu>

fix paths for changes in disk image layout

978:b08a4d98599e 08-Jul-2004 Nathan Binkert <binkertn@umich.edu>

Scripts that can be used with server.readfile and client.readfile
to run the netperf benchmark