---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated sim_ticks 262970500 # Number of ticks simulated final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 110323 # Simulator instruction rate (inst/s) host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) host_tick_rate 43749084 # Simulator tick rate (ticks/s) host_mem_usage 287188 # Number of bytes of host memory used host_seconds 6.01 # Real time elapsed on the host sim_insts 663135 # Number of instructions simulated sim_ops 663135 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls system.cpu0.numCycles 525941 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158580 # Number of instructions committed system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls system.cpu0.num_int_insts 109212 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_mem_refs 74024 # number of memory refs system.cpu0.num_load_insts 49009 # Number of load instructions system.cpu0.num_store_insts 25015 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles system.cpu0.num_busy_cycles 525941 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits system.cpu0.icache.overall_hits::total 158176 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17209000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 17209000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36850.107066 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits system.cpu0.dcache.demand_hits::cpu0.data 73608 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 73608 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 73608 # number of overall hits system.cpu0.dcache.overall_hits::total 73608 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 171 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 184 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 184 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses system.cpu0.dcache.overall_misses::total 355 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4683500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 4683500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7047500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 7047500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 364500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 364500 # number of SwapReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 11731000 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 11731000 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 11731000 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 11731000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48999 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 525940 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 166746 # Number of instructions committed system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls system.cpu1.num_int_insts 110403 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written system.cpu1.num_mem_refs 54388 # number of memory refs system.cpu1.num_load_insts 40871 # Number of load instructions system.cpu1.num_store_insts 13517 # Number of store instructions system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits system.cpu1.icache.overall_hits::total 166413 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 7565000 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 7565000 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 7565000 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 7565000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 166779 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 166779 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 166779 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 166779 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 166779 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 166779 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002195 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 20669.398907 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6833000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 6833000 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6833000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 6833000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6833000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 6833000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002195 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002195 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002195 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18669.398907 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements system.cpu1.dcache.tagsinuse 27.686467 # Cycle average of tags in use system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.occ_blocks::cpu1.data 27.686467 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.054075 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.054075 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40710 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40710 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 13344 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 13344 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits system.cpu1.dcache.demand_hits::cpu1.data 54054 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 54054 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 54054 # number of overall hits system.cpu1.dcache.overall_hits::total 54054 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses system.cpu1.dcache.overall_misses::total 259 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2954500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2954500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1962000 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 1962000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 274000 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 274000 # number of SwapReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 4916500 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 4916500 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 4916500 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 4916500 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 40863 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 40863 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 13450 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 13450 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 525941 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.committedInsts 169995 # Number of instructions committed system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls system.cpu2.num_int_insts 110917 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written system.cpu2.num_mem_refs 53535 # number of memory refs system.cpu2.num_load_insts 41127 # Number of load instructions system.cpu2.num_store_insts 12408 # Number of store instructions system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits system.cpu2.icache.overall_hits::total 169662 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5281000 # number of ReadReq miss cycles system.cpu2.icache.ReadReq_miss_latency::total 5281000 # number of ReadReq miss cycles system.cpu2.icache.demand_miss_latency::cpu2.inst 5281000 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_latency::total 5281000 # number of demand (read+write) miss cycles system.cpu2.icache.overall_miss_latency::cpu2.inst 5281000 # number of overall miss cycles system.cpu2.icache.overall_miss_latency::total 5281000 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 170028 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 170028 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 170028 # number of demand (read+write) accesses system.cpu2.icache.demand_accesses::total 170028 # number of demand (read+write) accesses system.cpu2.icache.overall_accesses::cpu2.inst 170028 # number of overall (read+write) accesses system.cpu2.icache.overall_accesses::total 170028 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002153 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002153 # miss rate for demand accesses system.cpu2.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002153 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14428.961749 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_miss_latency::total 14428.961749 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency system.cpu2.icache.demand_avg_miss_latency::total 14428.961749 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14428.961749 # average overall miss latency system.cpu2.icache.overall_avg_miss_latency::total 14428.961749 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4549000 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_latency::total 4549000 # number of ReadReq MSHR miss cycles system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4549000 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.demand_mshr_miss_latency::total 4549000 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4549000 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4549000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002153 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average ReadReq mshr miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12428.961749 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12428.961749 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12428.961749 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements system.cpu2.dcache.tagsinuse 25.908378 # Cycle average of tags in use system.cpu2.dcache.total_refs 27066 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 933.310345 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.occ_blocks::cpu2.data 25.908378 # Average occupied blocks per requestor system.cpu2.dcache.occ_percent::cpu2.data 0.050602 # Average percentage of cache occupancy system.cpu2.dcache.occ_percent::total 0.050602 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 40963 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 40963 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 12235 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 12235 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits system.cpu2.dcache.demand_hits::cpu2.data 53198 # number of demand (read+write) hits system.cpu2.dcache.demand_hits::total 53198 # number of demand (read+write) hits system.cpu2.dcache.overall_hits::cpu2.data 53198 # number of overall hits system.cpu2.dcache.overall_hits::total 53198 # number of overall hits system.cpu2.dcache.ReadReq_misses::cpu2.data 157 # number of ReadReq misses system.cpu2.dcache.ReadReq_misses::total 157 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses system.cpu2.dcache.overall_misses::total 262 # number of overall misses system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2754500 # number of ReadReq miss cycles system.cpu2.dcache.ReadReq_miss_latency::total 2754500 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1914500 # number of WriteReq miss cycles system.cpu2.dcache.WriteReq_miss_latency::total 1914500 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 286000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 286000 # number of SwapReq miss cycles system.cpu2.dcache.demand_miss_latency::cpu2.data 4669000 # number of demand (read+write) miss cycles system.cpu2.dcache.demand_miss_latency::total 4669000 # number of demand (read+write) miss cycles system.cpu2.dcache.overall_miss_latency::cpu2.data 4669000 # number of overall miss cycles system.cpu2.dcache.overall_miss_latency::total 4669000 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 41120 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 41120 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 12340 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 12340 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.demand_accesses::cpu2.data 53460 # number of demand (read+write) accesses system.cpu2.dcache.demand_accesses::total 53460 # number of demand (read+write) accesses system.cpu2.dcache.overall_accesses::cpu2.data 53460 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 53460 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003818 # miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_miss_rate::total 0.003818 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008509 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.008509 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.772727 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.772727 # miss rate for SwapReq accesses system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004901 # miss rate for demand accesses system.cpu2.dcache.demand_miss_rate::total 0.004901 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004901 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.004901 # miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17544.585987 # average ReadReq miss latency system.cpu2.dcache.ReadReq_avg_miss_latency::total 17544.585987 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18233.333333 # average WriteReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency::total 18233.333333 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5607.843137 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 5607.843137 # average SwapReq miss latency system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency system.cpu2.dcache.demand_avg_miss_latency::total 17820.610687 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17820.610687 # average overall miss latency system.cpu2.dcache.overall_avg_miss_latency::total 17820.610687 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2440500 # number of ReadReq MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2440500 # number of ReadReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704500 # number of WriteReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704500 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 184000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 184000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4145000 # number of demand (read+write) MSHR miss cycles system.cpu2.dcache.demand_mshr_miss_latency::total 4145000 # number of demand (read+write) MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4145000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_miss_latency::total 4145000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003818 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008509 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008509 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.772727 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for demand accesses system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency system.cpu2.dcache.demand_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 525940 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu3.committedInsts 167814 # Number of instructions committed system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls system.cpu3.num_int_insts 111369 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions system.cpu3.num_int_register_reads 278793 # number of times the integer registers were read system.cpu3.num_int_register_writes 105918 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written system.cpu3.num_mem_refs 55316 # number of memory refs system.cpu3.num_load_insts 41342 # Number of load instructions system.cpu3.num_store_insts 13974 # Number of store instructions system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 167480 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 167480 # number of demand (read+write) hits system.cpu3.icache.demand_hits::total 167480 # number of demand (read+write) hits system.cpu3.icache.overall_hits::cpu3.inst 167480 # number of overall hits system.cpu3.icache.overall_hits::total 167480 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5162000 # number of ReadReq miss cycles system.cpu3.icache.ReadReq_miss_latency::total 5162000 # number of ReadReq miss cycles system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4428000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_latency::total 4428000 # number of ReadReq MSHR miss cycles system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4428000 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4428000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002187 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.002187 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.002187 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12065.395095 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements system.cpu3.dcache.tagsinuse 26.814972 # Cycle average of tags in use system.cpu3.dcache.total_refs 30179 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu3.dcache.avg_refs 1040.655172 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.occ_blocks::cpu3.data 26.814972 # Average occupied blocks per requestor system.cpu3.dcache.occ_percent::cpu3.data 0.052373 # Average percentage of cache occupancy system.cpu3.dcache.occ_percent::total 0.052373 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41164 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41164 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 13787 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 13787 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 10 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 10 # number of SwapReq hits system.cpu3.dcache.demand_hits::cpu3.data 54951 # number of demand (read+write) hits system.cpu3.dcache.demand_hits::total 54951 # number of demand (read+write) hits system.cpu3.dcache.overall_hits::cpu3.data 54951 # number of overall hits system.cpu3.dcache.overall_hits::total 54951 # number of overall hits system.cpu3.dcache.ReadReq_misses::cpu3.data 171 # number of ReadReq misses system.cpu3.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 106 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 106 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses system.cpu3.dcache.demand_misses::cpu3.data 277 # number of demand (read+write) misses system.cpu3.dcache.demand_misses::total 277 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 277 # number of overall misses system.cpu3.dcache.overall_misses::total 277 # number of overall misses system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2803500 # number of ReadReq miss cycles system.cpu3.dcache.ReadReq_miss_latency::total 2803500 # number of ReadReq miss cycles system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2201500 # number of WriteReq miss cycles system.cpu3.dcache.WriteReq_miss_latency::total 2201500 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 368000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 368000 # number of SwapReq miss cycles system.cpu3.dcache.demand_miss_latency::cpu3.data 5005000 # number of demand (read+write) miss cycles system.cpu3.dcache.demand_miss_latency::total 5005000 # number of demand (read+write) miss cycles system.cpu3.dcache.overall_miss_latency::cpu3.data 5005000 # number of overall miss cycles system.cpu3.dcache.overall_miss_latency::total 5005000 # number of overall miss cycles system.cpu3.dcache.ReadReq_accesses::cpu3.data 41335 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 41335 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 13893 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::total 13893 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.demand_accesses::cpu3.data 55228 # number of demand (read+write) accesses system.cpu3.dcache.demand_accesses::total 55228 # number of demand (read+write) accesses system.cpu3.dcache.overall_accesses::cpu3.data 55228 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55228 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004137 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_miss_rate::total 0.004137 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007630 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.007630 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.873418 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.873418 # miss rate for SwapReq accesses system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005016 # miss rate for demand accesses system.cpu3.dcache.demand_miss_rate::total 0.005016 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005016 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.005016 # miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16394.736842 # average ReadReq miss latency system.cpu3.dcache.ReadReq_avg_miss_latency::total 16394.736842 # average ReadReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20768.867925 # average WriteReq miss latency system.cpu3.dcache.WriteReq_avg_miss_latency::total 20768.867925 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5333.333333 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 5333.333333 # average SwapReq miss latency system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency system.cpu3.dcache.demand_avg_miss_latency::total 18068.592058 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency system.cpu3.dcache.overall_avg_miss_latency::total 18068.592058 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 171 # number of ReadReq MSHR misses system.cpu3.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2461500 # number of ReadReq MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2461500 # number of ReadReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1989500 # number of WriteReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1989500 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 230000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 230000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4451000 # number of demand (read+write) MSHR miss cycles system.cpu3.dcache.demand_mshr_miss_latency::total 4451000 # number of demand (read+write) MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4451000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_miss_latency::total 4451000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004137 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004137 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007630 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007630 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.873418 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.873418 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for demand accesses system.cpu3.dcache.demand_mshr_miss_rate::total 0.005016 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_miss_rate::total 0.005016 # mshr miss rate for overall accesses system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14394.736842 # average ReadReq mshr miss latency system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14394.736842 # average ReadReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18768.867925 # average WriteReq mshr miss latency system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18768.867925 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3333.333333 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3333.333333 # average SwapReq mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16068.592058 # average overall mshr miss latency system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16068.592058 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16068.592058 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16068.592058 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements system.l2c.tagsinuse 349.061652 # Cycle average of tags in use system.l2c.total_refs 1220 # Total number of references to valid blocks. system.l2c.sampled_refs 429 # Sample count of references to valid blocks. system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 0.889079 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 231.800504 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 54.209816 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 51.703511 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 6.143370 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.inst 1.773026 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.data 0.811968 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.886563 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.843815 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000789 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.005326 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 300 # number of overall hits system.l2c.overall_hits::cpu1.data 3 # number of overall hits system.l2c.overall_hits::cpu2.inst 354 # number of overall hits system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses system.l2c.demand_misses::total 592 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 285 # number of overall misses system.l2c.overall_misses::cpu0.data 165 # number of overall misses system.l2c.overall_misses::cpu1.inst 66 # number of overall misses system.l2c.overall_misses::cpu1.data 23 # number of overall misses system.l2c.overall_misses::cpu2.inst 12 # number of overall misses system.l2c.overall_misses::cpu2.data 16 # number of overall misses system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14917500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.inst 3455000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 419000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 568500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 100000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.inst 385500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 95500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 23392500 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5174000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 784500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 741000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 7439500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.inst 14917500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8625500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 3455000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 1203500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 568500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 841000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.inst 385500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 835500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 30832000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.inst 14917500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8625500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 3455000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 1203500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 568500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 841000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.inst 385500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 835500 # number of overall miss cycles system.l2c.overall_miss_latency::total 30832000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # 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miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52342.105263 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52348.484848 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 47375 # 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number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 609500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.727273 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.975610 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------