---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 22159 # Simulator instruction rate (inst/s) host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) host_tick_rate 79599293 # Simulator tick rate (ticks/s) host_mem_usage 246136 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory system.physmem.bytes_read::total 25152 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 393 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 25152 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry system.physmem.totGap 16436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 393 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation system.physmem.totQLat 2047500 # Total cycles spent in queuing delays system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests system.physmem.totBusLat 1965000 # Total cycles spent in databus access system.physmem.totBankLat 5445000 # Total cycles spent in bank access system.physmem.avgQLat 5209.92 # Average queueing delay per request system.physmem.avgBankLat 13854.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 24064.89 # Average memory access latency system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.91 # Data bus utilization in percentage system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 41823.16 # Average gap between requests system.membus.throughput 1524918152 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 352 # Transaction distribution system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution system.membus.trans_dist::ReadExResp 41 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 22.3 # Layer utilization (%) system.cpu.branchPred.lookups 2479 # Number of BP lookups system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls system.cpu.numCycles 32989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2420 # Number of cycles decode is running system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2221 # Number of cycles rename is running system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8917 # Type of FU issued system.cpu.iq.rate 0.270302 # Inst issue rate system.cpu.iq.fu_busy_cnt 222 # FU busy when requested system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3296 # number of memory reference insts executed system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed system.cpu.iew.exec_rate 0.258268 # Inst execution rate system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8067 # cumulative count of insts written-back system.cpu.iew.wb_producers 3881 # num instructions producing a value system.cpu.iew.wb_consumers 7779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2138 # Number of memory references committed system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.branches 1007 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 23271 # The number of ROB reads system.cpu.rob.rob_writes 23399 # The number of ROB writes system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39193 # number of integer regfile reads system.cpu.int_regfile_writes 7983 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2975 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 4 # number of replacements system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits system.cpu.icache.overall_hits::total 1583 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits system.cpu.l2cache.overall_hits::total 40 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 398 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses system.cpu.dcache.overall_misses::total 497 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ----------